uart_dm: Add dsb() barrier.

Add dsb instructions to make sure correct sequence of uart intialization.

Change-Id: I5a9bcc924c7df7297e3ea06c3b050ff1d01bf311
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index 0a7aedc..01cf5a4 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -44,6 +44,8 @@
 #define NULL        0

 #endif

 

+extern void dsb(void);

+

 /* Note:

  * This is a basic implementation of UART_DM protocol. More focus has been

  * given on simplicity than efficiency. Few of the things to be noted are:

@@ -129,10 +131,12 @@
 {

     /* Configure the uart clock */

     clock_config_uart_dm(id);

+    dsb();

 

     /* Configure GPIO to provide connectivity between GSBI

        product ports and chip pads */

     gpio_config_uart_dm(id);

+    dsb();

 

     /* Configure Data Mover for GSBI operation.

      * Currently not supported. */

@@ -141,11 +145,13 @@
      * I2C on 2 ports, UART (without HS flow control) on the other 2. */

     writel(GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S,

            GSBI_CTRL_REG(id));

+    dsb();

 

-	/* Configure clock selection register for tx and rx rates.

-	 * Selecting 115.2k for both RX and TX.

-	 */

-	writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id));

+    /* Configure clock selection register for tx and rx rates.

+     * Selecting 115.2k for both RX and TX.

+     */

+    writel(UART_DM_CLK_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR(id));

+    dsb();

 

     return MSM_BOOT_UART_DM_E_SUCCESS;

 }