platform: pll: Explicitly turn off DSI PLL 1 for 20nm PHY
The DSI PLL phy drains some current in its reset state. We need to
manually turn off the DSI1 PLL even if its not enabled. This helps
fix the power leak issue seen during the first kernel boot if
continuous splash feature is enabled.
Change-Id: Id3cceb6f40698dbd8fbfc95bcfb36728db3bd3bf
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index 754eb18..0f7052a 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -227,6 +227,15 @@
pll_20nm_phy_loop_bw_config(pll_base);
}
+static void mdss_dsi_pll_20nm_disable(uint32_t pll_base)
+{
+ dprintf(SPEW, "Disabling DSI PHY PLL \n");
+ writel(0x042, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x002, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+ writel(0x002, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ dmb();
+}
+
int32_t mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
struct mdss_dsi_pll_config *pd)
{
@@ -235,6 +244,15 @@
mdss_dsi_phy_sw_reset(ctl_base);
pll_20nm_phy_config(pll_base);
+ /*
+ * For 20nm PHY, DSI PLL 1 drains some current in its reset state.
+ * Need to turn off the DSI1 PLL explicitly.
+ */
+ if (ctl_base == MIPI_DSI0_BASE) {
+ dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
+ mdss_dsi_pll_20nm_disable(DSI1_PLL_BASE);
+ }
+
/* set up divider */
data = readl(pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
data |= 0x080; /* bit 7 */