commit b4275f1a0276102c252270a74d4d40c7bd8644e7
author Channagoud Kadabi <ckadabi@codeaurora.org> Sat Aug 15 13:06:47 2015 -0700
committer Channagoud Kadabi <ckadabi@codeaurora.org> Sat Aug 15 13:06:47 2015 -0700
tree bb80e5cc1ed814bb648502b2777f8d81661b4be5
parent aeefe92f7d672219b66378b181b141b89580002b

platform: msm_shared: Fix the mask value for cfg register

The mask value for config register is 0x3 in the existing implementation
should be 0x7 instead because of this bits 8 to 10 of the config register
is getting update wrongly while lk updates the clock divider value
resulting in issues with rcg clock rate updates.

Change-Id: I0d161bf08915af7f6e0a0477ca2cc92c95948f16

platform/msm_shared/include/clock_lib2.h

diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index 6b07d45..6023044 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -106,7 +106,7 @@
 #define CFG_SRC_DIV_MASK        (0x1F << CFG_SRC_DIV_OFFSET)
 
 #define CFG_SRC_SEL_OFFSET      8
-#define CFG_SRC_SEL_MASK        (0x3 << CFG_SRC_SEL_OFFSET)
+#define CFG_SRC_SEL_MASK        (0x7 << CFG_SRC_SEL_OFFSET)
 
 #define CFG_MODE_DUAL_EDGE      0x2