diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index bad5743..c50fef7 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -34,6 +34,71 @@
 
 #define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
 
+#define REG_MM(off)                     (MSM_MMSS_CLK_CTL_BASE + (off))
+
+#define MDP_GDSCR                       REG_MM(0x2304)
+#define GDSC_POWER_ON_BIT               BIT(31)
+#define GDSC_POWER_ON_STATUS_BIT        BIT(29)
+#define GDSC_EN_FEW_WAIT_MASK           (0x0F << 16)
+#define GDSC_EN_FEW_WAIT_256_MASK       BIT(19)
+
+#define VSYNC_CMD_RCGR                  REG_MM(0x2080)
+#define VSYNC_CFG_RCGR                  REG_MM(0x2084)
+#define MDSS_VSYNC_CBCR                 REG_MM(0x2328)
+#define MDP_CMD_RCGR                    REG_MM(0x2040)
+#define MDP_CFG_RCGR                    REG_MM(0x2044)
+#define MDP_CBCR                        REG_MM(0x231C)
+#define MDP_LUT_CBCR                    REG_MM(0x2320)
+#define MDP_AHB_CBCR                    REG_MM(0x2308)
+
+#define MDP_AXI_CMD_RCGR                REG_MM(0x5040)
+#define MDP_AXI_CFG_RCGR                REG_MM(0x5044)
+
+#define MDP_AXI_CBCR                    REG_MM(0x2310)
+#define MMSS_S0_AXI_CBCR                REG_MM(0x5064)
+#define MMSS_MMSSNOC_AXI_CBCR           REG_MM(0x506C)
+
+#define DSI_BYTE0_CMD_RCGR              REG_MM(0x2120)
+#define DSI_BYTE0_CFG_RCGR              REG_MM(0x2124)
+#define DSI_BYTE0_CBCR                  REG_MM(0x233C)
+#define DSI_ESC0_CMD_RCGR               REG_MM(0x2160)
+#define DSI_ESC0_CFG_RCGR               REG_MM(0x2164)
+#define DSI_ESC0_CBCR                   REG_MM(0x2344)
+#define DSI_PIXEL0_CMD_RCGR             REG_MM(0x2000)
+#define DSI_PIXEL0_CFG_RCGR             REG_MM(0x2004)
+#define DSI_PIXEL0_CBCR                 REG_MM(0x2314)
+#define DSI_PIXEL0_M                    REG_MM(0x2008)
+#define DSI_PIXEL0_N                    REG_MM(0x200C)
+#define DSI_PIXEL0_D                    REG_MM(0x2010)
+
+#define DSI0_PHY_PLL_OUT                BIT(8)
+#define PIXEL_SRC_DIV_1_5               BIT(1)
+
+#define DSI_BYTE1_CMD_RCGR              REG_MM(0x2140)
+#define DSI_BYTE1_CFG_RCGR              REG_MM(0x2144)
+#define DSI_BYTE1_CBCR                  REG_MM(0x2340)
+#define DSI_ESC1_CMD_RCGR               REG_MM(0x2180)
+#define DSI_ESC1_CFG_RCGR               REG_MM(0x2184)
+#define DSI_ESC1_CBCR                   REG_MM(0x2348)
+#define DSI_PIXEL1_CMD_RCGR             REG_MM(0x2020)
+#define DSI_PIXEL1_CFG_RCGR             REG_MM(0x2024)
+#define DSI_PIXEL1_CBCR                 REG_MM(0x2318)
+#define DSI_PIXEL1_M                    REG_MM(0x2028)
+#define DSI_PIXEL1_N                    REG_MM(0x202C)
+#define DSI_PIXEL1_D                    REG_MM(0x2030)
+
+#define MDSS_EDPPIXEL_CBCR              REG_MM(0x232C)
+#define MDSS_EDPLINK_CBCR               REG_MM(0x2330)
+#define MDSS_EDPAUX_CBCR                REG_MM(0x2334)
+#define EDPPIXEL_M                      REG_MM(0x20A8)
+#define EDPPIXEL_N                      REG_MM(0x20AC)
+#define EDPPIXEL_D                      REG_MM(0x20B0)
+#define EDPPIXEL_CFG_RCGR               REG_MM(0x20A4)
+#define EDPPIXEL_CMD_RCGR               REG_MM(0x20A0)
+#define EDPLINK_CFG_RCGR                REG_MM(0x20C4)
+#define EDPLINK_CMD_RCGR                REG_MM(0x20C0)
+#define EDPAUX_CFG_RCGR                 REG_MM(0x20E4)
+#define EDPAUX_CMD_RCGR                 REG_MM(0x20E0)
 
 void platform_clock_init(void);
 
diff --git a/platform/msm8994/include/platform/iomap.h b/platform/msm8994/include/platform/iomap.h
index 2040d4a..a471def 100644
--- a/platform/msm8994/include/platform/iomap.h
+++ b/platform/msm8994/include/platform/iomap.h
@@ -209,4 +209,64 @@
 #define PLATFORM_QMP_OFFSET                  0x8
 
 #define SMEM_TARG_INFO_ADDR                  0xFE805FF0
+
+/* Display */
+#define EDP_BASE                    0xFD990000
+
+#define SOFT_RESET                  0x118
+#define CLK_CTRL                    0x11C
+#define TRIG_CTRL                   0x084
+#define CTRL                        0x004
+#define COMMAND_MODE_DMA_CTRL       0x03C
+#define COMMAND_MODE_MDP_CTRL       0x040
+#define COMMAND_MODE_MDP_DCS_CMD_CTRL   0x044
+#define COMMAND_MODE_MDP_STREAM0_CTRL   0x058
+#define COMMAND_MODE_MDP_STREAM0_TOTAL  0x05C
+#define COMMAND_MODE_MDP_STREAM1_CTRL   0x060
+#define COMMAND_MODE_MDP_STREAM1_TOTAL  0x064
+#define ERR_INT_MASK0               0x10C
+
+#define LANE_SWAP_CTL               0x0B0
+#define TIMING_CTL                  0x0C4
+
+#define VIDEO_MODE_ACTIVE_H         0x024
+#define VIDEO_MODE_ACTIVE_V         0x028
+#define VIDEO_MODE_TOTAL            0x02C
+#define VIDEO_MODE_HSYNC            0x030
+#define VIDEO_MODE_VSYNC            0x034
+#define VIDEO_MODE_VSYNC_VPOS       0x038
+
+/* MDSS */
+#define MSM_MMSS_CLK_CTL_BASE       0xFD8C0000
+#define MIPI_DSI_BASE               0xFD998000
+#define MIPI_DSI0_BASE              (MIPI_DSI_BASE)
+#define MIPI_DSI1_BASE              0xFD9A0000
+#define DSI0_PHY_BASE               0xFD998500
+#define DSI1_PHY_BASE               0xFD9A0500
+#define DSI0_PLL_BASE               0xFD998300
+#define DSI1_PLL_BASE               0xFD9A0300
+#define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
+#define MDP_BASE                    (0xfd900000)
+#define REG_MDP(off)                (MDP_BASE + (off))
+#define MDP_VP_0_VIG_0_BASE         REG_MDP(0x1200)
+#define MDP_VP_0_VIG_1_BASE         REG_MDP(0x1600)
+#define MDP_VP_0_RGB_0_BASE         REG_MDP(0x2200)
+#define MDP_VP_0_RGB_1_BASE         REG_MDP(0x2600)
+#define MDP_VP_0_DMA_0_BASE         REG_MDP(0x3200)
+#define MDP_VP_0_DMA_1_BASE         REG_MDP(0x3600)
+#define MDP_VP_0_MIXER_0_BASE       REG_MDP(0x3A00)
+#define MDP_VP_0_MIXER_1_BASE       REG_MDP(0x3E00)
+
+#define DMA_CMD_OFFSET              0x048
+#define DMA_CMD_LENGTH              0x04C
+
+#define INT_CTRL                    0x110
+#define CMD_MODE_DMA_SW_TRIGGER     0x090
+
+#define EOT_PACKET_CTRL             0x0CC
+#define MISR_CMD_CTRL               0x0A0
+#define MISR_VIDEO_CTRL             0x0A4
+#define VIDEO_MODE_CTRL             0x010
+#define HS_TIMER_CTRL               0x0BC
+
 #endif
diff --git a/platform/msm8994/msm8994-clock.c b/platform/msm8994/msm8994-clock.c
index 68343bf..033a88d 100644
--- a/platform/msm8994/msm8994-clock.c
+++ b/platform/msm8994/msm8994-clock.c
@@ -45,6 +45,8 @@
 #define mmpll1_mm_source_val 2
 #define mmpll3_mm_source_val 3
 #define gpll0_mm_source_val 5
+#define edppll_270_mm_source_val 4
+#define edppll_350_mm_source_val 4
 
 struct clk_freq_tbl rcg_dummy_freq = F_END;
 
@@ -486,6 +488,273 @@
 	},
 };
 
+/* Display clocks */
+static struct clk_freq_tbl ftbl_mdss_esc0_1_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mdss_esc1_1_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mmss_axi_clk[] = {
+	F_MM(19200000,     cxo,     1,   0,   0),
+	F_MM(100000000,  gpll0,     6,   0,   0),
+	F_END
+};
+
+static struct clk_freq_tbl ftbl_mdp_clk[] = {
+	F_MM( 75000000,  gpll0,   8,   0,   0),
+	F_MM( 240000000,  gpll0,   2.5,   0,   0),
+	F_END
+};
+
+static struct rcg_clk dsi_esc0_clk_src = {
+	.cmd_reg  = (uint32_t *) DSI_ESC0_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) DSI_ESC0_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_esc0_1_clk,
+
+	.c        = {
+		.dbg_name = "dsi_esc0_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct rcg_clk dsi_esc1_clk_src = {
+	.cmd_reg  = (uint32_t *) DSI_ESC1_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) DSI_ESC1_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_esc1_1_clk,
+
+	.c        = {
+		.dbg_name = "dsi_esc1_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_vsync_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct rcg_clk vsync_clk_src = {
+	.cmd_reg  = (uint32_t *) VSYNC_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) VSYNC_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_vsync_clk,
+
+	.c        = {
+		.dbg_name = "vsync_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct rcg_clk mdp_axi_clk_src = {
+	.cmd_reg  = (uint32_t *) MDP_AXI_CMD_RCGR,
+	.cfg_reg  = (uint32_t *) MDP_AXI_CFG_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mmss_axi_clk,
+
+	.c        = {
+		.dbg_name = "mdp_axi_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_esc0_clk = {
+	.cbcr_reg    = (uint32_t *) DSI_ESC0_CBCR,
+	.parent      = &dsi_esc0_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_esc0_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_esc1_clk = {
+	.cbcr_reg    = (uint32_t *) DSI_ESC1_CBCR,
+	.parent      = &dsi_esc1_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_esc1_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mmss_mmssnoc_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MMSS_MMSSNOC_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mmss_mmssnoc_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mmss_s0_axi_clk = {
+	.cbcr_reg    = (uint32_t *) MMSS_S0_AXI_CBCR,
+	.parent      = &mdp_axi_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mmss_s0_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdp_ahb_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_AHB_CBCR,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdp_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk mdss_mdp_clk_src = {
+	.cmd_reg      = (uint32_t *) MDP_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) MDP_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_mdp_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c            = {
+		.dbg_name = "mdss_mdp_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_mdp_clk = {
+	.cbcr_reg    = (uint32_t *) MDP_CBCR,
+	.parent      = &mdss_mdp_clk_src.c,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdss_mdp_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_mdp_lut_clk = {
+	.cbcr_reg    = MDP_LUT_CBCR,
+	.parent      = &mdss_mdp_clk_src.c,
+	.has_sibling = 1,
+
+	.c           = {
+		.dbg_name = "mdss_mdp_lut_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_vsync_clk = {
+	.cbcr_reg    = MDSS_VSYNC_CBCR,
+	.parent      = &vsync_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_vsync_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
+	F_MM(19200000,    cxo,   1,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edpaux_clk_src = {
+	.cmd_reg  = (uint32_t *) EDPAUX_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_edpaux_clk,
+
+	.c        = {
+		.dbg_name = "edpaux_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk mdss_edpaux_clk = {
+	.cbcr_reg    = MDSS_EDPAUX_CBCR,
+	.parent      = &edpaux_clk_src.c,
+	.has_sibling = 0,
+
+	.c           = {
+		.dbg_name = "mdss_edpaux_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
+	F_MDSS(162000000, edppll_270,   2,   0,   0),
+	F_MDSS(270000000, edppll_270,  11,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edplink_clk_src = {
+	.cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_edplink_clk,
+	.current_freq = &rcg_dummy_freq,
+	.c = {
+		.dbg_name = "edplink_clk_src",
+		.ops = &clk_ops_rcg,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
+	F_MDSS(138500000, edppll_350,   2,   0,   0),
+	F_MDSS(350000000, edppll_350,  11,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edppixel_clk_src = {
+	.cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl = ftbl_mdss_edppixel_clk,
+	.current_freq = &rcg_dummy_freq,
+	.c = {
+		.dbg_name = "edppixel_clk_src",
+		.ops = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk mdss_edplink_clk = {
+	.cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
+	.has_sibling = 0,
+	.parent = &edplink_clk_src.c,
+	.c = {
+		.dbg_name = "mdss_edplink_clk",
+		.ops = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_edppixel_clk = {
+	.cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
+	.has_sibling = 0,
+	.parent = &edppixel_clk_src.c,
+	.c = {
+		.dbg_name = "mdss_edppixel_clk",
+		.ops = &clk_ops_branch,
+	},
+};
 
 /* Clock lookup table */
 static struct clk_lookup msm_8994_clocks[] =
@@ -510,6 +779,22 @@
 	CLK_LOOKUP("usb30_phy_reset",     gcc_usb30_phy_reset.c),
 
 	CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk",     gcc_usb_phy_cfg_ahb2phy_clk.c),
+
+	/* mdss clocks */
+	CLK_LOOKUP("mdp_ahb_clk",          mdp_ahb_clk.c),
+	CLK_LOOKUP("mdss_esc0_clk",        mdss_esc0_clk.c),
+	CLK_LOOKUP("mdss_esc1_clk",        mdss_esc1_clk.c),
+	CLK_LOOKUP("mdss_axi_clk",         mdss_axi_clk.c),
+	CLK_LOOKUP("mmss_mmssnoc_axi_clk", mmss_mmssnoc_axi_clk.c),
+	CLK_LOOKUP("mmss_s0_axi_clk",      mmss_s0_axi_clk.c),
+	CLK_LOOKUP("mdss_vsync_clk",       mdss_vsync_clk.c),
+	CLK_LOOKUP("mdss_mdp_clk_src",     mdss_mdp_clk_src.c),
+	CLK_LOOKUP("mdss_mdp_clk",         mdss_mdp_clk.c),
+	CLK_LOOKUP("mdss_mdp_lut_clk",     mdss_mdp_lut_clk.c),
+
+	CLK_LOOKUP("edp_pixel_clk",        mdss_edppixel_clk.c),
+	CLK_LOOKUP("edp_link_clk",         mdss_edplink_clk.c),
+	CLK_LOOKUP("edp_aux_clk",          mdss_edpaux_clk.c),
 };
 
 void platform_clock_init(void)