diff --git a/arch/arm/asm.S b/arch/arm/asm.S
index 1b0ea1e..97ebc73 100644
--- a/arch/arm/asm.S
+++ b/arch/arm/asm.S
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2008 Travis Geiselbrecht
  *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining
  * a copy of this software and associated documentation files
  * (the "Software"), to deal in the Software without restriction,
@@ -49,8 +51,7 @@
 
 	/* clear any exlusive locks that the old thread holds */
 #if ARM_ISA_ARMV7
-	/* can clear it directly */
-	.word	0xf57ff01f // clrex
+	clrex
 #elif ARM_ISA_ARMV6
 	/* have to do a fake strex to clear it */
 	ldr		r0, =strex_spot
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index e67dc65..4f66c00 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -125,7 +125,7 @@
 	mov		r7, r0						// save flags
 
 	mrs		r12, cpsr					// save the old interrupt state
-	.word	0xf10c01c0	/* cpsid iaf */	// interrupts disabled
+	cpsid iaf							// interrupts disabled
 
 .Ldcache_disable:
 	tst		r7, #DCACHE
@@ -145,22 +145,11 @@
 	// NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
 	bl		flush_invalidate_cache_v7
 
-	b		.Ldcache_disable_L2
-
 .Ldcache_already_disabled:
 	// make sure all of the caches are invalidated
 	// NOTE: trashes a bunch of registers, can't be spilling stuff to the stack
 	bl		invalidate_cache_v7
 
-.Ldcache_disable_L2:
-
-#if ARM_WITH_L2
-	// disable the L2, if present
-	mrc     p15, 0, r0, c1, c0, 1		// aux cr1
-	bic		r0, #(1<<1)
-	mcr		p15, 0, r0, c1, c0, 1		// disable L2 dcache
-#endif
-
 .Licache_disable:
 	tst		r7, #ICACHE
 	beq		.Ldone_disable
@@ -227,7 +216,7 @@
 	msr		cpsr, r12
 	ldmfd	sp!, {r4-r11, pc}
 
-// flush & invalidate cache routine, trashes r0-r6, r9-r11
+// flush & invalidate cache routine
 flush_invalidate_cache_v7:
 	DMB
 	/* from ARMv7 manual, B2-17 */
@@ -243,24 +232,24 @@
 	CMP 	R1, #2 
 	BLT 	.Lskip 						// no cache or only instruction cache at this level 
 	MCR 	p15, 2, R10, c0, c0, 0 		// write the Cache Size selection register 
-	.word	0xf57ff06f	// ISB 			// ISB to sync the change to the CacheSizeID reg 
+	ISB									// ISB to sync the change to the CacheSizeID reg
 	MRC 	p15, 1, R1, c0, c0, 0 		// reads current Cache Size ID register 
 	AND 	R2, R1, #0x7 				// extract the line length field 
 	ADD 	R2, R2, #4 					// add 4 for the line length offset (log2 16 bytes) 
 	LDR 	R4, =0x3FF 
 	ANDS 	R4, R4, R1, LSR #3 			// R4 is the max number on the way size (right aligned) 
-	CLZ 	R5, R4 						// R5 is the bit position of the way size increment 
-	LDR 	R6, =0x00007FFF 
-	ANDS 	R6, R6, R1, LSR #13 		// R6 is the max number of the index size (right aligned) 
+	CLZ 	R5, R4 						// R5 is the bit position of the way size increment
+	MOV		R9, R4						// R9 working copy of max way size (right aligned)
 .Loop2:
-	MOV 	R9, R4 						// R9 working copy of the max way size (right aligned) 
+	LDR 	R7, =0x00007FFF
+	ANDS 	R7, R7, R1, LSR #13 		// R7 is the max number of the index size (right aligned)
 .Loop3:
 	ORR 	R11, R10, R9, LSL R5 		// factor in the way number and cache number into R11 
-	ORR 	R11, R11, R6, LSL R2 		// factor in the index number 
-	MCR 	p15, 0, R11, c7, c14, 2 	// clean & invalidate by set/way 
-	SUBS 	R9, R9, #1 					// decrement the way number 
+	ORR 	R11, R11, R7, LSL R2 		// factor in the index number
+	MCR 	p15, 0, R11, c7, c10, 2 	// clean & invalidate by set/way
+	SUBS 	R7, R7, #1 					// decrement the index
 	BGE 	.Loop3 
-	SUBS 	R6, R6, #1 					// decrement the index 
+	SUBS 	R9, R9, #1 					// decrement the index
 	BGE 	.Loop2 
 .Lskip:
  	ADD 	R10, R10, #2 					// increment the cache number 
@@ -271,11 +260,11 @@
 	mov		r10, #0
 	mcr		p15, 2, r10, c0, c0, 0		// select cache level 0
 	dsb
-	.word	0xf57ff06f	// isb
+	ISB
 
 	bx		lr
 
-// invalidate cache routine, trashes r0-r6, r9-r11
+// invalidate cache routine
 invalidate_cache_v7:
 	/* from ARMv7 manual, B2-17 */
 	MRC 	p15, 1, R0, c0, c0, 1 		// Read CLIDR 
@@ -290,24 +279,24 @@
 	CMP 	R1, #2 
 	BLT 	.Lskip_invalidate 			// no cache or only instruction cache at this level 
 	MCR 	p15, 2, R10, c0, c0, 0 		// write the Cache Size selection register 
-	.word	0xf57ff06f	// ISB 			// ISB to sync the change to the CacheSizeID reg 
+	ISB 								// ISB to sync the change to the CacheSizeID reg
 	MRC 	p15, 1, R1, c0, c0, 0 		// reads current Cache Size ID register 
 	AND 	R2, R1, #0x7 				// extract the line length field 
 	ADD 	R2, R2, #4 					// add 4 for the line length offset (log2 16 bytes) 
 	LDR 	R4, =0x3FF 
 	ANDS 	R4, R4, R1, LSR #3 			// R4 is the max number on the way size (right aligned) 
 	CLZ 	R5, R4 						// R5 is the bit position of the way size increment 
-	LDR 	R6, =0x00007FFF 
-	ANDS 	R6, R6, R1, LSR #13 		// R6 is the max number of the index size (right aligned) 
+	MOV		R9, R4						//R9 working copy of the max way size (right aligned)
 .Loop2_invalidate:
-	MOV 	R9, R4 						// R9 working copy of the max way size (right aligned) 
+	LDR 	R7, =0x00007FFF
+	ANDS 	R7, R7, R1, LSR #13 		// R7 is the max number of the index size (right aligned)
 .Loop3_invalidate:
 	ORR 	R11, R10, R9, LSL R5 		// factor in the way number and cache number into R11 
-	ORR 	R11, R11, R6, LSL R2 		// factor in the index number 
+	ORR 	R11, R11, R7, LSL R2 		// factor in the index number
 	MCR 	p15, 0, R11, c7, c6, 2 		// invalidate by set/way 
-	SUBS 	R9, R9, #1 					// decrement the way number 
+	SUBS 	R7, R7, #1 					// decrement the way number
 	BGE 	.Loop3_invalidate 
-	SUBS 	R6, R6, #1 					// decrement the index 
+	SUBS 	R9, R9, #1 					// decrement the index
 	BGE 	.Loop2_invalidate 
 .Lskip_invalidate:
  	ADD 	R10, R10, #2 				// increment the cache number 
@@ -318,7 +307,7 @@
 	mov		r10, #0
 	mcr		p15, 2, r10, c0, c0, 0		// select cache level 0
 	dsb
-	.word	0xf57ff06f	// isb
+	ISB
 
 	bx		lr
 
diff --git a/arch/arm/include/arch/defines.h b/arch/arm/include/arch/defines.h
index 55eba02..6f0985a 100644
--- a/arch/arm/include/arch/defines.h
+++ b/arch/arm/include/arch/defines.h
@@ -45,9 +45,11 @@
 #if ARM_ISA_ARMV7
 #define dsb() __asm__ volatile ("dsb" : : : "memory");
 #define dmb() __asm__ volatile ("dmb" : : : "memory");
+#define isb() __asm__ volatile ("isb" : : : "memory");
 #elif ARM_ISA_ARMV6
 #define dsb() __asm__ volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0): "memory");
 #define dmb() __asm__ volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0): "memory");
+#define isb() __asm__ volatile ("mcr p15, 0, %0, c7, c5,  4" : : "r" (0): "memory");
 #endif
 
 #define GET_CAHE_LINE_START_ADDR(addr) ROUNDDOWN(addr, CACHE_LINE)
diff --git a/arch/arm/ops.S b/arch/arm/ops.S
index 6b9d966..6daea96 100644
--- a/arch/arm/ops.S
+++ b/arch/arm/ops.S
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2008 Travis Geiselbrecht
  *
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
  * Permission is hereby granted, free of charge, to any person obtaining
  * a copy of this software and associated documentation files
  * (the "Software"), to deal in the Software without restriction,
@@ -188,9 +190,7 @@
 /* void arch_idle(); */
 FUNCTION(arch_idle)
 #if ARM_CPU_CORTEX_A8
-	.word 0xe320f003 /* wfi */
-#elif PLATFORM_MSM7K
-	/* TODO: safely handle wfi */
+	wfi
 #elif ARM_CPU_ARM1136 || ARM_CPU_ARM926
 	mov	r0, #0
 	mcr	p15, 0, r0, c7, c0, #4