arch: arm: Fix armv7 init code
Fix armv7 init code to add isb macro instead of isb function.
Fix L2 cache invalidate code as per arm manual section B2-17.
Use SCTLR (System Control Register) to enable & disable caches
instead of ACTLR (Auxiliary control Register). Replace hand
coded assembly with armv7 ISA.
Change-Id: I740757a2a812d0f70a4c170af4065b4ff14e88e3
diff --git a/arch/arm/asm.S b/arch/arm/asm.S
index 1b0ea1e..97ebc73 100644
--- a/arch/arm/asm.S
+++ b/arch/arm/asm.S
@@ -1,6 +1,8 @@
/*
* Copyright (c) 2008 Travis Geiselbrecht
*
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
@@ -49,8 +51,7 @@
/* clear any exlusive locks that the old thread holds */
#if ARM_ISA_ARMV7
- /* can clear it directly */
- .word 0xf57ff01f // clrex
+ clrex
#elif ARM_ISA_ARMV6
/* have to do a fake strex to clear it */
ldr r0, =strex_spot