msm_shared: Add support for uart_dm in BLSP block.
Change-Id: I79ae7a3a0cf40597e4badb84e011d1be560da242
diff --git a/platform/msm_shared/include/uart_dm.h b/platform/msm_shared/include/uart_dm.h
index 484e7b5..f7746de 100644
--- a/platform/msm_shared/include/uart_dm.h
+++ b/platform/msm_shared/include/uart_dm.h
@@ -73,13 +73,25 @@
#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
/* UART Clock Selection Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0xA0)
+#else
#define MSM_BOOT_UART_DM_CSR(base) ((base) + 0x08)
+#endif
/* UART DM TX FIFO Registers - 4 */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_TF(base, x) ((base + 0x100+(4*(x)))
+#else
#define MSM_BOOT_UART_DM_TF(base, x) ((base) + 0x70+(4*(x)))
+#endif
/* UART Command Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_CR(base) ((base) + 0xA8)
+#else
#define MSM_BOOT_UART_DM_CR(base) ((base) + 0x10)
+#endif
#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
@@ -88,8 +100,8 @@
/* UART Channel Command */
#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
-#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | \
- MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
+#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x)\
+ | MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
@@ -121,7 +133,12 @@
#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
/* UART Interrupt Mask Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0xB0)
+#else
#define MSM_BOOT_UART_DM_IMR(base) ((base) + 0x14)
+#endif
+
#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
@@ -165,7 +182,11 @@
#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
/* Register to enable IRDA function */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0xB8)
+#else
#define MSM_BOOT_UART_DM_IRDA(base) ((base) + 0x38)
+#endif
/* UART Data Mover Enable Register */
#define MSM_BOOT_UART_DM_DMEN(base) ((base) + 0x3C)
@@ -177,7 +198,11 @@
#define MSM_BOOT_UART_DM_BADR(base) ((base) + 0x44)
/* UART Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x0A4)
+#else
#define MSM_BOOT_UART_DM_SR(base) ((base) + 0x008)
+#endif
#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
@@ -189,16 +214,32 @@
#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
/* UART Receive FIFO Registers - 4 in numbers */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x140 + (4*(x)))
+#else
#define MSM_BOOT_UART_DM_RF(base, x) ((base) + 0x70 + (4*(x)))
+#endif
/* UART Masked Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0xAC)
+#else
#define MSM_BOOT_UART_DM_MISR(base) ((base) + 0x10)
+#endif
/* UART Interrupt Status Register */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0xB4)
+#else
#define MSM_BOOT_UART_DM_ISR(base) ((base) + 0x14)
+#endif
/* Number of characters received since the end of last RX transfer */
+#if PERIPH_BLK_BLSP
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0xBC)
+#else
#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base) ((base) + 0x38)
+#endif
/* UART TX FIFO Status Register */
#define MSM_BOOT_UART_DM_TXFS(base) ((base) + 0x4C)