platform: msm8974: Clock support for hs400
Add support for gpll4, sdc_ff & sdc_sleep clocks.
Also update sdc1 frquency table to run sdc1 core clock
at 400 MHZ
CRs-Fixed: 501718
Change-Id: I7c08a4f65c7850f23c0184342875a4bf035e6d5e
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index 7812d44..8b113c1 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -223,10 +223,19 @@
config.bus_width = DATA_BUS_WIDTH_8BIT;
};
- config.max_clk_rate = MMC_CLK_200MHZ;
-
/* Trying Slot 1*/
config.slot = 1;
+ /*
+ * For 8974 AC & 8x62 platforms the software clock
+ * plan recommends to use the following frequencies:
+ * 200 MHz --> 192 MHZ
+ * 400 MHZ --> 384 MHZ
+ * only for emmc slot
+ */
+ if (platform_is_8974ac() || platform_is_8x62())
+ config.max_clk_rate = MMC_CLK_192MHZ;
+ else
+ config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
@@ -234,6 +243,7 @@
if (!(dev = mmc_init(&config))) {
/* Trying Slot 2 next */
config.slot = 2;
+ config.max_clk_rate = MMC_CLK_200MHZ;
config.sdhc_base = mmc_sdhci_base[config.slot - 1];
config.pwrctl_base = mmc_sdc_base[config.slot - 1];
config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];