| commit | c1002b0c0ddf6ee9218d41027d07a8782fad8a83 | [log] [tgz] |
|---|---|---|
| author | Siddhartha Agrawal <agrawals@codeaurora.org> | Thu May 02 16:03:59 2013 -0700 |
| committer | Siddhartha Agrawal <agrawals@codeaurora.org> | Tue May 07 16:25:25 2013 -0700 |
| tree | 0d9f58dce08f0c54c5c358668e07e0c34ebfe456 | |
| parent | 4f311a8f73787b2687b76149398dd37d5d265548 [diff] |
msm_shared: mipi: Add correct post dividers for DSI PLL DSI pixel clock was not setup correctly causing clk_set_rate to fail on kernel bootup. Change-Id: I5edff1df934755877ede67d4af09e8a173f3ca8c