tree 47d28657e19f29b87e631bad1458737f75968f16
parent 9c68f9de633fcf844e81dabbadf316ae1cbe92b3
author Channagoud Kadabi <ckadabi@codeaurora.org> 1442357170 -0700
committer Channagoud Kadabi <ckadabi@codeaurora.org> 1442357775 -0700

arch: arm: Flush the cache after mmu tables are updated

Update the TTBCR bits with cache aatributes of mmu page tables memory.
MMU page table updates would not take affect if the page table mapping
and TTBCR bits for TTBR0 have different cache attributes. Make sure to
flush the page table memory after its updated and align the page table
address to cacheline

Change-Id: I864f7b97ec068d62203080c2bda2011b764d259c