commit c648e71d340916d0a85643767c31092aa3b3308c
author Shashank Mittal <mittals@codeaurora.org> Wed Oct 06 18:37:42 2010 -0700
committer Shashank Mittal <mittals@codeaurora.org> Fri Oct 08 17:48:03 2010 -0700
tree bc30708f92cc8e8e4465f036c7401429f1fd6d7d
parent 4ebc11c0a2446a774bfc2f90b8a9c0e808bd09ad

[msm8x60]: Fix LCDC display for new PXO plan.

    - Add support for new PXO frequency plan.
    - Update splash image
    - Disable mdp after loading HLOS into the ram.

Change-Id: I35072af621bae881a623def67b4f02dab9102bf4

platform/msm8x60/include/platform/clock.h

diff --git a/platform/msm8x60/include/platform/clock.h b/platform/msm8x60/include/platform/clock.h
old mode 100755
new mode 100644
index 7763f18..fc6ff46
--- a/platform/msm8x60/include/platform/clock.h
+++ b/platform/msm8x60/include/platform/clock.h
@@ -79,6 +79,13 @@
 #define PIXEL_MD_VAL            0x00A9FDA6
 #define PIXEL_CC_VAL            0x00000080
 
+#define MSM_CLK_CTL_BASE        0x00900000
+#define BB_PLL8_L_VAL_REG       (MSM_CLK_CTL_BASE + 0x3144)
+#define BB_PLL8_M_VAL_REG       (MSM_CLK_CTL_BASE + 0x3148)
+#define BB_PLL8_MODE_REG        (MSM_CLK_CTL_BASE + 0x3140)
+#define BB_PLL8_N_VAL_REG       (MSM_CLK_CTL_BASE + 0x314C)
+
+
 enum clk_sources {
     PLL_0 = 0,
     PLL_1,