diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index d732a4e..1e9dacd 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -33,7 +33,6 @@
 #include <app.h>
 #include <debug.h>
 #include <arch/arm.h>
-#include <dev/udc.h>
 #include <string.h>
 #include <stdlib.h>
 #include <kernel/thread.h>
@@ -124,14 +123,6 @@
 
 static device_info device = {DEVICE_MAGIC, 0, 0};
 
-static struct udc_device surf_udc_device = {
-	.vendor_id	= 0x18d1,
-	.product_id	= 0xD00D,
-	.version_id	= 0x0100,
-	.manufacturer	= "Google",
-	.product	= "Android",
-};
-
 struct atag_ptbl_entry
 {
 	char name[16];
@@ -696,7 +687,7 @@
 		device.is_unlocked,
 		device.is_tampered);
 
-	if(target_use_signed_kernel() && (!device.is_unlocked) && (!device.is_tampered))
+	if(target_use_signed_kernel() && (!device.is_unlocked))
 	{
 		offset = 0;
 
@@ -706,7 +697,7 @@
 		dt_actual = ROUND_TO_PAGE(hdr->dt_size, page_mask);
 		imagesize_actual = (page_size + kernel_actual + ramdisk_actual + dt_actual);
 
-		if (check_aboot_addr_range_overlap(hdr->tags_addr, hdr->dt_size))
+		if (check_aboot_addr_range_overlap(hdr->tags_addr, dt_actual))
 		{
 			dprintf(CRITICAL, "Device tree addresses overlap with aboot addresses.\n");
 			return -1;
@@ -719,6 +710,12 @@
 		dprintf(INFO, "Loading boot image (%d): start\n", imagesize_actual);
 		bs_set_timestamp(BS_KERNEL_LOAD_START);
 
+		if (check_aboot_addr_range_overlap(image_addr, imagesize_actual))
+		{
+			dprintf(CRITICAL, "Boot image buffer address overlaps with aboot addresses.\n");
+			return -1;
+		}
+
 		/* Read image without signature */
 		if (mmc_read(ptn + offset, (void *)image_addr, imagesize_actual))
 		{
@@ -730,6 +727,13 @@
 		bs_set_timestamp(BS_KERNEL_LOAD_DONE);
 
 		offset = imagesize_actual;
+
+		if (check_aboot_addr_range_overlap(image_addr + offset, page_size))
+		{
+			dprintf(CRITICAL, "Signature read buffer address overlaps with aboot addresses.\n");
+			return -1;
+		}
+
 		/* Read signature */
 		if(mmc_read(ptn + offset, (void *)(image_addr + offset), page_size))
 		{
@@ -776,7 +780,8 @@
 			 */
 			void *dtb;
 			dtb = dev_tree_appended((void*) hdr->kernel_addr,
-						(void *)hdr->tags_addr, hdr->kernel_size);
+						hdr->kernel_size,
+						(void *)hdr->tags_addr);
 			if (!dtb) {
 				dprintf(CRITICAL, "ERROR: Appended Device Tree Blob not found\n");
 				return -1;
@@ -867,7 +872,8 @@
 			 */
 			void *dtb;
 			dtb = dev_tree_appended((void*) hdr->kernel_addr,
-						(void *)hdr->tags_addr, hdr->kernel_size);
+						kernel_actual,
+						(void *)hdr->tags_addr);
 			if (!dtb) {
 				dprintf(CRITICAL, "ERROR: Appended Device Tree Blob not found\n");
 				return -1;
@@ -984,7 +990,7 @@
 #endif
 
 	/* Authenticate Kernel */
-	if(target_use_signed_kernel() && (!device.is_unlocked) && (!device.is_tampered))
+	if(target_use_signed_kernel() && (!device.is_unlocked))
 	{
 		image_addr = (unsigned char *)target_get_scratch_address();
 		offset = 0;
@@ -1432,7 +1438,8 @@
 	 */
 	if (!dtb_copied) {
 		void *dtb;
-		dtb = dev_tree_appended((void *)hdr->kernel_addr, (void *)hdr->tags_addr, hdr->kernel_size);
+		dtb = dev_tree_appended((void *)hdr->kernel_addr, hdr->kernel_size,
+					(void *)hdr->tags_addr);
 		if (!dtb) {
 			fastboot_fail("dtb not found");
 			return;
@@ -1940,11 +1947,50 @@
 	}
 }
 
+/* register commands and variables for fastboot */
+void aboot_fastboot_register_commands(void)
+{
+	if (target_is_emmc_boot())
+	{
+		fastboot_register("flash:", cmd_flash_mmc);
+		fastboot_register("erase:", cmd_erase_mmc);
+	}
+	else
+	{
+		fastboot_register("flash:", cmd_flash);
+		fastboot_register("erase:", cmd_erase);
+	}
+
+	fastboot_register("boot",              cmd_boot);
+	fastboot_register("continue",          cmd_continue);
+	fastboot_register("reboot",            cmd_reboot);
+	fastboot_register("reboot-bootloader", cmd_reboot_bootloader);
+	fastboot_register("oem unlock",        cmd_oem_unlock);
+	fastboot_register("oem device-info",   cmd_oem_devinfo);
+	fastboot_register("preflash",          cmd_preflash);
+
+	/* publish variables and their values */
+	fastboot_publish("product",  TARGET(BOARD));
+	fastboot_publish("kernel",   "lk");
+	fastboot_publish("serialno", sn_buf);
+
+	/*
+	 * partition info is supported only for emmc partitions
+	 * Calling this for NAND prints some error messages which
+	 * is harmless but misleading. Avoid calling this for NAND
+	 * devices.
+	 */
+	if (target_is_emmc_boot())
+		publish_getvar_partition_info(part_info, ARRAY_SIZE(part_info));
+
+	/* Max download size supported */
+	snprintf(max_download_size, MAX_RSP_SIZE, "\t0x%x", target_get_max_flash_size());
+	fastboot_publish("max-download-size", (const char *) max_download_size);
+}
+
 void aboot_init(const struct app_descriptor *app)
 {
 	unsigned reboot_mode = 0;
-	unsigned usb_init = 0;
-	unsigned sz = 0;
 	bool boot_into_fastboot = false;
 
 	/* Setup page size information for nand/emmc reads */
@@ -1969,7 +2015,6 @@
 
 	target_serialno((unsigned char *) sn_buf);
 	dprintf(SPEW,"serial number: %s\n",sn_buf);
-	surf_udc_device.serialno = sn_buf;
 
 	/* Check if we should do something other than booting up */
 	if (keys_get_state(KEY_VOLUMEUP) && keys_get_state(KEY_VOLUMEDOWN))
@@ -2039,49 +2084,16 @@
 			"to fastboot mode.\n");
 	}
 
-	sz = target_get_max_flash_size();
+	/* We are here means regular boot did not happen. Start fastboot. */
 
-	target_fastboot_init();
+	/* register aboot specific fastboot commands */
+	aboot_fastboot_register_commands();
 
-	if(!usb_init)
-		udc_init(&surf_udc_device);
-
-	fastboot_register("boot", cmd_boot);
-
-	if (target_is_emmc_boot())
-	{
-		fastboot_register("flash:", cmd_flash_mmc);
-		fastboot_register("erase:", cmd_erase_mmc);
-	}
-	else
-	{
-		fastboot_register("flash:", cmd_flash);
-		fastboot_register("erase:", cmd_erase);
-	}
-
-	fastboot_register("continue", cmd_continue);
-	fastboot_register("reboot", cmd_reboot);
-	fastboot_register("reboot-bootloader", cmd_reboot_bootloader);
-	fastboot_register("oem unlock", cmd_oem_unlock);
-	fastboot_register("oem device-info", cmd_oem_devinfo);
-	fastboot_register("preflash", cmd_preflash);
-	fastboot_publish("product", TARGET(BOARD));
-	fastboot_publish("kernel", "lk");
-	fastboot_publish("serialno", sn_buf);
-	/*
-	 * fastboot publish is supported only for emmc partitions
-	 * Calling this for NAND prints some error messages which
-	 * is harmless but misleading. Avoid calling this for NAND
-	 * devices.
-	 */
-	if (target_is_emmc_boot())
-		publish_getvar_partition_info(part_info, ARRAY_SIZE(part_info));
-	/* Max download size supported */
-	snprintf(max_download_size, MAX_RSP_SIZE, "\t0x%x", sz);
-	fastboot_publish("max-download-size", (const char *) max_download_size);
+	/* dump partition table for debug info */
 	partition_dump();
-	fastboot_init(target_get_scratch_address(), sz);
-	udc_start();
+
+	/* initialize and start fastboot */
+	fastboot_init(target_get_scratch_address(), target_get_max_flash_size());
 }
 
 uint32_t get_page_size()
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index 262a08e..66d0437 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -32,6 +32,7 @@
 #include <string.h>
 #include <stdlib.h>
 #include <platform.h>
+#include <target.h>
 #include <kernel/thread.h>
 #include <kernel/event.h>
 #include <dev/udc.h>
@@ -40,6 +41,26 @@
 #define MAX_USBFS_BULK_SIZE (32 * 1024)
 
 void boot_linux(void *bootimg, unsigned sz);
+static void fastboot_notify(struct udc_gadget *gadget, unsigned event);
+static struct udc_endpoint *fastboot_endpoints[2];
+
+static struct udc_device surf_udc_device = {
+	.vendor_id    = 0x18d1,
+	.product_id   = 0xD00D,
+	.version_id   = 0x0100,
+	.manufacturer = "Google",
+	.product      = "Android",
+};
+
+static struct udc_gadget fastboot_gadget = {
+	.notify        = fastboot_notify,
+	.ifc_class     = 0xff,
+	.ifc_subclass  = 0x42,
+	.ifc_protocol  = 0x03,
+	.ifc_endpoints = 2,
+	.ifc_string    = "fastboot",
+	.ept           = fastboot_endpoints,
+};
 
 /* todo: give lk strtoul and nuke this */
 static unsigned hex2unsigned(const char *x)
@@ -81,7 +102,7 @@
 	const char *name;
 	const char *value;
 };
-	
+
 static struct fastboot_cmd *cmdlist;
 
 void fastboot_register(const char *prefix,
@@ -305,6 +326,14 @@
 	}
 again:
 	while (fastboot_state != STATE_ERROR) {
+
+		/* Read buffer must be cleared first. If buffer is not cleared,
+		 * the original data in buf trailing the received command is
+		 * interpreted as part of the command.
+		 */
+		memset(buffer, 0, MAX_RSP_SIZE);
+		arch_clean_invalidate_cache_range((addr_t) buffer, MAX_RSP_SIZE);
+
 		r = usb_read(buffer, MAX_RSP_SIZE);
 		if (r < 0) break;
 		buffer[r] = 0;
@@ -322,7 +351,7 @@
 		}
 
 		fastboot_fail("unknown command");
-			
+
 	}
 	fastboot_state = STATE_OFFLINE;
 	dprintf(INFO,"fastboot: oops!\n");
@@ -345,26 +374,26 @@
 	}
 }
 
-static struct udc_endpoint *fastboot_endpoints[2];
-
-static struct udc_gadget fastboot_gadget = {
-	.notify		= fastboot_notify,
-	.ifc_class	= 0xff,
-	.ifc_subclass	= 0x42,
-	.ifc_protocol	= 0x03,
-	.ifc_endpoints	= 2,
-	.ifc_string	= "fastboot",
-	.ept		= fastboot_endpoints,
-};
-
 int fastboot_init(void *base, unsigned size)
 {
+	char sn_buf[13];
 	thread_t *thr;
 	dprintf(INFO, "fastboot_init()\n");
 
 	download_base = base;
 	download_max = size;
 
+	/* target specific initialization before going into fastboot. */
+	target_fastboot_init();
+
+	/* setup serialno */
+	target_serialno((unsigned char *) sn_buf);
+	dprintf(SPEW,"serial number: %s\n",sn_buf);
+	surf_udc_device.serialno = sn_buf;
+
+	/* register udc device */
+	udc_init(&surf_udc_device);
+
 	event_init(&usb_online, 0, EVENT_FLAG_AUTOUNSIGNAL);
 	event_init(&txn_done, 0, EVENT_FLAG_AUTOUNSIGNAL);
 
@@ -382,6 +411,7 @@
 	if (!req)
 		goto fail_alloc_req;
 
+	/* register gadget */
 	if (udc_register_gadget(&fastboot_gadget))
 		goto fail_udc_register;
 
@@ -395,12 +425,15 @@
 		goto fail_alloc_in;
 	}
 	thread_resume(thr);
+
+	udc_start();
+
 	return 0;
 
 fail_udc_register:
 	udc_request_free(req);
 fail_alloc_req:
-	udc_endpoint_free(out);	
+	udc_endpoint_free(out);
 fail_alloc_out:
 	udc_endpoint_free(in);
 fail_alloc_in:
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
old mode 100755
new mode 100644
index 7f78122..da69f20
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -184,21 +184,14 @@
 	if (pinfo->mipi.dual_dsi)
 		panel_width = panel_width / 2;
 
-	switch (pinfo->mipi.num_of_lanes) {
-	case 1:
-		lane_enable = 0x1; /*1 lane only */
-		break;
-	case 2:
-		lane_enable = 0x3; /* 2 lanes only */
-		break;
-	case 3:
-		lane_enable = 0x7; /* 3 lanes only */
-		break;
-	case 4:
-	default:
-		lane_enable = 0xf; /* 4 lanes */
-		break;
-	}
+	if (pinfo->mipi.data_lane0)
+		lane_enable |= (1 << 0);
+	if (pinfo->mipi.data_lane1)
+		lane_enable |= (1 << 1);
+	if (pinfo->mipi.data_lane2)
+		lane_enable |= (1 << 2);
+	if (pinfo->mipi.data_lane3)
+		lane_enable |= (1 << 3);
 
 	ret = mdss_dsi_video_mode_config((panel_width + plcdc->xres_pad),
 			(pinfo->yres + plcdc->yres_pad),
@@ -245,11 +238,24 @@
 			struct lcdc_panel_info *plcdc)
 {
 	int ret = NO_ERROR;
+	uint8_t lane_en = 0;
+	uint8_t ystride = pinfo->bpp / 8;
+
+	if (pinfo->mipi.data_lane0)
+		lane_en |= (1 << 0);
+	if (pinfo->mipi.data_lane1)
+		lane_en |= (1 << 1);
+	if (pinfo->mipi.data_lane2)
+		lane_en |= (1 << 2);
+	if (pinfo->mipi.data_lane3)
+		lane_en |= (1 << 3);
 
 	ret = mdss_dsi_cmd_mode_config((pinfo->xres + plcdc->xres_pad),
 			(pinfo->yres + plcdc->yres_pad),
 			(pinfo->xres), (pinfo->yres),
-			pinfo->mipi.dst_format, pinfo->mipi.traffic_mode);
+			pinfo->mipi.dst_format,
+			ystride, lane_en,
+			pinfo->mipi.interleave_mode);
 
 	return ret;
 }
diff --git a/dev/panel/msm/edp_auo_1080p.c b/dev/panel/msm/edp_auo_1080p.c
new file mode 100644
index 0000000..42aa021
--- /dev/null
+++ b/dev/panel/msm/edp_auo_1080p.c
@@ -0,0 +1,87 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <edp.h>
+#include <msm_panel.h>
+
+static void edp_auo_1080p_init_edid_data(struct edp_edid *edid)
+{
+	edid->id_name[0] = 'A';
+	edid->id_name[0] = 'U';
+	edid->id_name[0] = 'O';
+	edid->id_name[0] = 0;
+	edid->id_product = 0x305D;
+	edid->version = 1;
+	edid->revision = 4;
+	edid->ext_block_cnt = 0;
+	edid->video_digital = 0x5;
+	edid->color_depth = 6;
+	edid->dpm = 0;
+	edid->color_format = 0;
+	edid->timing[0].pclk = 138500000;
+	edid->timing[0].h_addressable = 1920;
+	edid->timing[0].h_blank = 160;
+	edid->timing[0].v_addressable = 1080;
+	edid->timing[0].v_blank = 30;
+	edid->timing[0].h_fporch = 48;
+	edid->timing[0].h_sync_pulse = 32;
+	edid->timing[0].v_sync_pulse = 14;
+	edid->timing[0].v_fporch = 8;
+	edid->timing[0].width_mm =  256;
+	edid->timing[0].height_mm = 144;
+	edid->timing[0].h_border = 0;
+	edid->timing[0].v_border = 0;
+	edid->timing[0].interlaced = 0;
+	edid->timing[0].stereo = 0;
+	edid->timing[0].sync_type = 1;
+	edid->timing[0].sync_separate = 1;
+	edid->timing[0].vsync_pol = 0;
+	edid->timing[0].hsync_pol = 0;
+
+}
+
+static void edp_auo_1080p_init_dpcd_data(struct dpcd_cap *cap)
+{
+	cap->max_lane_count = 2;
+	cap->max_link_clk = 270;
+}
+
+void edp_auo_1080p_init(struct edp_panel_data *edp_panel)
+{
+	if (!edp_panel->panel_data) {
+		dprintf(CRITICAL, "%s(), panel_data is null", __func__);
+		return;
+	}
+
+	edp_auo_1080p_init_edid_data(&(edp_panel->edid));
+	edp_auo_1080p_init_dpcd_data(&(edp_panel->dpcd));
+	edp_edid2pinfo(edp_panel);
+
+	edp_panel->panel_data->panel_info.on = edp_on;
+	edp_panel->panel_data->panel_info.off = edp_off;
+}
diff --git a/dev/panel/msm/mipi_nt35590_cmd_720p.c b/dev/panel/msm/mipi_nt35590_cmd_720p.c
index 41c6220..6629aa6 100644
--- a/dev/panel/msm/mipi_nt35590_cmd_720p.c
+++ b/dev/panel/msm/mipi_nt35590_cmd_720p.c
@@ -2385,7 +2385,9 @@
 			(pinfo->xres),
 			(pinfo->yres),
 			pinfo->mipi.dst_format,
-			pinfo->mipi.traffic_mode);
+			pinfo->bpp / 8,
+			0xf,
+			pinfo->mipi.interleave_mode);
 
 	return ret;
 }
diff --git a/dev/panel/msm/mipi_truly_cmd_wvga.c b/dev/panel/msm/mipi_truly_cmd_wvga.c
new file mode 100644
index 0000000..b1f6c31
--- /dev/null
+++ b/dev/panel/msm/mipi_truly_cmd_wvga.c
@@ -0,0 +1,314 @@
+/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <stdint.h>
+#include <msm_panel.h>
+#include <mipi_dsi.h>
+#include <sys/types.h>
+#include <err.h>
+#include <reg.h>
+#include <debug.h>
+#include <target/display.h>
+#include <platform/iomap.h>
+
+#define WVGA_MIPI_FB_WIDTH            480
+#define WVGA_MIPI_FB_HEIGHT           800
+
+#define TRULY_PANEL_FRAME_RATE        60
+#define TRULY_PANEL_NUM_OF_LANES      2
+#define TRULY_PANEL_LANE_SWAP         0
+#define TRULY_PANEL_T_CLK_PRE         0x41b
+#define TRULY_PANEL_T_CLK_POST        0x0
+#define TRULY_PANEL_BPP               24
+#define TRULY_PANEL_CLK_RATE          499000000
+
+static char disp_on0[4] = {
+	0x01, 0x00, 0x05, 0x80
+};
+static char disp_on1[4] = {
+	0xB0, 0x04, 0x23, 0x80
+};
+static char disp_on2[8] = {
+	0x03, 0x00, 0x29, 0xC0,
+	0xB3, 0x02, 0x00, 0xFF
+};
+static char disp_on3[4] = {
+	0xBD, 0x00, 0x23, 0x80
+};
+static char disp_on4[8] = {
+	0x03, 0x00, 0x29, 0xC0,
+	0xC0, 0x18, 0x66, 0xFF
+};
+static char disp_on5[20] = {
+	0x10, 0x00, 0x29, 0xC0,
+	0xC1, 0x23, 0x31, 0x99,
+	0x21, 0x20, 0x00, 0x30,
+	0x28, 0x0C, 0x0C, 0x00,
+	0x00, 0x00, 0x21, 0x01
+};
+static char disp_on6[12] = {
+	0x07, 0x00, 0x29, 0xC0,
+	0xC2, 0x00, 0x06, 0x06,
+	0x01, 0x03, 0x00, 0xFF
+};
+static char disp_on7[32] = {
+	0x19, 0x00, 0x29, 0xC0,
+	0xC8, 0x04, 0x10, 0x18,
+	0x20, 0x2E, 0x46, 0x3C,
+	0x28, 0x1F, 0x18, 0x10,
+	0x04, 0x04, 0x10, 0x18,
+	0x20, 0x2E, 0x46, 0x3C,
+	0x28, 0x1F, 0x18, 0x10,
+	0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on8[32] = {
+	0x19, 0x00, 0x29, 0xC0,
+	0xC9, 0x04, 0x10, 0x18,
+	0x20, 0x2E, 0x46, 0x3C,
+	0x28, 0x1F, 0x18, 0x10,
+	0x04, 0x04, 0x10, 0x18,
+	0x20, 0x2E, 0x46, 0x3C,
+	0x28, 0x1F, 0x18, 0x10,
+	0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on9[32] = {
+	0x19, 0x00, 0x29, 0xC0,
+	0xCA, 0x04, 0x10, 0x18,
+	0x20, 0x2E, 0x46, 0x3C,
+	0x28, 0x1F, 0x18, 0x10,
+	0x04, 0x04, 0x10, 0x18,
+	0x20, 0x2E, 0x46, 0x3C,
+	0x28, 0x1F, 0x18, 0x10,
+	0x04, 0xFF, 0xFF, 0xFF
+};
+static char disp_on10[24] = {
+	0x11, 0x00, 0x29, 0xC0,
+	0xD0, 0x29, 0x03, 0xce,
+	0xa6, 0x00, 0x43, 0x20,
+	0x10, 0x01, 0x00, 0x01,
+	0x01, 0x00, 0x03, 0x01,
+	0x00, 0xFF, 0xFF, 0xFF
+};
+static char disp_on11[12] = {
+	0x08, 0x00, 0x29, 0xC0,
+	0xD1, 0x18, 0x0C, 0x23,
+	0x03, 0x75, 0x02, 0x50
+};
+static char disp_on12[4] = {
+	0xD3, 0x11, 0x23, 0x80
+};
+static char disp_on13[8] = {
+	0x03, 0x00, 0x29, 0xC0,
+	0xD5, 0x2A, 0x2A, 0xFF
+};
+static char disp_on14[8] = {
+	0x03, 0x00, 0x29, 0xC0,
+	0xDE, 0x01, 0x51, 0xFF
+};
+static char disp_on15[4] = {
+	0xE6, 0x51, 0x23, 0x80
+};
+static char disp_on16[4] = {
+	0xFA, 0x03, 0x23, 0x80
+};
+static char disp_on17[4] = {
+	0xD6, 0x28, 0x23, 0x80
+};
+static char disp_on18[4] = {
+	0x36, 0x41, 0x15, 0x80
+};
+static char disp_on19[12] = {
+	0x05, 0x00, 0x39, 0xC0,
+	0x2A, 0x00, 0x00, 0x01,
+	0xDF, 0xFF, 0xFF, 0xFF
+};
+static char disp_on20[12] = {
+	0x05, 0x00, 0x39, 0xC0,
+	0x2B, 0x00, 0x00, 0x03,
+	0x1F, 0xFF, 0xFF, 0xFF
+};
+static char disp_on21[4] = {
+	0x35, 0x00, 0x15, 0x80
+};
+static char disp_on22[8] = {
+	0x03, 0x00, 0x39, 0xc0,
+	0x44, 0x00, 0x50, 0xFF
+};
+static char disp_on23[4] = {
+	0x3A, 0x77, 0x15, 0x80
+};
+static char disp_on24[4] = {
+	0x11, 0x00, 0x05, 0x80
+};
+static char disp_on25[4] = {
+	0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd truly_wvga_panel_cmd_mode_cmds[] = {
+	{sizeof(disp_on0), (char *)disp_on0},
+	{sizeof(disp_on1), (char *)disp_on1},
+	{sizeof(disp_on2), (char *)disp_on2},
+	{sizeof(disp_on3), (char *)disp_on3},
+	{sizeof(disp_on4), (char *)disp_on4},
+	{sizeof(disp_on5), (char *)disp_on5},
+	{sizeof(disp_on6), (char *)disp_on6},
+	{sizeof(disp_on7), (char *)disp_on7},
+	{sizeof(disp_on8), (char *)disp_on8},
+	{sizeof(disp_on9), (char *)disp_on9},
+	{sizeof(disp_on10), (char *)disp_on10},
+	{sizeof(disp_on11), (char *)disp_on11},
+	{sizeof(disp_on12), (char *)disp_on12},
+	{sizeof(disp_on13), (char *)disp_on13},
+	{sizeof(disp_on14), (char *)disp_on14},
+	{sizeof(disp_on15), (char *)disp_on15},
+	{sizeof(disp_on16), (char *)disp_on16},
+	{sizeof(disp_on17), (char *)disp_on17},
+	{sizeof(disp_on18), (char *)disp_on18},
+	{sizeof(disp_on19), (char *)disp_on19},
+	{sizeof(disp_on20), (char *)disp_on20},
+	{sizeof(disp_on21), (char *)disp_on21},
+	{sizeof(disp_on22), (char *)disp_on22},
+	{sizeof(disp_on23), (char *)disp_on23},
+	{sizeof(disp_on24), (char *)disp_on24},
+	{sizeof(disp_on25), (char *)disp_on25},
+};
+
+int mipi_truly_cmd_wvga_config(void *pdata)
+{
+	int ret = NO_ERROR;
+	/* 2 Lanes -- Enables Data Lane0, 1 */
+	unsigned char lane_en = 0x3;
+	unsigned long low_pwr_stop_mode = 0;
+
+	/* Needed or else will have blank line at top of display */
+	unsigned char eof_bllp_pwr = 0x9;
+
+	unsigned char interleav = 0;
+	struct lcdc_panel_info *lcdc = NULL;
+	struct msm_panel_info *pinfo = (struct msm_panel_info *) pdata;
+
+	if (pinfo == NULL)
+		return ERR_INVALID_ARGS;
+
+	lcdc =  &(pinfo->lcdc);
+	if (lcdc == NULL)
+		return ERR_INVALID_ARGS;
+
+	ret = mdss_dsi_cmd_mode_config((pinfo->xres + lcdc->xres_pad),
+					(pinfo->yres + lcdc->yres_pad),
+					(pinfo->xres),
+					(pinfo->yres),
+					pinfo->mipi.dst_format,
+					pinfo->bpp / 8,
+					lane_en,
+					0);
+
+	return ret;
+}
+
+int mipi_truly_cmd_wvga_on()
+{
+	int ret = NO_ERROR;
+	return ret;
+}
+
+int mipi_truly_cmd_wvga_off()
+{
+	int ret = NO_ERROR;
+	return ret;
+}
+
+static struct mdss_dsi_phy_ctrl dsi_video_mode_phy_db = {
+	/* regulator */
+	{0x02, 0x08, 0x05, 0x00, 0x20, 0x03},
+	/* timing   */
+	{0x5d, 0x12, 0x0c, 0x00, 0x33, 0x38,
+		0x10, 0x16, 0x1e, 0x03, 0x04, 0x00},
+	/* phy ctrl */
+	{0x7f, 0x00, 0x00, 0x00},
+	/* strength */
+	{0xff, 0x06},
+	/* bist */
+	{0x03, 0x03, 0x00, 0x00, 0x0f, 0x00},
+	/* lane config */
+	{0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+		0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+		0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+		0x80, 0x45, 0x00, 0x00, 0x00, 0x01, 0x66, 0x00, 0x00,
+		0x40, 0x67, 0x00, 0x00, 0x00, 0x01, 0x88, 0x00, 0x00},
+};
+
+void mipi_truly_cmd_wvga_init(struct msm_panel_info *pinfo)
+{
+	if (!pinfo)
+		return;
+
+	pinfo->xres = WVGA_MIPI_FB_WIDTH;
+	pinfo->yres = WVGA_MIPI_FB_HEIGHT;
+	pinfo->lcdc.h_back_porch = MIPI_HSYNC_BACK_PORCH_DCLK;
+	pinfo->lcdc.h_front_porch = MIPI_HSYNC_FRONT_PORCH_DCLK;
+	pinfo->lcdc.h_pulse_width = MIPI_HSYNC_PULSE_WIDTH;
+	pinfo->lcdc.v_back_porch = MIPI_VSYNC_BACK_PORCH_LINES;
+	pinfo->lcdc.v_front_porch = MIPI_VSYNC_FRONT_PORCH_LINES;
+	pinfo->lcdc.v_pulse_width = MIPI_VSYNC_PULSE_WIDTH;
+	pinfo->mipi.num_of_lanes = TRULY_PANEL_NUM_OF_LANES;
+	pinfo->mipi.frame_rate = TRULY_PANEL_FRAME_RATE;
+
+	pinfo->type = MIPI_CMD_PANEL;
+	pinfo->wait_cycle = 0;
+	pinfo->bpp = TRULY_PANEL_BPP;
+	pinfo->clk_rate = TRULY_PANEL_CLK_RATE;
+
+	pinfo->mipi.mode = DSI_CMD_MODE;
+	pinfo->mipi.traffic_mode = 1;
+	pinfo->mipi.dst_format = DSI_VIDEO_DST_FORMAT_RGB888;
+	pinfo->mipi.vc = 0;
+	pinfo->mipi.lane_swap = TRULY_PANEL_LANE_SWAP;
+	pinfo->mipi.data_lane0 = TRUE;
+	pinfo->mipi.data_lane1 = TRUE;
+	pinfo->mipi.data_lane2 = FALSE;
+	pinfo->mipi.data_lane3 = FALSE;
+	pinfo->mipi.t_clk_post = TRULY_PANEL_T_CLK_POST;
+	pinfo->mipi.t_clk_pre = TRULY_PANEL_T_CLK_PRE;
+	pinfo->mipi.stream = 0;
+	pinfo->mipi.mdp_trigger = DSI_CMD_TRIGGER_NONE;
+	pinfo->mipi.dma_trigger = DSI_CMD_TRIGGER_SW;
+
+	pinfo->mipi.mdss_dsi_phy_db = &dsi_video_mode_phy_db;
+	pinfo->mipi.tx_eot_append = TRUE;
+
+	pinfo->mipi.panel_cmds = truly_wvga_panel_cmd_mode_cmds;
+	pinfo->mipi.num_of_panel_cmds = ARRAY_SIZE(truly_wvga_panel_cmd_mode_cmds);
+
+	pinfo->on = mipi_truly_cmd_wvga_on;
+	pinfo->off = mipi_truly_cmd_wvga_off;
+	pinfo->config = mipi_truly_cmd_wvga_config;
+
+	return;
+}
diff --git a/dev/panel/msm/rules.mk b/dev/panel/msm/rules.mk
index b3bdac3..56e6815 100644
--- a/dev/panel/msm/rules.mk
+++ b/dev/panel/msm/rules.mk
@@ -24,7 +24,8 @@
 ifeq ($(PLATFORM),msm8974)
 OBJS += \
 	$(LOCAL_DIR)/mipi_toshiba_video_720p.o \
-	$(LOCAL_DIR)/mipi_sharp_video_qhd.o
+	$(LOCAL_DIR)/mipi_sharp_video_qhd.o \
+	$(LOCAL_DIR)/edp_auo_1080p.o
 endif
 
 ifeq ($(PLATFORM),msm8226)
@@ -35,5 +36,6 @@
 
 ifeq ($(PLATFORM),msm8610)
 OBJS += \
-	$(LOCAL_DIR)/mipi_truly_video_wvga.o
+	$(LOCAL_DIR)/mipi_truly_video_wvga.o \
+	$(LOCAL_DIR)/mipi_truly_cmd_wvga.o
 endif
diff --git a/dev/pmic/pm8921/pm8921.c b/dev/pmic/pm8921/pm8921.c
index cafa6a8..9cf5e91 100644
--- a/dev/pmic/pm8921/pm8921.c
+++ b/dev/pmic/pm8921/pm8921.c
@@ -747,3 +747,23 @@
 
 	return 0;
 }
+
+int pm8921_configure_wled(void)
+{
+	pm8921_masked_write(WLED_BOOST_CFG_REG, 0xFF, 0x47);
+	pm8921_masked_write(WLED_HIGH_POLE_CAP_REG, 0xFF, 0x2c);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(2), 0xFF, 0x19);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(3), 0xFF, 0x59);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(4), 0xFF, 0x59);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(5), 0xFF, 0x66);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(6), 0xFF, 0x66);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(7), 0xFF, 0x0f);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(8), 0xFF, 0xff);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(9), 0xFF, 0x0f);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(10), 0xFF, 0xff);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(12), 0xFF, 0x16);
+	pm8921_masked_write(SSBI_REG_ADDR_WLED_CTRL(13), 0xFF, 0x55);
+	pm8921_masked_write(WLED_MOD_CTRL_REG, 0xFF, 0x7f);
+	pm8921_masked_write(WLED_SYNC_REG, WLED_SYNC_MASK,	WLED_SYNC_VAL);
+	pm8921_masked_write(WLED_SYNC_REG, WLED_SYNC_MASK,	WLED_SYNC_RESET_VAL);
+}
diff --git a/dev/pmic/pm8921/pm8921_hw.h b/dev/pmic/pm8921/pm8921_hw.h
index ea3046f..02771ce 100644
--- a/dev/pmic/pm8921/pm8921_hw.h
+++ b/dev/pmic/pm8921/pm8921_hw.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012, Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2013, Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -154,6 +154,18 @@
 #define PLDO_TYPE                             0
 #define NLDO_TYPE                             1
 
+#define SSBI_REG_ADDR_WLED_CTRL_BASE    0x25A
+#define SSBI_REG_ADDR_WLED_CTRL(n)      (SSBI_REG_ADDR_WLED_CTRL_BASE + (n) - 1)
+
+/* wled control registers */
+#define WLED_MOD_CTRL_REG              SSBI_REG_ADDR_WLED_CTRL(1)
+#define WLED_SYNC_REG                  SSBI_REG_ADDR_WLED_CTRL(11)
+#define WLED_BOOST_CFG_REG             SSBI_REG_ADDR_WLED_CTRL(14)
+#define WLED_HIGH_POLE_CAP_REG         SSBI_REG_ADDR_WLED_CTRL(16)
+#define WLED_SYNC_VAL                  0x07
+#define WLED_SYNC_RESET_VAL            0x00
+#define WLED_SYNC_MASK                 0xF8
+
 #define PM8921_MVS_5V_HDMI_SWITCH             0x70
 
 #define LDO(_name, _type, _test_reg, _ctrl_reg) \
diff --git a/dev/pmic/pm8x41/include/pm8x41.h b/dev/pmic/pm8x41/include/pm8x41.h
index b230549..236aed7 100644
--- a/dev/pmic/pm8x41/include/pm8x41.h
+++ b/dev/pmic/pm8x41/include/pm8x41.h
@@ -202,5 +202,5 @@
 void pm8x41_config_output_mpp(struct pm8x41_mpp *mpp);
 void pm8x41_enable_mpp(struct pm8x41_mpp *mpp, enum mpp_en_ctl enable);
 uint8_t pm8x41_get_is_cold_boot();
-
+void pm8x41_diff_clock_ctrl(uint8_t enable);
 #endif
diff --git a/dev/pmic/pm8x41/include/pm8x41_hw.h b/dev/pmic/pm8x41/include/pm8x41_hw.h
index 9c10ab8..c8c83ce 100644
--- a/dev/pmic/pm8x41/include/pm8x41_hw.h
+++ b/dev/pmic/pm8x41/include/pm8x41_hw.h
@@ -105,4 +105,8 @@
 #define LDO_POWER_MODE                        0x45
 #define LDO_EN_CTL_REG                        0x46
 
+/* USB3 phy clock */
+#define DIFF_CLK1_EN_CTL                      0x5746
+#define DIFF_CLK1_EN_BIT                      7
+
 #endif
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index 0e1109b..915cf52 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -382,3 +382,22 @@
 	dprintf(INFO,"%s: cold boot\n", __func__);
 	return 1;
 }
+
+/* api to control diff clock */
+void pm8x41_diff_clock_ctrl(uint8_t enable)
+{
+	uint8_t reg;
+
+	reg = REG_READ(DIFF_CLK1_EN_CTL);
+
+	if (enable)
+	{
+		reg |= BIT(DIFF_CLK1_EN_BIT);
+	}
+	else
+	{
+		reg &= ~BIT(DIFF_CLK1_EN_BIT);
+	}
+
+	REG_WRITE(DIFF_CLK1_EN_CTL, reg);
+}
diff --git a/include/dev/udc.h b/include/dev/udc.h
index dc578a1..0dd1f86 100644
--- a/include/dev/udc.h
+++ b/include/dev/udc.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2009, Google Inc.
  * All rights reserved.
+ * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -9,7 +10,7 @@
  *    notice, this list of conditions and the following disclaimer.
  *  * Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the 
+ *    the documentation and/or other materials provided with the
  *    distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
@@ -19,7 +20,7 @@
  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
@@ -77,7 +78,7 @@
 	const char *product;
 	const char *serialno;
 };
-	
+
 int udc_init(struct udc_device *devinfo);
 int udc_register_gadget(struct udc_gadget *gadget);
 int udc_start(void);
@@ -95,12 +96,16 @@
 #define GET_INTERFACE        10
 #define SET_INTERFACE        11
 #define SYNCH_FRAME          12
+#define SET_SEL              48
 
 #define TYPE_DEVICE          1
 #define TYPE_CONFIGURATION   2
 #define TYPE_STRING          3
 #define TYPE_INTERFACE       4
 #define TYPE_ENDPOINT        5
+#define TYPE_BOS             15
+#define TYPE_DEVICE_CAP      16
+#define TYPE_SS_EP_COMP      48
 
 #define DEVICE_READ          0x80
 #define DEVICE_WRITE         0x00
diff --git a/platform/fsm9900/acpuclock.c b/platform/fsm9900/acpuclock.c
new file mode 100644
index 0000000..f92f940
--- /dev/null
+++ b/platform/fsm9900/acpuclock.c
@@ -0,0 +1,338 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <err.h>
+#include <assert.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/timer.h>
+#include <platform/iomap.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/clock.h>
+#include <blsp_qup.h>
+
+void hsusb_clock_init(void)
+{
+	int ret;
+	struct clk *iclk, *cclk;
+
+	ret = clk_get_set_enable("usb_iface_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_get_set_enable("usb_core_clk", 75000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	mdelay(20);
+
+	iclk = clk_get("usb_iface_clk");
+	cclk = clk_get("usb_core_clk");
+
+	clk_disable(iclk);
+	clk_disable(cclk);
+
+	mdelay(20);
+
+	/* Start the block reset for usb */
+	writel(1, USB_HS_BCR);
+
+	mdelay(20);
+
+	/* Take usb block out of reset */
+	writel(0, USB_HS_BCR);
+
+	mdelay(20);
+
+	ret = clk_enable(iclk);
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	ret = clk_enable(cclk);
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb_iface_clk after async ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+}
+
+void clock_init_mmc(uint32_t interface)
+{
+	char clk_name[64];
+	int ret;
+
+	snprintf(clk_name, 64, "sdc%u_iface_clk", interface);
+
+	/* enable interface clock */
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc1_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+	int ret;
+	uint32_t reg;
+	char clk_name[64];
+
+	snprintf(clk_name, 64, "sdc%u_core_clk", interface);
+
+	/* Disalbe MCI_CLK before changing the sdcc clock */
+#ifndef MMC_SDHCI_SUPPORT
+	mmc_boot_mci_clk_disable();
+#endif
+
+	if(freq == MMC_CLK_400KHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 400000, 1);
+	}
+	else if(freq == MMC_CLK_50MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 50000000, 1);
+	}
+	else if(freq == MMC_CLK_96MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 100000000, 1);
+	}
+	else if(freq == MMC_CLK_200MHZ)
+	{
+		ret = clk_get_set_enable(clk_name, 200000000, 1);
+	}
+	else
+	{
+		dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+		ASSERT(0);
+	}
+
+
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Enalbe MCI clock */
+#ifndef MMC_SDHCI_SUPPORT
+	mmc_boot_mci_clk_enable();
+#endif
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+	int ret;
+	char str[256];
+
+	sprintf(str, "uart%d_iface_clk", id);
+	ret = clk_get_set_enable(str, 0, 1);
+    	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set uart2_iface_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	sprintf(str, "uart%d_core_clk", id);
+	ret = clk_get_set_enable(str, 7372800, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set uart1_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
+
+/* Function to asynchronously reset CE.
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+	if (instance == 1)
+	{
+		/* TODO: Add support for instance 1. */
+		dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+		ASSERT(0);
+	}
+	else if (instance == 2)
+	{
+		/* Start the block reset for CE */
+		writel(1, GCC_CE2_BCR);
+
+		udelay(2);
+
+		/* Take CE block out of reset */
+		writel(0, GCC_CE2_BCR);
+
+		udelay(2);
+	}
+	else
+	{
+		dprintf(CRITICAL, "CE instance not supported instance = %d", instance);
+		ASSERT(0);
+	}
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+	int ret;
+	char clk_name[64];
+
+	snprintf(clk_name, 64, "ce%u_src_clk", instance);
+	ret = clk_get_set_enable(clk_name, 100000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_src_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	snprintf(clk_name, 64, "ce%u_core_clk", instance);
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_core_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_ahb_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+	ret = clk_get_set_enable(clk_name, 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set ce_axi_clk ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	/* Wait for 48 * #pipes cycles.
+	 * This is necessary as immediately after an access control reset (boot up)
+	 * or a debug re-enable, the Crypto core sequentially clears its internal
+	 * pipe key storage memory. If pipe key initialization writes are attempted
+	 * during this time, they may be overwritten by the internal clearing logic.
+	 */
+	udelay(1);
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+	struct clk *ahb_clk;
+	struct clk *cclk;
+	struct clk *axi_clk;
+	struct clk *src_clk;
+	char clk_name[64];
+
+	snprintf(clk_name, 64, "ce%u_src_clk", instance);
+	src_clk = clk_get(clk_name);
+
+	snprintf(clk_name, 64, "ce%u_ahb_clk", instance);
+	ahb_clk = clk_get(clk_name);
+
+	snprintf(clk_name, 64, "ce%u_axi_clk", instance);
+	axi_clk = clk_get(clk_name);
+
+	snprintf(clk_name, 64, "ce%u_core_clk", instance);
+	cclk    = clk_get(clk_name);
+
+	clk_disable(ahb_clk);
+	clk_disable(axi_clk);
+	clk_disable(cclk);
+	clk_disable(src_clk);
+
+	/* Some delay for the clocks to stabalize. */
+	udelay(1);
+}
+
+void clock_config_ce(uint8_t instance)
+{
+	/* Need to enable the clock before disabling since the clk_disable()
+	 * has a check to default to nop when the clk_enable() is not called
+	 * on that particular clock.
+	 */
+	clock_ce_enable(instance);
+
+	clock_ce_disable(instance);
+
+	ce_async_reset(instance);
+
+	clock_ce_enable(instance);
+
+}
+
+void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+	uint8_t ret = 0;
+	char clk_name[64];
+
+	struct clk *qup_clk;
+
+	snprintf(clk_name, 64, "blsp%u_ahb_clk", blsp_id);
+
+	ret = clk_get_set_enable(clk_name, 0 , 1);
+
+	if (ret) {
+		dprintf(CRITICAL, "Failed to enable %s clock\n", clk_name);
+		return;
+	}
+
+	snprintf(clk_name, 64, "blsp%u_qup%u_i2c_apps_clk", blsp_id,
+							(qup_id + 1));
+
+	qup_clk = clk_get(clk_name);
+
+	if (!qup_clk) {
+		dprintf(CRITICAL, "Failed to get %s\n", clk_name);
+		return;
+	}
+
+	ret = clk_enable(qup_clk);
+
+	if (ret) {
+		dprintf(CRITICAL, "Failed to enable %s\n", clk_name);
+		return;
+	}
+}
diff --git a/platform/fsm9900/fsm9900-clock.c b/platform/fsm9900/fsm9900-clock.c
new file mode 100644
index 0000000..a9955fc
--- /dev/null
+++ b/platform/fsm9900/fsm9900-clock.c
@@ -0,0 +1,815 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val    0
+#define gpll0_source_val  1
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_branch =
+{
+	.enable     = clock_lib2_branch_clk_enable,
+	.disable    = clock_lib2_branch_clk_disable,
+	.set_rate   = clock_lib2_branch_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+	.enable     = clock_lib2_rcg_enable,
+	.set_rate   = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+	.enable     = cxo_clk_enable,
+	.disable    = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+	.enable     = pll_vote_clk_enable,
+	.disable    = pll_vote_clk_disable,
+	.auto_off   = pll_vote_clk_disable,
+	.is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+	.enable     = clock_lib2_vote_clk_enable,
+	.disable    = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+	.c = {
+		.rate     = 19200000,
+		.dbg_name = "cxo_clk_src",
+		.ops      = &clk_ops_cxo,
+	},
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+	.en_reg       = (void *) APCS_GPLL_ENA_VOTE,
+	.en_mask      = BIT(0),
+	.status_reg   = (void *) GPLL0_STATUS,
+	.status_mask  = BIT(17),
+	.parent       = &cxo_clk_src.c,
+
+	.c = {
+		.rate     = 600000000,
+		.dbg_name = "gpll0_clk_src",
+		.ops      = &clk_ops_pll_vote,
+	},
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] =
+{
+	F(   144000,    cxo,  16,   3,  25),
+	F(   400000,    cxo,  12,   1,   4),
+	F( 20000000,  gpll0,  15,   1,   2),
+	F( 25000000,  gpll0,  12,   1,   2),
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F(200000000,  gpll0,   3,   0,   0),
+	F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC1_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC1_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC1_M,
+	.n_reg        = (uint32_t *) SDCC1_N,
+	.d_reg        = (uint32_t *) SDCC1_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_2_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc1_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_APPS_CBCR,
+	.parent       = &sdcc1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC1_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc1_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) SDCC2_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) SDCC2_CFG_RCGR,
+	.m_reg        = (uint32_t *) SDCC2_M,
+	.n_reg        = (uint32_t *) SDCC2_N,
+	.d_reg        = (uint32_t *) SDCC2_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_sdcc1_2_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "sdc2_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC2_APPS_CBCR,
+	.parent       = &sdcc2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_sdcc2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) SDCC2_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sdcc2_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+	F( 3686400,  gpll0,    1,  96,  15625),
+	F( 7372800,  gpll0,    1, 192,  15625),
+	F(14745600,  gpll0,    1, 384,  15625),
+	F(16000000,  gpll0,    5,   2,     15),
+	F(19200000,    cxo,    1,   0,      0),
+	F(24000000,  gpll0,    5,   1,      5),
+	F(32000000,  gpll0,    1,   4,     75),
+	F(40000000,  gpll0,   15,   0,      0),
+	F(46400000,  gpll0,    1,  29,    375),
+	F(48000000,  gpll0, 12.5,   0,      0),
+	F(51200000,  gpll0,    1,  32,    375),
+	F(56000000,  gpll0,    1,   7,     75),
+	F(58982400,  gpll0,    1, 1536, 15625),
+	F(60000000,  gpll0,   10,   0,      0),
+	F_END
+};
+
+static struct rcg_clk blsp1_uart0_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART0_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART0_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART0_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART0_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART0_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart0_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart0_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART0_APPS_CBCR,
+	.parent       = &blsp1_uart0_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart0_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART1_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART1_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART1_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART1_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART1_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart1_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART1_APPS_CBCR,
+	.parent       = &blsp1_uart1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART2_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART2_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART2_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+	.parent       = &blsp1_uart2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart3_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART3_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART3_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART3_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart3_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART3_APPS_CBCR,
+	.parent       = &blsp1_uart3_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart3_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart4_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART4_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART4_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART4_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART4_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART4_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart4_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart4_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART4_APPS_CBCR,
+	.parent       = &blsp1_uart4_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart4_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp1_uart5_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP1_UART5_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP1_UART5_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP1_UART5_APPS_M,
+	.n_reg        = (uint32_t *) BLSP1_UART5_APPS_N,
+	.d_reg        = (uint32_t *) BLSP1_UART5_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp1_uart5_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp1_uart5_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP1_UART5_APPS_CBCR,
+	.parent       = &blsp1_uart5_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_uart5_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp2_uart0_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP2_UART0_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP2_UART0_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP2_UART0_APPS_M,
+	.n_reg        = (uint32_t *) BLSP2_UART0_APPS_N,
+	.d_reg        = (uint32_t *) BLSP2_UART0_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp2_uart0_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp2_uart0_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP2_UART0_APPS_CBCR,
+	.parent       = &blsp2_uart0_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp2_uart0_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp2_uart1_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP2_UART1_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP2_UART1_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP2_UART1_APPS_M,
+	.n_reg        = (uint32_t *) BLSP2_UART1_APPS_N,
+	.d_reg        = (uint32_t *) BLSP2_UART1_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp2_uart1_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp2_uart1_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP2_UART1_APPS_CBCR,
+	.parent       = &blsp2_uart1_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp2_uart1_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp2_uart2_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP2_UART2_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP2_UART2_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP2_UART2_APPS_M,
+	.n_reg        = (uint32_t *) BLSP2_UART2_APPS_N,
+	.d_reg        = (uint32_t *) BLSP2_UART2_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp2_uart2_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp2_uart2_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP2_UART2_APPS_CBCR,
+	.parent       = &blsp2_uart2_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp2_uart2_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp2_uart3_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP2_UART3_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP2_UART3_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP2_UART3_APPS_M,
+	.n_reg        = (uint32_t *) BLSP2_UART3_APPS_N,
+	.d_reg        = (uint32_t *) BLSP2_UART3_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp2_uart3_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp2_uart3_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP2_UART3_APPS_CBCR,
+	.parent       = &blsp2_uart3_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp2_uart3_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp2_uart4_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP2_UART4_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP2_UART4_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP2_UART4_APPS_M,
+	.n_reg        = (uint32_t *) BLSP2_UART4_APPS_N,
+	.d_reg        = (uint32_t *) BLSP2_UART4_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp2_uart4_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp2_uart4_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP2_UART4_APPS_CBCR,
+	.parent       = &blsp2_uart4_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp2_uart4_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct rcg_clk blsp2_uart5_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) BLSP2_UART5_APPS_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) BLSP2_UART5_APPS_CFG_RCGR,
+	.m_reg        = (uint32_t *) BLSP2_UART5_APPS_M,
+	.n_reg        = (uint32_t *) BLSP2_UART5_APPS_N,
+	.d_reg        = (uint32_t *) BLSP2_UART5_APPS_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "blsp2_uart5_apps_clk",
+		.ops      = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk gcc_blsp2_uart5_apps_clk =
+{
+	.cbcr_reg     = (uint32_t *) BLSP2_UART5_APPS_CBCR,
+	.parent       = &blsp2_uart5_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp2_uart5_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+	.cbcr_reg     = (uint32_t *) BLSP1_AHB_CBCR,
+	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask      = BIT(17),
+
+	.c = {
+		.dbg_name = "gcc_blsp1_ahb_clk",
+		.ops      = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_blsp2_ahb_clk = {
+	.cbcr_reg     = (uint32_t *) BLSP2_AHB_CBCR,
+	.vote_reg     = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask      = BIT(15),
+
+	.c = {
+		.dbg_name = "gcc_blsp2_ahb_clk",
+		.ops      = &clk_ops_vote,
+	},
+};
+
+/* USB Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] =
+{
+	F(75000000,  gpll0,   8,   0,   0),
+	F_END
+};
+
+static struct rcg_clk usb_hs_system_clk_src =
+{
+	.cmd_reg      = (uint32_t *) USB_HS_SYSTEM_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) USB_HS_SYSTEM_CFG_RCGR,
+
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_usb_hs_system_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb_hs_system_clk",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_system_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_SYSTEM_CBCR,
+	.parent       = &usb_hs_system_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_system_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_usb_hs_ahb_clk =
+{
+	.cbcr_reg     = (uint32_t *) USB_HS_AHB_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_usb_hs_ahb_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* CE Clocks */
+static struct clk_freq_tbl ftbl_gcc_ce2_clk[] = {
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F_END
+};
+
+static struct rcg_clk ce2_clk_src = {
+	.cmd_reg      = (uint32_t *) GCC_CE2_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_CE2_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_ce2_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "ce2_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct vote_clk gcc_ce2_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE2_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(2),
+
+	.c = {
+		.dbg_name = "gcc_ce2_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce2_ahb_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE2_AHB_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(0),
+
+	.c = {
+		.dbg_name = "gcc_ce2_ahb_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce2_axi_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE2_AXI_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(1),
+
+	.c = {
+		.dbg_name = "gcc_ce2_axi_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct clk_freq_tbl ftbl_gcc_ce1_clk[] = {
+	F( 50000000,  gpll0,  12,   0,   0),
+	F(100000000,  gpll0,   6,   0,   0),
+	F_END
+};
+
+static struct rcg_clk ce1_clk_src = {
+	.cmd_reg      = (uint32_t *) GCC_CE1_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_CE1_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_ce1_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "ce1_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct vote_clk gcc_ce1_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE1_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(5),
+
+	.c = {
+		.dbg_name = "gcc_ce1_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce1_ahb_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE1_AHB_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(3),
+
+	.c = {
+		.dbg_name = "gcc_ce1_ahb_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+static struct vote_clk gcc_ce1_axi_clk = {
+	.cbcr_reg = (uint32_t *) GCC_CE1_AXI_CBCR,
+	.vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+	.en_mask = BIT(4),
+
+	.c = {
+		.dbg_name = "gcc_ce1_axi_clk",
+		.ops = &clk_ops_vote,
+	},
+};
+
+
+struct branch_clk gcc_blsp2_qup5_i2c_apps_clk = {
+	.cbcr_reg = BLSP2_QUP5_I2C_APPS_CBCR,
+	.parent   = &cxo_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp2_qup5_i2c_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+/* Clock lookup table */
+static struct clk_lookup msm_clocks_fsm9900[] =
+{
+	CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+	CLK_LOOKUP("sdc1_core_clk",  gcc_sdcc1_apps_clk.c),
+
+	CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+	CLK_LOOKUP("sdc2_core_clk",  gcc_sdcc2_apps_clk.c),
+
+	CLK_LOOKUP("uart0_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart0_core_clk",  gcc_blsp1_uart0_apps_clk.c),
+	CLK_LOOKUP("uart1_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart1_core_clk",  gcc_blsp1_uart1_apps_clk.c),
+	CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart2_core_clk",  gcc_blsp1_uart2_apps_clk.c),
+	CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart3_core_clk",  gcc_blsp1_uart3_apps_clk.c),
+	CLK_LOOKUP("uart4_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart4_core_clk",  gcc_blsp1_uart4_apps_clk.c),
+	CLK_LOOKUP("uart5_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("uart5_core_clk",  gcc_blsp1_uart5_apps_clk.c),
+	CLK_LOOKUP("uart6_iface_clk", gcc_blsp2_ahb_clk.c),
+	CLK_LOOKUP("uart6_core_clk",  gcc_blsp2_uart0_apps_clk.c),
+	CLK_LOOKUP("uart7_iface_clk", gcc_blsp2_ahb_clk.c),
+	CLK_LOOKUP("uart7_core_clk",  gcc_blsp2_uart1_apps_clk.c),
+	CLK_LOOKUP("uart8_iface_clk", gcc_blsp2_ahb_clk.c),
+	CLK_LOOKUP("uart8_core_clk",  gcc_blsp2_uart2_apps_clk.c),
+	CLK_LOOKUP("uart9_iface_clk", gcc_blsp2_ahb_clk.c),
+	CLK_LOOKUP("uart9_core_clk",  gcc_blsp2_uart3_apps_clk.c),
+	CLK_LOOKUP("uart10_iface_clk", gcc_blsp2_ahb_clk.c),
+	CLK_LOOKUP("uart10_core_clk",  gcc_blsp2_uart4_apps_clk.c),
+	CLK_LOOKUP("uart11_iface_clk", gcc_blsp2_ahb_clk.c),
+	CLK_LOOKUP("uart11_core_clk",  gcc_blsp2_uart5_apps_clk.c),
+
+	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
+	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
+
+	CLK_LOOKUP("ce2_ahb_clk",  gcc_ce2_ahb_clk.c),
+	CLK_LOOKUP("ce2_axi_clk",  gcc_ce2_axi_clk.c),
+	CLK_LOOKUP("ce2_core_clk", gcc_ce2_clk.c),
+	CLK_LOOKUP("ce2_src_clk",  ce2_clk_src.c),
+
+	CLK_LOOKUP("ce1_ahb_clk",  gcc_ce1_ahb_clk.c),
+	CLK_LOOKUP("ce1_axi_clk",  gcc_ce1_axi_clk.c),
+	CLK_LOOKUP("ce1_core_clk", gcc_ce1_clk.c),
+	CLK_LOOKUP("ce1_src_clk",  ce1_clk_src.c),
+
+
+	CLK_LOOKUP("blsp2_ahb_clk",           gcc_blsp2_ahb_clk.c),
+	CLK_LOOKUP("blsp2_qup5_i2c_apps_clk", gcc_blsp2_qup5_i2c_apps_clk.c),
+};
+
+
+void platform_clock_init(void)
+{
+	clk_init(msm_clocks_fsm9900, ARRAY_SIZE(msm_clocks_fsm9900));
+}
diff --git a/platform/fsm9900/gpio.c b/platform/fsm9900/gpio.c
new file mode 100644
index 0000000..bbe4beb
--- /dev/null
+++ b/platform/fsm9900/gpio.c
@@ -0,0 +1,109 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+#include <gsbi.h>
+#include <blsp_qup.h>
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+		      uint8_t dir, uint8_t pull,
+		      uint8_t drvstr, uint32_t enable)
+{
+	uint32_t val = 0;
+	val |= pull;
+	val |= func << 2;
+	val |= drvstr << 6;
+	val |= enable << 9;
+	writel(val, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+	return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+	writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
+	return;
+}
+
+void gpio_config_uart_dm(uint8_t id)
+{
+	static struct {
+		unsigned int gpio_tx;
+		unsigned int gpio_rx;
+	} gpio_table[] = {
+		{ 0, 1 },
+		{ 4, 5 },
+		{ 8, 9 },
+		{ 12, 13 },
+		{ 16, 17 },
+		{ 20, 21 },
+		{ 24, 25 },
+		{ 28, 29 },
+		{ 32, 33 },
+		{ 36, 37 },
+	};
+
+	if (id >= ARRAY_SIZE(gpio_table))
+		return;
+
+	/* configure rx gpio */
+	gpio_tlmm_config(gpio_table[id].gpio_rx, 2, GPIO_INPUT, GPIO_NO_PULL,
+				GPIO_8MA, GPIO_DISABLE);
+
+	/* configure tx gpio */
+	gpio_tlmm_config(gpio_table[id].gpio_tx, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+				GPIO_8MA, GPIO_DISABLE);
+}
+
+void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
+{
+	if (blsp_id == BLSP_ID_2) {
+		switch (qup_id) {
+		case QUP_ID_4:
+			gpio_tlmm_config(83, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+						GPIO_6MA, GPIO_DISABLE);
+			gpio_tlmm_config(84, 3, GPIO_OUTPUT, GPIO_NO_PULL,
+						GPIO_6MA, GPIO_DISABLE);
+		break;
+		default:
+			dprintf(CRITICAL, "Configure gpios for QUP instance: %u\n",
+					  qup_id);
+			ASSERT(0);
+		};
+	}
+	else if (blsp_id == BLSP_ID_1) {
+		switch (qup_id) {
+		default:
+			dprintf(CRITICAL, "Configure gpios for QUP instance: %u\n",
+					   qup_id);
+			ASSERT(0);
+		};
+	}
+}
diff --git a/platform/fsm9900/include/platform/clock.h b/platform/fsm9900/include/platform/clock.h
new file mode 100644
index 0000000..e19920d
--- /dev/null
+++ b/platform/fsm9900/include/platform/clock.h
@@ -0,0 +1,47 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __FSM9900_CLOCK_H
+#define __FSM9900_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xFF
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+
+#endif
diff --git a/platform/fsm9900/include/platform/gpio.h b/platform/fsm9900/include/platform/gpio.h
new file mode 100644
index 0000000..334ba7c
--- /dev/null
+++ b/platform/fsm9900/include/platform/gpio.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *  * Neither the name of The Linux Foundation, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_FSM9900_GPIO_H
+#define __PLATFORM_FSM9900_GPIO_H
+
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT      0
+#define GPIO_OUTPUT     1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL    0
+#define GPIO_PULL_DOWN  1
+#define GPIO_KEEPER     2
+#define GPIO_PULL_UP    3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA        0
+#define GPIO_4MA        1
+#define GPIO_6MA        2
+#define GPIO_8MA        3
+#define GPIO_10MA       4
+#define GPIO_12MA       5
+#define GPIO_14MA       6
+#define GPIO_16MA       7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE     0
+#define GPIO_DISABLE    1
+
+void gpio_config_uart_dm(uint8_t id);
+void gpio_config_blsp_i2c(uint8_t, uint8_t);
+#endif
diff --git a/platform/fsm9900/include/platform/iomap.h b/platform/fsm9900/include/platform/iomap.h
new file mode 100644
index 0000000..c8fdcf9
--- /dev/null
+++ b/platform/fsm9900/include/platform/iomap.h
@@ -0,0 +1,267 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_FSM9900_IOMAP_H_
+#define _PLATFORM_FSM9900_IOMAP_H_
+
+#define MSM_IOMAP_BASE              0xF9000000
+#define MSM_IOMAP_END               0xFEFFFFFF
+
+#define SDRAM_START_ADDR            0x00000000
+#define SDRAM_SEC_BANK_START_ADDR   0x10000000
+
+#define MSM_SHARED_BASE             0x0FA00000
+
+#define RPM_MSG_RAM_BASE            0xFC42B000
+#define SYSTEM_IMEM_BASE            0xFE800000
+#define MSM_SHARED_IMEM_BASE        0xFE805000
+
+#define RESTART_REASON_ADDR             (RPM_MSG_RAM_BASE     + 0x65C)
+#define RESTART_REASON_ADDR_V2          (MSM_SHARED_IMEM_BASE + 0x65C)
+#define DLOAD_MODE_ADDR_V2              (MSM_SHARED_IMEM_BASE + 0x0)
+#define EMERGENCY_DLOAD_MODE_ADDR_V2    (MSM_SHARED_IMEM_BASE + 0xFE0)
+
+#define KPSS_BASE                   0xF9000000
+
+#define MSM_GIC_DIST_BASE           KPSS_BASE
+#define MSM_GIC_CPU_BASE            (KPSS_BASE + 0x2000)
+#define APCS_KPSS_ACS_BASE          (KPSS_BASE + 0x00008000)
+#define APCS_APC_KPSS_PLL_BASE      (KPSS_BASE + 0x0000A000)
+#define APCS_KPSS_CFG_BASE          (KPSS_BASE + 0x00010000)
+#define APCS_KPSS_WDT_BASE          (KPSS_BASE + 0x00017000)
+#define KPSS_APCS_QTMR_AC_BASE      (KPSS_BASE + 0x00020000)
+#define KPSS_APCS_F0_QTMR_V1_BASE   (KPSS_BASE + 0x00021000)
+#define QTMR_BASE                   KPSS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE              0xF9800000
+
+#define MSM_SDC1_BAM_BASE           (PERIPH_SS_BASE + 0x00004000)
+#define MSM_SDC1_BASE               (PERIPH_SS_BASE + 0x00024000)
+#define MSM_SDC1_DML_BASE           (PERIPH_SS_BASE + 0x00024800)
+#define MSM_SDC1_SDHCI_BASE         (PERIPH_SS_BASE + 0x00024900)
+#define MSM_SDC2_BAM_BASE           (PERIPH_SS_BASE + 0x00084000)
+#define MSM_SDC2_BASE               (PERIPH_SS_BASE + 0x000A4000)
+#define MSM_SDC2_DML_BASE           (PERIPH_SS_BASE + 0x000A4800)
+#define MSM_SDC2_SDHCI_BASE         (PERIPH_SS_BASE + 0x000A4900)
+
+/* BLSP1_UART[0:5] */
+#define BLSP1_UART0_BASE            (PERIPH_SS_BASE + 0x0011D000)
+#define BLSP1_UART1_BASE            (PERIPH_SS_BASE + 0x0011E000)
+#define BLSP1_UART2_BASE            (PERIPH_SS_BASE + 0x0011F000)
+#define BLSP1_UART3_BASE            (PERIPH_SS_BASE + 0x00120000)
+#define BLSP1_UART4_BASE            (PERIPH_SS_BASE + 0x00121000)
+#define BLSP1_UART5_BASE            (PERIPH_SS_BASE + 0x00122000)
+
+/* BLSP2_UART[0:5] */
+#define BLSP2_UART0_BASE            (PERIPH_SS_BASE + 0x0015D000)
+#define BLSP2_UART1_BASE            (PERIPH_SS_BASE + 0x0015E000)
+#define BLSP2_UART2_BASE            (PERIPH_SS_BASE + 0x0015F000)
+#define BLSP2_UART3_BASE            (PERIPH_SS_BASE + 0x00160000)
+#define BLSP2_UART4_BASE            (PERIPH_SS_BASE + 0x00161000)
+#define BLSP2_UART5_BASE            (PERIPH_SS_BASE + 0x00162000)
+
+#define CLK_CTL_BASE                0xFC400000
+
+#define GCC_WDOG_DEBUG              (CLK_CTL_BASE +  0x00001780)
+
+#define USB_HS_BCR                  (CLK_CTL_BASE + 0x480)
+
+#define SPMI_BASE                   0xFC4C0000
+#define SPMI_GENI_BASE              (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE               (SPMI_BASE + 0xB000)
+
+#define MSM_CE2_BAM_BASE            0xFD444000
+#define MSM_CE2_BASE                0xFD45A000
+
+#define TLMM_BASE_ADDR              0xFD510000
+#define GPIO_CONFIG_ADDR(x)         (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
+#define GPIO_IN_OUT_ADDR(x)         (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
+
+#define MPM2_MPM_CTRL_BASE                   0xFC4A1000
+#define MPM2_MPM_PS_HOLD                     0xFC4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL    0xFC4A3000
+
+/* CE 1 */
+#define  GCC_CE1_BCR                (CLK_CTL_BASE + 0x1040)
+#define  GCC_CE1_CMD_RCGR           (CLK_CTL_BASE + 0x1050)
+#define  GCC_CE1_CFG_RCGR           (CLK_CTL_BASE + 0x1054)
+#define  GCC_CE1_CBCR               (CLK_CTL_BASE + 0x1044)
+#define  GCC_CE1_AXI_CBCR           (CLK_CTL_BASE + 0x1048)
+#define  GCC_CE1_AHB_CBCR           (CLK_CTL_BASE + 0x104C)
+
+/* CE 2 */
+#define  GCC_CE2_BCR                (CLK_CTL_BASE + 0x1080)
+#define  GCC_CE2_CMD_RCGR           (CLK_CTL_BASE + 0x1090)
+#define  GCC_CE2_CFG_RCGR           (CLK_CTL_BASE + 0x1094)
+#define  GCC_CE2_CBCR               (CLK_CTL_BASE + 0x1084)
+#define  GCC_CE2_AXI_CBCR           (CLK_CTL_BASE + 0x1088)
+#define  GCC_CE2_AHB_CBCR           (CLK_CTL_BASE + 0x108C)
+
+/* GPLL */
+#define GPLL0_STATUS                (CLK_CTL_BASE + 0x001C)
+#define APCS_GPLL_ENA_VOTE          (CLK_CTL_BASE + 0x1480)
+#define APCS_CLOCK_BRANCH_ENA_VOTE  (CLK_CTL_BASE + 0x1484)
+
+/* SDCC 1 */
+#define SDCC1_BCR                   (CLK_CTL_BASE + 0x4C0) /* block reset */
+#define SDCC1_APPS_CBCR             (CLK_CTL_BASE + 0x4C4) /* branch control */
+#define SDCC1_AHB_CBCR              (CLK_CTL_BASE + 0x4C8)
+#define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC)
+#define SDCC1_CMD_RCGR              (CLK_CTL_BASE + 0x4D0) /* cmd */
+#define SDCC1_CFG_RCGR              (CLK_CTL_BASE + 0x4D4) /* cfg */
+#define SDCC1_M                     (CLK_CTL_BASE + 0x4D8) /* m */
+#define SDCC1_N                     (CLK_CTL_BASE + 0x4DC) /* n */
+#define SDCC1_D                     (CLK_CTL_BASE + 0x4E0) /* d */
+
+/* SDCC2 */
+#define SDCC2_BCR                   (CLK_CTL_BASE + 0x500) /* block reset */
+#define SDCC2_APPS_CBCR             (CLK_CTL_BASE + 0x504) /* branch control */
+#define SDCC2_AHB_CBCR              (CLK_CTL_BASE + 0x508)
+#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
+#define SDCC2_CMD_RCGR              (CLK_CTL_BASE + 0x510) /* cmd */
+#define SDCC2_CFG_RCGR              (CLK_CTL_BASE + 0x514) /* cfg */
+#define SDCC2_M                     (CLK_CTL_BASE + 0x518) /* m */
+#define SDCC2_N                     (CLK_CTL_BASE + 0x51C) /* n */
+#define SDCC2_D                     (CLK_CTL_BASE + 0x520) /* d */
+
+/* UART
+   BLSP1_UART[0:5]
+   BLSP2_UART[0:5]
+*/
+#define BLSP1_AHB_CBCR              (CLK_CTL_BASE + 0x5C4)
+#define BLSP2_AHB_CBCR              (CLK_CTL_BASE + 0x944)
+
+#define BLSP1_UART0_APPS_CBCR       (CLK_CTL_BASE + 0x684)
+#define BLSP1_UART0_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x68C)
+#define BLSP1_UART0_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x690)
+#define BLSP1_UART0_APPS_M          (CLK_CTL_BASE + 0x694)
+#define BLSP1_UART0_APPS_N          (CLK_CTL_BASE + 0x698)
+#define BLSP1_UART0_APPS_D          (CLK_CTL_BASE + 0x69C)
+
+#define BLSP1_UART1_APPS_CBCR       (CLK_CTL_BASE + 0x704)
+#define BLSP1_UART1_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x70C)
+#define BLSP1_UART1_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x710)
+#define BLSP1_UART1_APPS_M          (CLK_CTL_BASE + 0x714)
+#define BLSP1_UART1_APPS_N          (CLK_CTL_BASE + 0x718)
+#define BLSP1_UART1_APPS_D          (CLK_CTL_BASE + 0x71C)
+
+#define BLSP1_UART2_APPS_CBCR       (CLK_CTL_BASE + 0x784)
+#define BLSP1_UART2_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x78C)
+#define BLSP1_UART2_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x790)
+#define BLSP1_UART2_APPS_M          (CLK_CTL_BASE + 0x794)
+#define BLSP1_UART2_APPS_N          (CLK_CTL_BASE + 0x798)
+#define BLSP1_UART2_APPS_D          (CLK_CTL_BASE + 0x79C)
+
+#define BLSP1_UART3_APPS_CBCR       (CLK_CTL_BASE + 0x804)
+#define BLSP1_UART3_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x80C)
+#define BLSP1_UART3_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x810)
+#define BLSP1_UART3_APPS_M          (CLK_CTL_BASE + 0x814)
+#define BLSP1_UART3_APPS_N          (CLK_CTL_BASE + 0x818)
+#define BLSP1_UART3_APPS_D          (CLK_CTL_BASE + 0x81C)
+
+#define BLSP1_UART4_APPS_CBCR       (CLK_CTL_BASE + 0x884)
+#define BLSP1_UART4_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x88C)
+#define BLSP1_UART4_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x890)
+#define BLSP1_UART4_APPS_M          (CLK_CTL_BASE + 0x894)
+#define BLSP1_UART4_APPS_N          (CLK_CTL_BASE + 0x898)
+#define BLSP1_UART4_APPS_D          (CLK_CTL_BASE + 0x89C)
+
+#define BLSP1_UART5_APPS_CBCR       (CLK_CTL_BASE + 0x904)
+#define BLSP1_UART5_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x90C)
+#define BLSP1_UART5_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x910)
+#define BLSP1_UART5_APPS_M          (CLK_CTL_BASE + 0x914)
+#define BLSP1_UART5_APPS_N          (CLK_CTL_BASE + 0x918)
+#define BLSP1_UART5_APPS_D          (CLK_CTL_BASE + 0x91C)
+
+#define BLSP2_UART0_APPS_CBCR       (CLK_CTL_BASE + 0x9C4)
+#define BLSP2_UART0_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x9CC)
+#define BLSP2_UART0_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x9D0)
+#define BLSP2_UART0_APPS_M          (CLK_CTL_BASE + 0x9D4)
+#define BLSP2_UART0_APPS_N          (CLK_CTL_BASE + 0x9D8)
+#define BLSP2_UART0_APPS_D          (CLK_CTL_BASE + 0x9DC)
+
+#define BLSP2_UART1_APPS_CBCR       (CLK_CTL_BASE + 0xA44)
+#define BLSP2_UART1_APPS_CMD_RCGR   (CLK_CTL_BASE + 0xA4C)
+#define BLSP2_UART1_APPS_CFG_RCGR   (CLK_CTL_BASE + 0xA50)
+#define BLSP2_UART1_APPS_M          (CLK_CTL_BASE + 0xA54)
+#define BLSP2_UART1_APPS_N          (CLK_CTL_BASE + 0xA58)
+#define BLSP2_UART1_APPS_D          (CLK_CTL_BASE + 0xA5C)
+
+#define BLSP2_UART2_APPS_CBCR       (CLK_CTL_BASE + 0xAC4)
+#define BLSP2_UART2_APPS_CMD_RCGR   (CLK_CTL_BASE + 0xACC)
+#define BLSP2_UART2_APPS_CFG_RCGR   (CLK_CTL_BASE + 0xAD0)
+#define BLSP2_UART2_APPS_M          (CLK_CTL_BASE + 0xAD4)
+#define BLSP2_UART2_APPS_N          (CLK_CTL_BASE + 0xAD8)
+#define BLSP2_UART2_APPS_D          (CLK_CTL_BASE + 0xADC)
+
+#define BLSP2_UART3_APPS_CBCR       (CLK_CTL_BASE + 0xB44)
+#define BLSP2_UART3_APPS_CMD_RCGR   (CLK_CTL_BASE + 0xB4C)
+#define BLSP2_UART3_APPS_CFG_RCGR   (CLK_CTL_BASE + 0xB50)
+#define BLSP2_UART3_APPS_M          (CLK_CTL_BASE + 0xB54)
+#define BLSP2_UART3_APPS_N          (CLK_CTL_BASE + 0xB58)
+#define BLSP2_UART3_APPS_D          (CLK_CTL_BASE + 0xB5C)
+
+#define BLSP2_UART4_APPS_CBCR       (CLK_CTL_BASE + 0xBC4)
+#define BLSP2_UART4_APPS_CMD_RCGR   (CLK_CTL_BASE + 0xBCC)
+#define BLSP2_UART4_APPS_CFG_RCGR   (CLK_CTL_BASE + 0xBD0)
+#define BLSP2_UART4_APPS_M          (CLK_CTL_BASE + 0xBD4)
+#define BLSP2_UART4_APPS_N          (CLK_CTL_BASE + 0xBD8)
+#define BLSP2_UART4_APPS_D          (CLK_CTL_BASE + 0xBDC)
+
+#define BLSP2_UART5_APPS_CBCR       (CLK_CTL_BASE + 0xC44)
+#define BLSP2_UART5_APPS_CMD_RCGR   (CLK_CTL_BASE + 0xC4C)
+#define BLSP2_UART5_APPS_CFG_RCGR   (CLK_CTL_BASE + 0xC50)
+#define BLSP2_UART5_APPS_M          (CLK_CTL_BASE + 0xC54)
+#define BLSP2_UART5_APPS_N          (CLK_CTL_BASE + 0xC58)
+#define BLSP2_UART5_APPS_D          (CLK_CTL_BASE + 0xC5C)
+
+/* USB */
+#define USB_HS_SYSTEM_CBCR          (CLK_CTL_BASE + 0x484)
+#define USB_HS_AHB_CBCR             (CLK_CTL_BASE + 0x488)
+#define USB_HS_SYSTEM_CMD_RCGR      (CLK_CTL_BASE + 0x490)
+#define USB_HS_SYSTEM_CFG_RCGR      (CLK_CTL_BASE + 0x494)
+
+/* I2C */
+#define BLSP2_QUP5_I2C_APPS_CBCR    (CLK_CTL_BASE + 0xB88)
+
+#define BLSP_QUP_BASE(blsp_id, qup_id)   ((blsp_id == 1) ? \
+                                         (PERIPH_SS_BASE + 0x00123000 \
+                                         + (qup_id * 0x1000)) :\
+                                         (PERIPH_SS_BASE + 0x00163000 + \
+                                         (qup_id * 0x1000)))
+
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL           (TLMM_BASE_ADDR + 0x00002044)
+
+/* SDHCI */
+#define SDCC_MCI_HC_MODE            (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG   (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG     (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG    (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG      (0x000000E8)
+#endif
diff --git a/platform/fsm9900/include/platform/irqs.h b/platform/fsm9900/include/platform/irqs.h
new file mode 100644
index 0000000..955438b
--- /dev/null
+++ b/platform/fsm9900/include/platform/irqs.h
@@ -0,0 +1,70 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above
+ *     copyright notice, this list of conditions and the following
+ *     disclaimer in the documentation and/or other materials provided
+ *     with the distribution.
+ *   * Neither the name of The Linux Foundation, Inc. nor the names of its
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __IRQS_FSM9900_H
+#define __IRQS_FSM9900_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15:  STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+:   SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START                          16
+#define GIC_SPI_START                          32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP      (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP             (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP      (GIC_SPI_START + 8)
+
+#define USB1_HS_BAM_IRQ                        (GIC_SPI_START + 135)
+#define USB1_HS_IRQ                            (GIC_SPI_START + 134)
+#define USB1_IRQ                               (GIC_SPI_START + 142)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS                             USB1_HS_IRQ
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ         (GIC_SPI_START + 190)
+
+#define NR_MSM_IRQS                            256
+#define NR_GPIO_IRQS                           173
+#define NR_BOARD_IRQS                          0
+
+#define NR_IRQS                                (NR_MSM_IRQS + NR_GPIO_IRQS + \
+                                               NR_BOARD_IRQS)
+
+#define BLSP_QUP_IRQ(blsp_id, qup_id)          ((blsp_id == 1) ? \
+                                               ((GIC_SPI_START + 95) + qup_id):\
+                                               ((GIC_SPI_START + 101) + qup_id))
+
+#define SDCC1_PWRCTL_IRQ                       (GIC_SPI_START + 138)
+#define SDCC2_PWRCTL_IRQ                       (GIC_SPI_START + 221)
+#endif	/* __IRQS_FSM9900_H */
diff --git a/platform/fsm9900/platform.c b/platform/fsm9900/platform.c
new file mode 100644
index 0000000..7a1791e
--- /dev/null
+++ b/platform/fsm9900/platform.c
@@ -0,0 +1,171 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+#include <boot_stats.h>
+
+#define MB (1024*1024)
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY         (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+                           MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY      (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+                           MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* IMEM memory - cacheable, write through */
+#define IMEM_MEMORY       (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+                           MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/*   Physical addr,    Virtual addr,     Size (in MB),   Flags */
+	{MEMBASE,          MEMBASE,          (MEMSIZE / MB), LK_MEMORY},
+	{MSM_IOMAP_BASE,   MSM_IOMAP_BASE,   MSM_IOMAP_SIZE, IOMAP_MEMORY},
+	/* IMEM  needs a seperate entry in the table as it's length is only 0x8000. */
+	{SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1,              IMEM_MEMORY},
+};
+
+static struct smem_ram_ptable ram_ptable;
+
+/* Boot timestamps */
+#define BS_INFO_OFFSET     (0x6B0)
+#define BS_INFO_ADDR_V1    (RPM_MSG_RAM_BASE     + BS_INFO_OFFSET)
+#define BS_INFO_ADDR_V2    (MSM_SHARED_IMEM_BASE + BS_INFO_OFFSET)
+
+void platform_early_init(void)
+{
+	board_init();
+	platform_clock_init();
+	qgic_init();
+	qtimer_init();
+}
+
+void platform_init(void)
+{
+	dprintf(INFO, "platform_init()\n");
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+	return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
+
+addr_t get_bs_info_addr()
+{
+	uint32_t soc_ver = board_soc_version();
+
+	if (soc_ver < BOARD_SOC_VERSION2)
+		return ((addr_t)BS_INFO_ADDR_V1);
+	else
+		return ((addr_t)BS_INFO_ADDR_V2);
+
+}
+
+void platform_uninit(void)
+{
+	qtimer_uninit();
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+	/* Use only the mappings specified in this file. */
+	return 0;
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+	/* Return same address as we are using 1-1 mapping. */
+	return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+	/* Return same address as we are using 1-1 mapping. */
+	return phys_addr;
+}
+
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+	uint32_t i;
+	uint32_t sections;
+	uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+
+	ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+	/* Configure the MMU page entries for SDRAM and IMEM memory read
+	   from the smem ram table*/
+	for(i = 0; i < ram_ptable.len; i++)
+	{
+		if(ram_ptable.parts[i].type == SYS_MEMORY)
+		{
+			if((ram_ptable.parts[i].category == SDRAM) ||
+			   (ram_ptable.parts[i].category == IMEM))
+			{
+				/* Check to ensure that start address is 1MB aligned */
+				ASSERT((ram_ptable.parts[i].start & 0xFFFFF) == 0);
+
+				sections = (ram_ptable.parts[i].size) / MB;
+				while(sections--) {
+					arm_mmu_map_section(ram_ptable.parts[i].start +
+								sections * MB,
+								ram_ptable.parts[i].start +
+								sections * MB,
+								(MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+								MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
+				}
+			}
+		}
+	}
+	/* Configure the MMU page entries for memory read from the
+	   mmu_section_table */
+	for (i = 0; i < table_size; i++) {
+		sections = mmu_section_table[i].num_of_sections;
+
+		while (sections--) {
+			arm_mmu_map_section(mmu_section_table[i].paddress +
+					    sections * MB,
+					    mmu_section_table[i].vaddress +
+					    sections * MB,
+					    mmu_section_table[i].flags);
+		}
+	}
+}
diff --git a/platform/fsm9900/rules.mk b/platform/fsm9900/rules.mk
new file mode 100644
index 0000000..e115234
--- /dev/null
+++ b/platform/fsm9900/rules.mk
@@ -0,0 +1,28 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH    := arm
+ARM_CPU := cortex-a8
+CPU     := generic
+
+DEFINES += ARM_CPU_CORE_KRAIT
+
+MMC_SLOT         := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+	   MMC_SLOT=$(MMC_SLOT) SSD_ENABLE
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+DEVS += fbcon
+MODULES += dev/fbcon
+
+OBJS += \
+	$(LOCAL_DIR)/platform.o \
+	$(LOCAL_DIR)/acpuclock.o \
+	$(LOCAL_DIR)/fsm9900-clock.o \
+	$(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/msm8974/acpuclock.c b/platform/msm8974/acpuclock.c
index 6131e61..1699824 100644
--- a/platform/msm8974/acpuclock.c
+++ b/platform/msm8974/acpuclock.c
@@ -142,14 +142,14 @@
 	}
 	else
 	{
-		dprintf(CRITICAL, "sdc frequency (%d) is not supported\n", freq);
+		dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
 		ASSERT(0);
 	}
 
 
 	if(ret)
 	{
-		dprintf(CRITICAL, "failed to set sdc1_core_clk ret = %d\n", ret);
+		dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
 		ASSERT(0);
 	}
 
diff --git a/platform/msm8974/include/platform/clock.h b/platform/msm8974/include/platform/clock.h
index e9f8d08..c96763a 100644
--- a/platform/msm8974/include/platform/clock.h
+++ b/platform/msm8974/include/platform/clock.h
@@ -81,6 +81,16 @@
 #define DSI_PIXEL1_CFG_RCGR             REG_MM(0x2024)
 #define DSI_PIXEL1_CBCR                 REG_MM(0x2318)
 
+#define MDSS_EDPPIXEL_CBCR              REG_MM(0x232C)
+#define MDSS_EDPLINK_CBCR               REG_MM(0x2330)
+#define EDPPIXEL_M                      REG_MM(0x20A8)
+#define EDPPIXEL_N                      REG_MM(0x20AC)
+#define EDPPIXEL_D                      REG_MM(0x20B0)
+#define EDPPIXEL_CFG_RCGR               REG_MM(0x20A4)
+#define EDPPIXEL_CMD_RCGR               REG_MM(0x20A0)
+#define EDPLINK_CFG_RCGR                REG_MM(0x20C4)
+#define EDPLINK_CMD_RCGR                REG_MM(0x20C0)
+
 void platform_clock_init(void);
 
 void clock_init_mmc(uint32_t interface);
@@ -90,6 +100,7 @@
 void clock_config_ce(uint8_t instance);
 void mdp_clock_init(void);
 void mdp_gdsc_ctrl(uint8_t enable);
+void edp_clk_enable(void);
 void clock_ce_enable(uint8_t instance);
 void clock_ce_disable(uint8_t instance);
 
diff --git a/platform/msm8974/include/platform/iomap.h b/platform/msm8974/include/platform/iomap.h
index 3e27c3b..b3edca9 100644
--- a/platform/msm8974/include/platform/iomap.h
+++ b/platform/msm8974/include/platform/iomap.h
@@ -182,6 +182,8 @@
 #define MIPI_DSI1_BASE              (0xFD922E00)
 #define REG_DSI(off)                (MIPI_DSI_BASE + 0x04 + (off))
 
+#define EDP_BASE                    (0xFD923400)
+
 #define MDP_BASE                    (0xfd900000)
 #define REG_MDP(off)                (MDP_BASE + (off))
 
diff --git a/platform/msm8974/msm8974-clock.c b/platform/msm8974/msm8974-clock.c
index dbba8c4..991fe17 100644
--- a/platform/msm8974/msm8974-clock.c
+++ b/platform/msm8974/msm8974-clock.c
@@ -44,6 +44,8 @@
 #define mmpll1_mm_source_val 2
 #define mmpll3_mm_source_val 3
 #define gpll0_mm_source_val 5
+#define edppll_270_mm_source_val 4
+#define edppll_350_mm_source_val 4
 
 struct clk_freq_tbl rcg_dummy_freq = F_END;
 
@@ -624,6 +626,60 @@
 	},
 };
 
+static struct clk_freq_tbl ftbl_mdss_edplink_clk[] = {
+	F_MDSS(162000000, edppll_270,   2,   0,   0),
+	F_MDSS(270000000, edppll_270,  11,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edplink_clk_src = {
+	.cmd_reg = (uint32_t *)EDPLINK_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl = ftbl_mdss_edplink_clk,
+	.current_freq = &rcg_dummy_freq,
+	.c = {
+		.dbg_name = "edplink_clk_src",
+		.ops = &clk_ops_rcg,
+	},
+};
+
+static struct clk_freq_tbl ftbl_mdss_edppixel_clk[] = {
+	F_MDSS(138500000, edppll_350,   2,   0,   0),
+	F_MDSS(350000000, edppll_350,  11,   0,   0),
+	F_END
+};
+
+static struct rcg_clk edppixel_clk_src = {
+	.cmd_reg = (uint32_t *)EDPPIXEL_CMD_RCGR,
+	.set_rate = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl = ftbl_mdss_edppixel_clk,
+	.current_freq = &rcg_dummy_freq,
+	.c = {
+		.dbg_name = "edppixel_clk_src",
+		.ops = &clk_ops_rcg_mnd,
+	},
+};
+
+static struct branch_clk mdss_edplink_clk = {
+	.cbcr_reg = (uint32_t *)MDSS_EDPLINK_CBCR,
+	.has_sibling = 0,
+	.parent = &edplink_clk_src.c,
+	.c = {
+		.dbg_name = "mdss_edplink_clk",
+		.ops = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk mdss_edppixel_clk = {
+	.cbcr_reg = (uint32_t *)MDSS_EDPPIXEL_CBCR,
+	.has_sibling = 0,
+	.parent = &edppixel_clk_src.c,
+	.c = {
+		.dbg_name = "mdss_edppixel_clk",
+		.ops = &clk_ops_branch,
+	},
+};
+
 /* Clock lookup table */
 static struct clk_lookup msm_clocks_8974[] =
 {
@@ -663,6 +719,9 @@
 	CLK_LOOKUP("mdss_mdp_clk_src",     mdss_mdp_clk_src.c),
 	CLK_LOOKUP("mdss_mdp_clk",         mdss_mdp_clk.c),
 	CLK_LOOKUP("mdss_mdp_lut_clk",     mdss_mdp_lut_clk.c),
+
+	CLK_LOOKUP("edp_pixel_clk",        mdss_edppixel_clk.c),
+	CLK_LOOKUP("edp_link_clk",         mdss_edplink_clk.c),
 };
 
 
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index ee0582d..4e1d44f 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -52,6 +52,75 @@
  */
 extern int check_aboot_addr_range_overlap(uint32_t start, uint32_t size);
 
+struct msm_id
+{
+	uint32_t platform_id;
+	uint32_t hardware_id;
+	uint32_t soc_rev;
+};
+
+/* Returns soc version if platform id and hardware id matches
+   otherwise return 0xFFFFFFFF */
+#define INVALID_SOC_REV_ID 0XFFFFFFFF
+static uint32_t dev_tree_compatible(void *dtb)
+{
+	int root_offset;
+	const void *prop;
+	char model[128];
+	struct msm_id msm_id;
+	int len;
+
+	root_offset = fdt_path_offset(dtb, "/");
+	if (root_offset < 0)
+		return false;
+
+	prop = fdt_getprop(dtb, root_offset, "model", &len);
+	if (prop && len > 0) {
+		memcpy(model, prop, MIN((int)sizeof(model), len));
+		model[sizeof(model) - 1] = '\0';
+	} else {
+		model[0] = '\0';
+	}
+
+	prop = fdt_getprop(dtb, root_offset, "qcom,msm-id", &len);
+	if (!prop || len <= 0) {
+		dprintf(INFO, "qcom,msm-id entry not found\n");
+		return false;
+	} else if (len < (int)sizeof(struct msm_id)) {
+		dprintf(INFO, "qcom,msm-id entry size mismatch (%d != %d)\n",
+			len, sizeof(struct msm_id));
+		return false;
+	}
+	msm_id.platform_id = fdt32_to_cpu(((const struct msm_id *)prop)->platform_id);
+	msm_id.hardware_id = fdt32_to_cpu(((const struct msm_id *)prop)->hardware_id);
+	msm_id.soc_rev = fdt32_to_cpu(((const struct msm_id *)prop)->soc_rev);
+
+	dprintf(INFO, "Found an appended flattened device tree (%s - %d %d 0x%x)\n",
+		*model ? model : "unknown",
+		msm_id.platform_id, msm_id.hardware_id, msm_id.soc_rev);
+
+	if (msm_id.platform_id != board_platform_id() ||
+		msm_id.hardware_id != board_hardware_id()) {
+		dprintf(INFO, "Device tree's msm_id doesn't match the board: <%d %d 0x%x> != <%d %d 0x%x>\n",
+			msm_id.platform_id,
+			msm_id.hardware_id,
+			msm_id.soc_rev,
+			board_platform_id(),
+			board_hardware_id(),
+			board_soc_version());
+		return INVALID_SOC_REV_ID;
+	}
+
+	dprintf(INFO, "Device tree's msm_id matches the board: <%d %d 0x%x> == <%d %d 0x%x>\n",
+		msm_id.platform_id,
+		msm_id.hardware_id,
+		msm_id.soc_rev,
+		board_platform_id(),
+		board_hardware_id(),
+		board_soc_version());
+	return msm_id.soc_rev;
+}
+
 /*
  * Will relocate the DTB to the tags addr if the device tree is found and return
  * its address
@@ -63,46 +132,66 @@
  * Return Value: DTB address : If appended device tree is found
  *               'NULL'         : Otherwise
  */
-void *dev_tree_appended(void *kernel, void *tags, uint32_t kernel_size)
+void *dev_tree_appended(void *kernel, uint32_t kernel_size, void *tags)
 {
+	void *kernel_end = kernel + kernel_size;
 	uint32_t app_dtb_offset = 0;
-	uint32_t size;
+	void *dtb;
+	void *bestmatch_tag = NULL;
+	uint32_t bestmatch_tag_size;
+	uint32_t bestmatch_soc_rev_id = INVALID_SOC_REV_ID;
 
 	memcpy((void*) &app_dtb_offset, (void*) (kernel + DTB_OFFSET), sizeof(uint32_t));
 
-	/*
-	 * Check if we have valid offset for the DTB, if not return error.
-	 * If the kernel image does not have appeneded device tree, DTB offset
-	 * might contain some random address which is not accessible & cause
-	 * data abort. If kernel start + dtb offset address exceed the total
-	 * size of the kernel, then we dont have an appeneded DTB.
-	 */
-	if (app_dtb_offset < kernel_size)
-	{
-		if (!fdt_check_header((void*) (kernel + app_dtb_offset)))
-		{
-			void *dtb;
-			int rc;
+	dtb = kernel + app_dtb_offset;
+	while (dtb + sizeof(struct fdt_header) < kernel_end) {
+		uint32_t dtb_soc_rev_id;
+		struct fdt_header dtb_hdr;
+		uint32_t dtb_size;
 
-			dprintf(INFO, "Found Appeneded Flattened Device tree\n");
-			dtb = kernel + app_dtb_offset;
-			size = fdt_totalsize(dtb);
-			if (check_aboot_addr_range_overlap(tags, size))
-			{
-				dprintf(CRITICAL, "Appended dtb aboot overlap check failed.\n");
-				return NULL;
-			}
-			rc = fdt_open_into(dtb, tags, size);
-			if (rc == 0)
-			{
-				/* clear out the old DTB magic so kernel doesn't find it */
-				*((uint32_t *)dtb) = 0;
-				return tags;
+		/* the DTB could be unaligned, so extract the header,
+		 * and operate on it separately */
+		memcpy(&dtb_hdr, dtb, sizeof(struct fdt_header));
+		if (fdt_check_header((const void *)&dtb_hdr) != 0 ||
+		    (dtb + fdt_totalsize((const void *)&dtb_hdr) > kernel_end))
+			break;
+		dtb_size = fdt_totalsize(&dtb_hdr);
+
+		/* now that we know we have a valid DTB, we need to copy
+		 * it somewhere aligned, like tags */
+		memcpy(tags, dtb, dtb_size);
+
+		dtb_soc_rev_id = dev_tree_compatible(tags);
+		if (dtb_soc_rev_id == board_soc_version()) {
+			/* clear out the old DTB magic so kernel doesn't find it */
+			*((uint32_t *)(kernel + app_dtb_offset)) = 0;
+			return tags;
+		} else if ((dtb_soc_rev_id != INVALID_SOC_REV_ID) &&
+				   (dtb_soc_rev_id < board_soc_version())) {
+			/* if current bestmatch is less than new dtb_soc_rev_id then update
+			   bestmatch_tag */
+			if((bestmatch_soc_rev_id == INVALID_SOC_REV_ID) ||
+			   (bestmatch_soc_rev_id < dtb_soc_rev_id)) {
+				bestmatch_tag = dtb;
+				bestmatch_tag_size = dtb_size;
+				bestmatch_soc_rev_id = dtb_soc_rev_id;
 			}
 		}
+
+		/* goto the next device tree if any */
+		dtb += dtb_size;
 	}
-	else
-		dprintf(CRITICAL, "DTB offset is incorrect, kernel image does not have appended DTB\n");
+
+	if(bestmatch_tag) {
+		dprintf(INFO,"DTB found with bestmatch soc rev id 0x%x.Board soc rev id 0x%x\n",
+				bestmatch_soc_rev_id, board_soc_version());
+		memcpy(tags, bestmatch_tag, bestmatch_tag_size);
+		/* clear out the old DTB magic so kernel doesn't find it */
+		*((uint32_t *)(kernel + app_dtb_offset)) = 0;
+		return tags;
+	}
+
+	dprintf(CRITICAL, "DTB offset is incorrect, kernel image does not have appended DTB\n");
 
 	return NULL;
 }
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
old mode 100755
new mode 100644
index 9254a78..3768ca8
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -112,8 +112,8 @@
 		break;
 	case MIPI_CMD_PANEL:
 		dprintf(INFO, "Config MIPI_CMD_PANEL.\n");
-
-		if (mdp_get_revision() == MDP_REV_50)
+		mdp_rev = mdp_get_revision();
+		if (mdp_rev == MDP_REV_50 || mdp_rev == MDP_REV_304)
 			ret = mdss_dsi_config(panel);
 		else
 			ret = mipi_config(panel);
@@ -150,6 +150,7 @@
 int msm_display_on()
 {
 	int ret = NO_ERROR;
+	int mdp_rev;
 	struct msm_panel_info *pinfo;
 
 	if (!panel)
@@ -183,7 +184,8 @@
 		ret = mdp_dma_on();
 		if (ret)
 			goto msm_display_on_out;
-		if (mdp_get_revision() != MDP_REV_50) {
+		mdp_rev = mdp_get_revision();
+		if (mdp_rev != MDP_REV_50 && mdp_rev != MDP_REV_304) {
 			ret = mipi_cmd_trigger();
 			if (ret)
 				goto msm_display_on_out;
diff --git a/platform/msm_shared/edp.c b/platform/msm_shared/edp.c
new file mode 100644
index 0000000..d170f19
--- /dev/null
+++ b/platform/msm_shared/edp.c
@@ -0,0 +1,163 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "edp.h"
+#include "mdp5.h"
+
+#define RGB_COMPONENTS		3
+#define MAX_NUMBER_EDP_LANES	4
+
+static void edp_config_sync(void)
+{
+	int ret = 0;
+
+	ret = edp_read(EDP_BASE + 0xc); /* EDP_CONFIGURATION_CTRL */
+	ret &= ~0x733;
+	ret |= (0x55 & 0x733);
+	edp_write(EDP_BASE + 0xc, ret);
+	edp_write(EDP_BASE + 0xc, 0x55); /* EDP_CONFIGURATION_CTRL */
+}
+
+static void edp_config_sw_div(void)
+{
+	edp_write(EDP_BASE + 0x14, 0x13b); /* EDP_SOFTWARE_MVID */
+	edp_write(EDP_BASE + 0x18, 0x266); /* EDP_SOFTWARE_NVID */
+}
+
+static void edp_config_static_mdiv(void)
+{
+	int ret = 0;
+
+	ret = edp_read(EDP_BASE + 0xc); /* EDP_CONFIGURATION_CTRL */
+	edp_write(EDP_BASE + 0xc, ret | 0x2); /* EDP_CONFIGURATION_CTRL */
+	edp_write(EDP_BASE + 0xc, 0x57); /* EDP_CONFIGURATION_CTRL */
+}
+
+static void edp_config_timing(void)
+{
+	edp_write(EDP_BASE + 0x98, 0);
+	edp_write(EDP_BASE + 0x9C, 0x8200020); /* EDP_HSYNC_CTL */
+	edp_write(EDP_BASE + 0x100, 0x233AC0); /* EDP_VSYNC_PERIOD_F0 */
+	edp_write(EDP_BASE + 0x104, 0x0);
+	edp_write(EDP_BASE + 0x10C, 0x0);
+	edp_write(EDP_BASE + 0x130, 0x7ef0070); /* EDP_DISPLAY_HCTL */
+	edp_write(EDP_BASE + 0x134, 0x0); /* EDP_ACTIVE_HCTL */
+	edp_write(EDP_BASE + 0x110, 0xB330); /* EDP_DISPLAY_V_START_F0 */
+	edp_write(EDP_BASE + 0x118, 0x22f98f); /* EDP_DISPLAY_V_END_F0 */
+	edp_write(EDP_BASE + 0x114, 0x0);
+	edp_write(EDP_BASE + 0x11C, 0x0);
+	edp_write(EDP_BASE + 0x120, 0x0); /* EDP_ACTIVE_V_START_F0 */
+	edp_write(EDP_BASE + 0x128, 0x0); /* EDP_ACTIVE_V_END_F0 */
+	edp_write(EDP_BASE + 0x124, 0x0);
+	edp_write(EDP_BASE + 0x12C, 0x0);
+}
+
+static void edp_enable(int enable)
+{
+	edp_write(EDP_BASE + 0x8, 0x0); /* EDP_STATE_CTRL */
+	edp_write(EDP_BASE + 0x8, 0x40); /* EDP_STATE_CTRL */
+	edp_write(EDP_BASE + 0x94, enable); /* EDP_TIMING_ENGINE_EN */
+	edp_write(EDP_BASE + 0x4, enable); /* EDP_MAINLINK_CTRL */
+}
+
+/*
+ * Converts from EDID struct to msm_panel_info
+ */
+void edp_edid2pinfo(struct edp_panel_data *edp_panel)
+{
+	struct display_timing_desc *dp;
+	struct msm_panel_info *pinfo;
+
+	dp = &edp_panel->edid.timing[0];
+	pinfo = &edp_panel->panel_data->panel_info;
+
+	pinfo->clk_rate = dp->pclk;
+
+	pinfo->xres = dp->h_addressable + dp->h_border * 2;
+	pinfo->yres = dp->v_addressable + dp->v_border * 2;
+
+	pinfo->lcdc.h_back_porch = dp->h_blank - dp->h_fporch \
+		- dp->h_sync_pulse;
+	pinfo->lcdc.h_front_porch = dp->h_fporch;
+	pinfo->lcdc.h_pulse_width = dp->h_sync_pulse;
+
+	pinfo->lcdc.v_back_porch = dp->v_blank - dp->v_fporch \
+		- dp->v_sync_pulse;
+	pinfo->lcdc.v_front_porch = dp->v_fporch;
+	pinfo->lcdc.v_pulse_width = dp->v_sync_pulse;
+
+	pinfo->type = EDP_PANEL;
+	pinfo->wait_cycle = 0;
+	pinfo->bpp = 24;
+
+	pinfo->lcdc.border_clr = 0;	 /* black */
+	pinfo->lcdc.underflow_clr = 0xff; /* blue */
+	pinfo->lcdc.hsync_skew = 0;
+}
+
+int edp_on(void)
+{
+	int i;
+
+	edp_phy_sw_reset();
+	edp_pll_configure();
+	edp_config_clk();
+	edp_phy_misc_cfg();
+	edp_config_sync();
+	edp_config_sw_div();
+	edp_config_static_mdiv();
+	edp_config_timing();
+
+	edp_hw_powerup(1);
+
+	for (i = 0; i < MAX_NUMBER_EDP_LANES; ++i)
+		edp_enable_lane_bist(i, 1);
+
+	edp_enable_mainlink(1);
+	edp_enable(1);
+
+	return 0;
+}
+
+int edp_off(void)
+{
+	int i;
+
+	mdp_edp_off();
+	edp_enable(0);
+	edp_unconfig_clk();
+	edp_enable_mainlink(0);
+
+	for (i = 0; i < MAX_NUMBER_EDP_LANES; ++i)
+		edp_enable_lane_bist(i, 0);
+
+	edp_hw_powerup(0);
+
+	return 0;
+}
diff --git a/platform/msm_shared/edp_phy.c b/platform/msm_shared/edp_phy.c
new file mode 100644
index 0000000..32ca68e
--- /dev/null
+++ b/platform/msm_shared/edp_phy.c
@@ -0,0 +1,197 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include "edp.h"
+#include <platform/timer.h>
+
+/* EDP phy configuration settings */
+void edp_phy_sw_reset(void)
+{
+	/* phy sw reset */
+	edp_write(EDP_BASE + 0x74, 0x100); /* EDP_PHY_CTRL */
+	dmb();
+	udelay(1);
+	edp_write(EDP_BASE + 0x74, 0x000); /* EDP_PHY_CTRL */
+	dmb();
+	udelay(1);
+
+	/* phy PLL sw reset */
+	edp_write(EDP_BASE + 0x74, 0x001); /* EDP_PHY_CTRL */
+	dmb();
+	udelay(1);
+	edp_write(EDP_BASE + 0x74, 0x000); /* EDP_PHY_CTRL */
+	dmb();
+	udelay(1);
+}
+
+void edp_hw_powerup(int enable)
+{
+	int ret = 0;
+
+	if (enable) {
+		/* EDP_PHY_EDPPHY_GLB_PD_CTL */
+		edp_write(EDP_BASE + 0x52c, 0x3f);
+		/* EDP_PHY_EDPPHY_GLB_CFG */
+		edp_write(EDP_BASE + 0x528, 0x1);
+		/* EDP_PHY_PLL_UNIPHY_PLL_GLB_CFG */
+		edp_write(EDP_BASE + 0x620, 0xf);
+		/* EDP_AUX_CTRL */
+		ret = edp_read(EDP_BASE + 0x300);
+		edp_write(EDP_BASE + 0x300, ret | 0x1);
+	} else {
+		/* EDP_PHY_EDPPHY_GLB_PD_CTL */
+		edp_write(EDP_BASE + 0x52c, 0xc0);
+	}
+}
+
+void edp_pll_configure(void)
+{
+	edp_write(EDP_BASE + 0x664, 0x5); /* UNIPHY_PLL_LKDET_CFG2 */
+	edp_write(EDP_BASE + 0x600, 0x1); /* UNIPHY_PLL_REFCLK_CFG */
+	edp_write(EDP_BASE + 0x638, 0x36); /* UNIPHY_PLL_SDM_CFG0 */
+	edp_write(EDP_BASE + 0x63c, 0x62); /* UNIPHY_PLL_SDM_CFG1 */
+	edp_write(EDP_BASE + 0x640, 0x0); /* UNIPHY_PLL_SDM_CFG2 */
+	edp_write(EDP_BASE + 0x644, 0x28); /* UNIPHY_PLL_SDM_CFG3 */
+	edp_write(EDP_BASE + 0x648, 0x0); /* UNIPHY_PLL_SDM_CFG4 */
+	edp_write(EDP_BASE + 0x64c, 0x80); /* UNIPHY_PLL_SSC_CFG0 */
+	edp_write(EDP_BASE + 0x650, 0x0); /* UNIPHY_PLL_SSC_CFG1 */
+	edp_write(EDP_BASE + 0x654, 0x0); /* UNIPHY_PLL_SSC_CFG2 */
+	edp_write(EDP_BASE + 0x658, 0x0); /* UNIPHY_PLL_SSC_CFG3 */
+	edp_write(EDP_BASE + 0x66c, 0xa); /* UNIPHY_PLL_CAL_CFG0 */
+	edp_write(EDP_BASE + 0x674, 0x1); /* UNIPHY_PLL_CAL_CFG2 */
+	edp_write(EDP_BASE + 0x684, 0x5a); /* UNIPHY_PLL_CAL_CFG6 */
+	edp_write(EDP_BASE + 0x688, 0x0); /* UNIPHY_PLL_CAL_CFG7 */
+	edp_write(EDP_BASE + 0x68c, 0x60); /* UNIPHY_PLL_CAL_CFG8 */
+	edp_write(EDP_BASE + 0x690, 0x0); /* UNIPHY_PLL_CAL_CFG9 */
+	edp_write(EDP_BASE + 0x694, 0x46); /* UNIPHY_PLL_CAL_CFG10 */
+	edp_write(EDP_BASE + 0x698, 0x5); /* UNIPHY_PLL_CAL_CFG11 */
+	edp_write(EDP_BASE + 0x65c, 0x10); /* UNIPHY_PLL_LKDET_CFG0 */
+	edp_write(EDP_BASE + 0x660, 0x1a); /* UNIPHY_PLL_LKDET_CFG1 */
+	edp_write(EDP_BASE + 0x604, 0x0); /* UNIPHY_PLL_POSTDIV1_CFG */
+	edp_write(EDP_BASE + 0x624, 0x0); /* UNIPHY_PLL_POSTDIV2_CFG */
+	edp_write(EDP_BASE + 0x628, 0x0); /* UNIPHY_PLL_POSTDIV3_CFG */
+
+	edp_write(EDP_BASE + 0x620, 0x1); /* UNIPHY_PLL_GLB_CFG */
+	edp_write(EDP_BASE + 0x620, 0x5); /* UNIPHY_PLL_GLB_CFG */
+	edp_write(EDP_BASE + 0x620, 0x7); /* UNIPHY_PLL_GLB_CFG */
+	edp_write(EDP_BASE + 0x620, 0xf); /* UNIPHY_PLL_GLB_CFG */
+}
+
+void edp_enable_mainlink(int enable)
+{
+	uint32_t data;
+
+	data = edp_read(EDP_BASE + 0x004);
+	data &= ~BIT(0);
+
+	if (enable) {
+		data |= 0x1;
+		edp_write(EDP_BASE + 0x004, data);
+		edp_write(EDP_BASE + 0x004, 0x1);
+	} else {
+		data |= 0x0;
+		edp_write(EDP_BASE + 0x004, data);
+	}
+}
+
+void edp_enable_lane_bist(int lane, int enable)
+{
+	unsigned char *addr_ln_bist_cfg, *addr_ln_pd_ctrl;
+
+	/* EDP_PHY_EDPPHY_LNn_PD_CTL */
+	addr_ln_pd_ctrl = (unsigned char *)(EDP_BASE + 0x404 + (0x40 * lane));
+	/* EDP_PHY_EDPPHY_LNn_BIST_CFG0 */
+	addr_ln_bist_cfg = (unsigned char *)(EDP_BASE + 0x408 + (0x40 * lane));
+
+	if (enable) {
+		edp_write(addr_ln_pd_ctrl, 0x0);
+		edp_write(addr_ln_bist_cfg, 0x10);
+
+	} else {
+		edp_write(addr_ln_pd_ctrl, 0xf);
+		edp_write(addr_ln_bist_cfg, 0x10);
+	}
+}
+
+void edp_enable_pixel_clk(int enable)
+{
+	if (!enable) {
+		edp_write(MDSS_EDPPIXEL_CBCR, 0); /* CBCR */
+		return;
+	}
+
+	edp_write(EDP_BASE + 0x624, 0x1); /* PostDiv2 */
+
+	/* Configuring MND for Pixel */
+	edp_write(EDPPIXEL_M, 0x3f); /* M value */
+	edp_write(EDPPIXEL_N, 0xb); /* N value */
+	edp_write(EDPPIXEL_D, 0x0); /* D value */
+
+	/* CFG RCGR */
+	edp_write(EDPPIXEL_CFG_RCGR, (5 << 8) | (2 << 12));
+	edp_write(EDPPIXEL_CMD_RCGR, 3); /* CMD RCGR */
+
+	edp_write(MDSS_EDPPIXEL_CBCR, 1); /* CBCR */
+}
+
+void edp_enable_link_clk(int enable)
+{
+	if (!enable) {
+		edp_write(MDSS_EDPLINK_CBCR, 0); /* CBCR */
+		return;
+	}
+
+	edp_write(EDPLINK_CFG_RCGR, (4 << 8)); /* CFG RCGR */
+	edp_write(EDPLINK_CMD_RCGR, 3); /* CMD RCGR */
+
+	edp_write(MDSS_EDPLINK_CBCR, 1); /* CBCR */
+}
+
+void edp_config_clk(void)
+{
+	edp_enable_link_clk(1);
+	edp_enable_pixel_clk(1);
+}
+
+void edp_unconfig_clk(void)
+{
+	edp_enable_link_clk(0);
+	edp_enable_pixel_clk(0);
+}
+
+void edp_phy_misc_cfg(void)
+{
+	/* EDP_PHY_EDPPHY_GLB_VM_CFG0 */
+	edp_write(EDP_BASE + 0x510, 0x3);
+	/* EDP_PHY_EDPPHY_GLB_VM_CFG1 */
+	edp_write(EDP_BASE + 0x514, 0x64);
+	/* EDP_PHY_EDPPHY_GLB_MISC9 */
+	edp_write(EDP_BASE + 0x518, 0x6c);
+	/* EDP_MISC1_MISC0 */
+	edp_write(EDP_BASE + 0x2c, 0x1);
+}
diff --git a/platform/msm_shared/include/clock_lib2.h b/platform/msm_shared/include/clock_lib2.h
index a7606bc..008d5fa 100644
--- a/platform/msm_shared/include/clock_lib2.h
+++ b/platform/msm_shared/include/clock_lib2.h
@@ -70,6 +70,16 @@
 			| BVAL(10, 8, s##_mm_source_val), \
 	}
 
+#define F_MDSS(f, s, div, m, n) \
+	{ \
+		.freq_hz = (f), \
+		.m_val = (m), \
+		.n_val = ~((n)-(m)) * !!(n), \
+		.d_val = ~(n),\
+		.div_src_val = BVAL(4, 0, (int)(2*(div) - 1)) \
+			| BVAL(10, 8, s##_mm_source_val), \
+	}
+
 /* Branch Clock Bits */
 #define CBCR_BRANCH_ENABLE_BIT  BIT(0)
 #define CBCR_BRANCH_OFF_BIT     BIT(31)
diff --git a/platform/msm_shared/include/dev_tree.h b/platform/msm_shared/include/dev_tree.h
index d0b0ca8..2a8ee01 100644
--- a/platform/msm_shared/include/dev_tree.h
+++ b/platform/msm_shared/include/dev_tree.h
@@ -70,5 +70,5 @@
 int dev_tree_get_entry_info(struct dt_table *table, struct dt_entry *dt_entry_info);
 int update_device_tree(void *, const char *, void *, unsigned);
 int dev_tree_add_mem_info(void *fdt, uint32_t offset, uint32_t size, uint32_t addr);
-void *dev_tree_appended(void *kernel, void *tags, uint32_t kernel_size);
+void *dev_tree_appended(void *kernel, uint32_t kernel_size, void *tags);
 #endif
diff --git a/platform/msm_shared/include/edp.h b/platform/msm_shared/include/edp.h
new file mode 100644
index 0000000..04a3e49
--- /dev/null
+++ b/platform/msm_shared/include/edp.h
@@ -0,0 +1,55 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of The Linux Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#ifndef EDP_H
+#define EDP_H
+
+#include "msm_panel.h"
+#include <reg.h>
+#include <debug.h>
+#include <err.h>
+#include <platform/iomap.h>
+#include <platform/clock.h>
+
+#define edp_read(offset) readl_relaxed((offset))
+#define edp_write(offset, data) writel_relaxed((data), (offset))
+
+void edp_phy_sw_reset(void);
+void edp_pll_configure(void);
+void edp_enable_lane_bist(int lane, int enable);
+void edp_enable_mainlink(int enable);
+void edp_hw_powerup(int enable);
+void edp_config_clk(void);
+void edp_unconfig_clk(void);
+void edp_phy_misc_cfg(void);
+void edp_edid2pinfo(struct edp_panel_data *edp_panel);
+int edp_on(void);
+int edp_off(void);
+int edp_config(void *pdata);
+
+#endif /* EDP_H */
diff --git a/platform/msm_shared/include/mdp3.h b/platform/msm_shared/include/mdp3.h
index 813b4ba..8dff686 100644
--- a/platform/msm_shared/include/mdp3.h
+++ b/platform/msm_shared/include/mdp3.h
@@ -28,6 +28,8 @@
  */
 
 #include <dev/fbcon.h>
+#include <msm_panel.h>
+
 //TODO: Make a global PASS / FAIL define
 #define PASS                        0
 #define FAIL                        1
@@ -51,3 +53,8 @@
 void mdp_shutdown(void);
 void mdp_set_revision(int rev);
 int mdp_get_revision();
+
+/* defining no-op functions that are implemented only for mdp5 */
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_edp_on(void);
+int mdp_edp_off(void);
diff --git a/platform/msm_shared/include/mdp4.h b/platform/msm_shared/include/mdp4.h
index e0fc2c7..c988dee 100644
--- a/platform/msm_shared/include/mdp4.h
+++ b/platform/msm_shared/include/mdp4.h
@@ -111,4 +111,10 @@
 int mdp_lcdc_off();
 void mdp_set_revision(int rev);
 int mdp_get_revision();
+
+/* defining no-op functions that are implemented only for mdp5 */
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_edp_on(void);
+int mdp_edp_off(void);
+
 #endif
diff --git a/platform/msm_shared/include/mdp5.h b/platform/msm_shared/include/mdp5.h
index 994d54e..75e4e0d 100644
--- a/platform/msm_shared/include/mdp5.h
+++ b/platform/msm_shared/include/mdp5.h
@@ -76,6 +76,7 @@
 #define MDP_UPPER_NEW_ROI_PRIOR_RO_START        REG_MDP(0x02EC)
 #define MDP_LOWER_NEW_ROI_PRIOR_TO_START        REG_MDP(0x04F8)
 
+#define MDP_INTF_0_TIMING_ENGINE_EN             REG_MDP(0x12500)
 #define MDP_INTF_1_TIMING_ENGINE_EN             REG_MDP(0x12700)
 
 #define MDP_CTL_0_BASE                          REG_MDP(0x600)
@@ -91,6 +92,7 @@
 #define MDP_REG_SPLIT_DISPLAY_EN                REG_MDP(0x3F4)
 #define MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL    REG_MDP(0x3F8)
 
+#define MDP_INTF_0_BASE                         REG_MDP(0x12500)
 #define MDP_INTF_1_BASE                         REG_MDP(0x12700)
 #define MDP_INTF_2_BASE                         REG_MDP(0x12900)
 
@@ -156,6 +158,9 @@
 			unsigned short num_of_lanes);
 int mdp_dsi_video_on(void);
 int mdp_dma_on(void);
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb);
+int mdp_edp_on(void);
+int mdp_edp_off(void);
 void mdp_disable(void);
 
 #endif
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index 22a47ad..42f2b47 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -49,6 +49,7 @@
 #define MIPI_CMD_PANEL		9	/* MIPI */
 #define WRITEBACK_PANEL		10	/* Wifi display */
 #define LVDS_PANEL		11	/* LVDS */
+#define EDP_PANEL		12	/* EDP */
 
 enum msm_mdp_hw_revision {
 	MDP_REV_20 = 1,
@@ -207,6 +208,56 @@
 	int (*pll_clk_func) (int enable, struct msm_panel_info *);
 };
 
+struct display_timing_desc {
+	uint32_t pclk;
+	uint32_t h_addressable; /* addressable + boder = active */
+	uint32_t h_border;
+	uint32_t h_blank;	/* fporch + bporch + sync_pulse = blank */
+	uint32_t h_fporch;
+	uint32_t h_sync_pulse;
+	uint32_t v_addressable; /* addressable + boder = active */
+	uint32_t v_border;
+	uint32_t v_blank;	/* fporch + bporch + sync_pulse = blank */
+	uint32_t v_fporch;
+	uint32_t v_sync_pulse;
+	uint32_t width_mm;
+	uint32_t height_mm;
+	uint32_t interlaced;
+	uint32_t stereo;
+	uint32_t sync_type;
+	uint32_t sync_separate;
+	uint32_t vsync_pol;
+	uint32_t hsync_pol;
+};
+
+struct edp_edid {
+	char id_name[4];
+	short id_product;
+	char version;
+	char revision;
+	char video_digital;
+	char color_depth;	/* 6, 8, 10, 12 and 14 bits */
+	char color_format;	/* RGB 4:4:4, YCrCb 4:4:4, Ycrcb 4:2:2 */
+	char dpm;		/* display power management */
+	char sync_digital;	/* 1 = digital */
+	char sync_separate;	/* 1 = separate */
+	char vsync_pol;		/* 0 = negative, 1 = positive */
+	char hsync_pol;		/* 0 = negative, 1 = positive */
+	char ext_block_cnt;
+	struct display_timing_desc timing[4];
+};
+
+struct dpcd_cap {
+	char max_lane_count;
+	uint32_t max_link_clk;  /* 162, 270 and 540 Mb, divided by 10 */
+};
+
+struct edp_panel_data {
+	struct msm_fb_panel_data *panel_data;
+	struct edp_edid edid;
+	struct dpcd_cap dpcd;
+};
+
 
 int msm_display_init(struct msm_fb_panel_data *pdata);
 #endif
diff --git a/platform/msm_shared/mdp3.c b/platform/msm_shared/mdp3.c
index 0629b8e..169dce5 100644
--- a/platform/msm_shared/mdp3.c
+++ b/platform/msm_shared/mdp3.c
@@ -165,7 +165,7 @@
 int mdp_dma_on()
 {
 	int ret = 0;
-
+	mdelay(100);
 	writel(0x00000001, MDP_DMA_P_START);
 
 	return ret;
@@ -180,3 +180,18 @@
 
 	return ret;
 }
+
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+	return NO_ERROR;
+}
+
+int mdp_edp_on(void)
+{
+	return NO_ERROR;
+}
+
+int mdp_edp_off(void)
+{
+	return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp4.c b/platform/msm_shared/mdp4.c
index e347438..b3ade80 100644
--- a/platform/msm_shared/mdp4.c
+++ b/platform/msm_shared/mdp4.c
@@ -408,3 +408,18 @@
 {
 	return mdp_rev;
 }
+
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+	return NO_ERROR;
+}
+
+int mdp_edp_on(void)
+{
+	return NO_ERROR;
+}
+
+int mdp_edp_off(void)
+{
+	return NO_ERROR;
+}
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index e86c8df..1a190ab 100644
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -253,6 +253,11 @@
 	display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period)
 		+lcdc->hsync_skew - 1;
 
+	if (intf_base == MDP_INTF_0_BASE) { /* eDP */
+		display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch;
+		display_vend -= lcdc->h_front_porch;
+	}
+
 	hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width;
 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
 
@@ -278,8 +283,10 @@
 	writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
 	writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
 
-	writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
-
+	if (intf_base == MDP_INTF_0_BASE) /* eDP */
+		writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+	else
+		writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
 }
 
 void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
@@ -368,6 +375,33 @@
 	return 0;
 }
 
+int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb)
+{
+	int ret = NO_ERROR;
+	struct lcdc_panel_info *lcdc = NULL;
+
+	mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE);
+
+	mdp_clk_gating_ctrl();
+
+	mdss_vbif_setup();
+	mdss_smp_setup(pinfo);
+
+	writel(0x0E9, MDP_QOS_REMAPPER_CLASS_0);
+
+	mdss_rgb_pipe_config(fb, pinfo, MDP_VP_0_RGB_0_BASE);
+
+	mdss_layer_mixer_setup(fb, pinfo);
+
+	writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP);
+	writel(0x9, MDP_DISP_INTF_SEL);
+	writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL);
+	writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START);
+	writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START);
+
+	return 0;
+}
+
 int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
                 struct fbcon_config *fb)
 {
@@ -452,3 +486,26 @@
 {
 
 }
+
+int mdp_edp_on(void)
+{
+	writel(0x32048, MDP_CTL_0_BASE + CTL_FLUSH);
+	writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN  + mdss_mdp_intf_offset());
+	return NO_ERROR;
+}
+
+int mdp_edp_off(void)
+{
+	if (!target_cont_splash_screen()) {
+
+		writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN +
+				mdss_mdp_intf_offset());
+		mdelay(60);
+		/* Ping-Pong done Tear Check Read/Write  */
+		/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable  */
+		writel(0xFF777713, MDP_INTR_CLEAR);
+		writel(0x00000000, MDP_INTR_EN);
+	}
+
+	return NO_ERROR;
+}
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 43559eb..6b6e6c6 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -951,7 +951,6 @@
 	unsigned char eof_bllp_pwr,
 	unsigned char interleav)
 {
-
 	int status = 0;
 
 	/* disable mdp first */
@@ -1033,16 +1032,27 @@
 	uint16_t img_width,
 	uint16_t img_height,
 	uint16_t dst_format,
-	uint16_t traffic_mode)
+	uint8_t ystride,
+	uint8_t lane_en,
+	uint8_t interleav)
 {
-	uint8_t DST_FORMAT;
-	uint8_t TRAFIC_MODE;
-	uint8_t DLNx_EN;
-	// video mode data ctrl
-	int status = 0;
-	uint8_t interleav = 0;
-	uint8_t ystride = 0x03;
-	// disable mdp first
+	uint16_t dst_fmt = 0;
+
+	switch (dst_format) {
+	case DSI_VIDEO_DST_FORMAT_RGB565:
+		dst_fmt = DSI_CMD_DST_FORMAT_RGB565;
+		break;
+	case DSI_VIDEO_DST_FORMAT_RGB666:
+	case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE:
+		dst_fmt = DSI_CMD_DST_FORMAT_RGB666;
+		break;
+	case DSI_VIDEO_DST_FORMAT_RGB888:
+		dst_fmt = DSI_CMD_DST_FORMAT_RGB888;
+		break;
+	default:
+		dprintf(CRITICAL, "unsupported dst format\n");
+		return ERROR;
+	}
 
 #if (DISPLAY_TYPE_MDSS == 1)
 	writel(0x00000000, DSI_CLK_CTRL);
@@ -1061,16 +1071,7 @@
 
 	writel(0x02020202, DSI_INT_CTRL);
 
-	DST_FORMAT = 8;		// RGB888
-	dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
-
-	DLNx_EN = 0xf;		// 4 lane with clk programming
-	dprintf(SPEW, "Data Lane: 4 lane\n");
-
-	TRAFIC_MODE = 0;	// non burst mode with sync pulses
-	dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
-
-	writel(DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
+	writel(dst_fmt, DSI_COMMAND_MODE_MDP_CTRL);
 	writel((img_width * ystride + 1) << 16 | 0x0039,
 	       DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
 	writel((img_width * ystride + 1) << 16 | 0x0039,
@@ -1080,13 +1081,13 @@
 	writel(img_height << 16 | img_width,
 	       DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
 	writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
-	writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
+	writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105,
 	       DSI_CTRL);
 	writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
 	writel(0x10000000, DSI_MISR_CMD_CTRL);
 #endif
 
-	return NO_ERROR;
+	return 0;
 }
 
 int mipi_dsi_cmd_mode_config(unsigned short disp_width,
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index cb00a3c..8dae760 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -287,7 +287,7 @@
 		mmc_cid.pnm[6] = 0;
 
 		mmc_cid.prv = UNPACK_BITS(raw_cid, 56, 8, mmc_sizeof);
-		mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 31, mmc_sizeof);
+		mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 32, mmc_sizeof);
 		mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
 		mmc_cid.year = UNPACK_BITS(raw_cid, 12, 8, mmc_sizeof);
 		mmc_cid.year += 2000;
@@ -302,7 +302,7 @@
 		mmc_cid.pnm[6] = 0;
 
 		mmc_cid.prv = UNPACK_BITS(raw_cid, 48, 8, mmc_sizeof);
-		mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 31, mmc_sizeof);
+		mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 32, mmc_sizeof);
 		mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof);
 		mmc_cid.year = UNPACK_BITS(raw_cid, 12, 4, mmc_sizeof);
 		mmc_cid.year += 1997;
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index 5cca931..6c0ae6c 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -227,7 +227,10 @@
 	/* Print out the GPT first */
 	ret = mmc_read(PROTECTIVE_MBR_SIZE, (unsigned int *)data, BLOCK_SIZE);
 	if (ret)
+	{
 		dprintf(CRITICAL, "GPT: Could not read primary gpt from mmc\n");
+		return ret;
+	}
 
 	ret = partition_parse_gpt_header(data, &first_usable_lba,
 					 &partition_entry_size, &header_size,
@@ -441,7 +444,7 @@
 {
 	int byte_length = 8;	/*length of unit (i.e. byte) */
 	int msb = 0;
-	int polynomial = 0x104C11DB7;	/* IEEE 32bit polynomial */
+	int polynomial = 0x04C11DB7;	/* IEEE 32bit polynomial */
 	unsigned int regs = 0xFFFFFFFF;	/* init to all ones */
 	int regs_mask = 0xFFFFFFFF;	/* ensure only 32 bit answer */
 	int regs_msb = 0;
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index f43f1f6..0ffa27c 100755
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -98,7 +98,9 @@
 			$(LOCAL_DIR)/crypto5_wrapper.o \
 			$(LOCAL_DIR)/i2c_qup.o \
 			$(LOCAL_DIR)/gpio.o \
-			$(LOCAL_DIR)/dload_util.o
+			$(LOCAL_DIR)/dload_util.o \
+			$(LOCAL_DIR)/edp.o \
+			$(LOCAL_DIR)/edp_phy.o
 endif
 
 ifeq ($(PLATFORM),msm8226)
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index adeecc8..26e203e 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -308,10 +308,11 @@
 		if(parse_rsp.status == SSD_PMD_ENCRYPTED)
 		{
 			*ctx_id      = parse_rsp.md_ctx_id;
-			*img_len_ptr = *img_len_ptr - (parse_rsp.md_end_ptr - *img_ptr);
+			*img_len_ptr = *img_len_ptr - ((uint8_t*)parse_rsp.md_end_ptr - (uint8_t*)*img_ptr);
 			*img_ptr     = (uint32_t*)parse_rsp.md_end_ptr;
-			ret          = 1;
 		}
+
+		ret = parse_rsp.status;
 	}
 	else
 	{
@@ -330,43 +331,62 @@
 	ssd_decrypt_img_frag_req decrypt_req;
 	ssd_decrypt_img_frag_rsp decrypt_rsp;
 
-	if(ssd_image_is_encrypted(img_ptr,img_len_ptr,&ctx_id))
+	ret = ssd_image_is_encrypted(img_ptr,img_len_ptr,&ctx_id);
+	switch(ret)
 	{
+		case SSD_PMD_ENCRYPTED:
+			/* Image data is operated upon by TZ, which accesses only the main memory.
+			* It must be flushed/invalidated before and after TZ call.
+			*/
 
-		/* Image data is operated upon by TZ, which accesses only the main memory.
-		 * It must be flushed/invalidated before and after TZ call.
-		 */
+			arch_clean_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
 
-		arch_clean_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
+			/*decrypt the image here*/
 
-		/*decrypt the image here*/
+			decrypt_req.md_ctx_id = ctx_id;
+			decrypt_req.last_frag = 1;
+			decrypt_req.frag_len  = *img_len_ptr;
+			decrypt_req.frag      = *img_ptr;
 
-		decrypt_req.md_ctx_id = ctx_id;
-		decrypt_req.last_frag = 1;
-		decrypt_req.frag_len  = *img_len_ptr;
-		decrypt_req.frag      = *img_ptr;
+			ret = scm_call(SCM_SVC_SSD,
+					SSD_DECRYPT_IMG_FRAG_ID,
+					&decrypt_req,
+					sizeof(decrypt_req),
+					&decrypt_rsp,
+					sizeof(decrypt_rsp));
 
-		ret = scm_call(SCM_SVC_SSD,
-				SSD_DECRYPT_IMG_FRAG_ID,
-				&decrypt_req,
-				sizeof(decrypt_req),
-				&decrypt_rsp,
-				sizeof(decrypt_rsp));
+			if(!ret){
+				ret = decrypt_rsp.status;
+			}
 
-		if(!ret){
-			ret = decrypt_rsp.status;
-		}
+			/* Values at img_ptr and img_len_ptr are updated by TZ. Must be invalidated
+			* before we use them.
+			*/
+			arch_invalidate_cache_range((addr_t) img_ptr, sizeof(img_ptr));
+			arch_invalidate_cache_range((addr_t) img_len_ptr, sizeof(img_len_ptr));
 
-		/* Values at img_ptr and img_len_ptr are updated by TZ. Must be invalidated
-		* before we use them.
-		*/
-		arch_invalidate_cache_range((addr_t) img_ptr, sizeof(img_ptr));
-		arch_invalidate_cache_range((addr_t) img_len_ptr, sizeof(img_len_ptr));
+			/* Invalidate the updated image data */
+			arch_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
 
-		/* Invalidate the updated image data */
-		arch_invalidate_cache_range((addr_t) *img_ptr, *img_len_ptr);
+			break;
+
+		case SSD_PMD_NOT_ENCRYPTED:
+		case SSD_PMD_NO_MD_FOUND:
+			ret = 0;
+			break;
+
+		case SSD_PMD_BUSY:
+		case SSD_PMD_BAD_MD_PTR_OR_LEN:
+		case SSD_PMD_PARSING_INCOMPLETE:
+		case SSD_PMD_PARSING_FAILED:
+		case SSD_PMD_SETUP_CIPHER_FAILED:
+			dprintf(CRITICAL,"decrypt_scm_v2: failed status %d\n",ret);
+			break;
+
+		default:
+			dprintf(CRITICAL,"decrypt_scm_v2: case default: failed status %d\n",ret);
+			break;
 	}
-
 	return ret;
 }
 
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index 8ebbce8..ba77c86 100755
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -300,6 +300,7 @@
 	APQ8074   = 184,
 	MSM8274   = 185,
 	MSM8674   = 186,
+	FSM9900   = 188,
 	MSM8974AC = 194,
 	MSM8126   = 198,
 	APQ8026   = 199,
diff --git a/project/fsm9900.mk b/project/fsm9900.mk
new file mode 100644
index 0000000..8945556
--- /dev/null
+++ b/project/fsm9900.mk
@@ -0,0 +1,35 @@
+# top level project rules for the fsm9900 project
+#
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+TARGET := fsm9900
+
+MODULES += app/aboot
+
+DEBUG := 1
+EMMC_BOOT := 1
+ENABLE_SDHCI_SUPPORT := 0
+
+#DEFINES += WITH_DEBUG_DCC=1
+DEFINES += WITH_DEBUG_UART=1
+#DEFINES += WITH_DEBUG_FBCON=1
+DEFINES += DEVICE_TREE=1
+#DEFINES += MMC_BOOT_BAM=1
+DEFINES += CRYPTO_BAM=1
+DEFINES += CRYPTO_REG_ACCESS=1
+DEFINES += ABOOT_IGNORE_BOOT_HEADER_ADDRS=1
+
+#Disable thumb mode
+ENABLE_THUMB := false
+
+DEFINES += ABOOT_FORCE_KERNEL_ADDR=0x00008000
+DEFINES += ABOOT_FORCE_RAMDISK_ADDR=0x02000000
+DEFINES += ABOOT_FORCE_TAGS_ADDR=0x01e00000
+
+ifeq ($(EMMC_BOOT),1)
+DEFINES += _EMMC_BOOT=1
+endif
+
+ifeq ($(ENABLE_SDHCI_SUPPORT),1)
+DEFINES += MMC_SDHCI_SUPPORT=1
+endif
diff --git a/project/msm8974.mk b/project/msm8974.mk
index 17f564b..80b310c 100644
--- a/project/msm8974.mk
+++ b/project/msm8974.mk
@@ -8,7 +8,7 @@
 
 DEBUG := 1
 EMMC_BOOT := 1
-ENABLE_SDHCI_SUPPORT := 0
+ENABLE_SDHCI_SUPPORT := 1
 
 #DEFINES += WITH_DEBUG_DCC=1
 DEFINES += WITH_DEBUG_UART=1
diff --git a/scripts/aboot_test.py b/scripts/aboot_test.py
new file mode 100755
index 0000000..c43364c
--- /dev/null
+++ b/scripts/aboot_test.py
@@ -0,0 +1,189 @@
+# Copyright (c) 2013, The Linux Foundation. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+#     * Neither the name of The Linux Foundation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+# ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+# BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+# * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+# IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#!/usr/bin/python
+
+import os
+import sys
+import time
+import re
+import subprocess
+import getopt
+
+#
+# Erase routine, erase a parition & print the time taken for erase
+#
+def fastboot_erase(partition):
+	start_time = time.time()
+	exe = subprocess.Popen(['fastboot', 'erase', partition], stdout=subprocess.PIPE,stderr=subprocess.STDOUT).stdout.read()
+	print exe
+	print "Time Taken for erase:", partition, ":", time.time() - start_time, "seconds"
+	print("")
+	return
+
+#
+# Flash routine, flash a parition & print the time taken to flash the image
+#
+def fastboot_flash(image_name, partition):
+	start_time = time.time()
+	exe = subprocess.Popen(['fastboot', 'flash', partition, image_name], stdout=subprocess.PIPE,stderr=subprocess.STDOUT).stdout.read()
+	print exe
+	print "Time Taken for flashing:", partition, ":", time.time() - start_time, "seconds"
+	print("")
+	return
+
+#
+# Execute any other fasboot command & print the time taken
+#
+def fastboot_exec(command):
+	start_time = time.time()
+	exe = subprocess.Popen(['fastboot', command], stdout=subprocess.PIPE, stderr=subprocess.STDOUT).stdout.read()
+	print exe
+	print "Time Taken for fastboot:", command, time.time() - start_time, "seconds"
+	print("")
+	return
+
+#
+# Aboot test, Test aboot with different use cases
+#
+def test_aboot(iteration, input_path):
+	system=''
+	userdata=''
+	boot=''
+
+	print ("ABOOT TEST START")
+	t0 = time.clock()
+
+	boot = os.path.join(input_path, 'boot.img')
+	system = os.path.join(input_path, 'system.img')
+	userdata = os.path.join(input_path, 'userdata.img')
+
+	print("")
+	getstate = subprocess.Popen(["fastboot", "devices"], stdout=subprocess.PIPE).communicate()[0]
+	if(re.search("fastboot",getstate) == None):
+		print("Device is not in fastboot, please make sure device is in fastboot mode ... [FAIL]")
+		sys.exit(-1)
+	else:
+		print ("fastboot devices ... [OKAY]")
+		print ("Executing other fastboot tests ...")
+		print("")
+
+	fastboot_erase("boot")
+	time.sleep(2)
+
+	fastboot_exec("reboot")
+	time.sleep(2)
+	fastboot_exec("devices")
+	time.sleep(2)
+	getstate = subprocess.Popen(["fastboot", "devices"], stdout=subprocess.PIPE).communicate()[0]
+	if(re.search("fastboot",getstate) == None):
+		print("fastboot reboot ... [FAIL]")
+		sys.exit(-1)
+
+	iteration = int(iteration)
+
+	# Flash images in a loop
+	i = 0
+	while i < iteration:
+		print "Iteration ", i
+		print ("fastboot flash boot boot.img...")
+		fastboot_flash(boot, 'boot')
+		print("")
+		print ("fastboot flash system system.img ...")
+		fastboot_flash(system, 'system')
+		print("")
+		print ("fastboot flash userdata userdata.img ...")
+		fastboot_flash(userdata, 'userdata')
+		print("")
+		i+=1
+
+	fastboot_exec("reboot")
+	print ("fastboot reboot ... [OKAY]")
+	print("")
+	time.sleep(1)
+	print("Waiting for adb to come up ...")
+	print("")
+	i = 0
+	while i < 10:
+		getstate = subprocess.Popen(["adb", "get-state"], stdout=subprocess.PIPE).communicate()[0]
+		if(re.search("device",getstate) == None):
+			i+=1
+			time.sleep(2)
+		else:
+			print("Device Online")
+			print("")
+			break
+
+	os.system("adb reboot-bootloader")
+	time.sleep(4)
+	getstate = subprocess.Popen(["fastboot", "devices"], stdout=subprocess.PIPE).communicate()[0]
+	if(re.search("fastboot",getstate) == None):
+		print ("adb reboot-bootloader ... [FAIL]")
+		sys.exit(-1)
+	else:
+		print ("adb reboot-bootloader ... [PASS]")
+
+	print("")
+	fastboot_exec("devices")
+	print ("fastboot devices ... [OKAY]")
+	print("")
+
+	fastboot_erase("system")
+	fastboot_erase("userdata")
+
+	fastboot_exec("continue")
+	print ("fastboot continue ... [OKAY]")
+	print("")
+
+	print ("ABOOT TEST DONE")
+	return
+
+# Main function to parse i/p args
+def main(argv):
+	input_path = ''
+	iteration = ''
+	if len(sys.argv) < 2:
+		print "aboot_test.py -i <iterations> -p <Binary Image Path>"
+		sys.exit(2)
+	try:
+		opts, args = getopt.getopt(argv, "hi:p:",["iter=","opath="])
+	except getopt.GetoptError:
+		print "aboot_test.py -i <iterations> -p <Binary Image Path>"
+		sys.exit(2)
+	for opt, arg in opts:
+		if opt == '-h':
+			print "aboot_test.py -i <iterations> -o <Binary Image Path>"
+			sys.exit(2)
+		elif opt in ("-i", "--iter"):
+			iteration = arg
+		elif opt in ("-p", "--opath"):
+			input_path = arg
+	test_aboot(iteration, input_path)
+
+if __name__ == "__main__":
+   main(sys.argv[1:])
diff --git a/target/fsm9900/init.c b/target/fsm9900/init.c
new file mode 100644
index 0000000..8bfc791
--- /dev/null
+++ b/target/fsm9900/init.c
@@ -0,0 +1,486 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/gpio.h>
+#include <reg.h>
+#include <target.h>
+#include <platform.h>
+#include <dload_util.h>
+#include <uart_dm.h>
+#include <mmc.h>
+#include <spmi.h>
+#include <board.h>
+#include <smem.h>
+#include <baseband.h>
+#include <dev/keys.h>
+#include <crypto5_wrapper.h>
+#include <hsusb.h>
+#include <clock.h>
+#include <partition_parser.h>
+#include <scm.h>
+#include <platform/clock.h>
+#include <platform/gpio.h>
+#include <stdlib.h>
+
+extern  bool target_use_signed_kernel(void);
+static void set_sdc_power_ctrl();
+
+static unsigned int target_id;
+
+#if MMC_SDHCI_SUPPORT
+struct mmc_device *dev;
+#endif
+
+#define PMIC_ARB_CHANNEL_NUM    0
+#define PMIC_ARB_OWNER_ID       0
+
+#define WDOG_DEBUG_DISABLE_BIT  17
+
+#define CE_INSTANCE             2
+#define CE_EE                   1
+#define CE_FIFO_SIZE            64
+#define CE_READ_PIPE            3
+#define CE_WRITE_PIPE           2
+#define CE_READ_PIPE_LOCK_GRP   0
+#define CE_WRITE_PIPE_LOCK_GRP  0
+#define CE_ARRAY_SIZE           20
+
+#ifdef SSD_ENABLE
+#define SSD_CE_INSTANCE_1       1
+#define SSD_PARTITION_SIZE      8192
+#endif
+
+#define FASTBOOT_MODE           0x77665500
+
+#define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000)
+
+#if MMC_SDHCI_SUPPORT
+static uint32_t mmc_sdhci_base[] =
+	{ MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
+#endif
+
+static uint32_t mmc_sdc_base[] =
+	{ MSM_SDC1_BASE, MSM_SDC2_BASE };
+
+static uint32_t mmc_sdc_pwrctl_irq[] =
+	{ SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
+
+void target_early_init(void)
+{
+#if WITH_DEBUG_UART
+	uart_dm_init(9, 0, BLSP2_UART3_BASE);
+#endif
+}
+
+/* Return 1 if vol_up pressed */
+static int target_volume_up()
+{
+	return 0;
+}
+
+/* Return 1 if vol_down pressed */
+uint32_t target_volume_down()
+{
+	return 0;
+}
+
+static void target_keystatus()
+{
+	keys_init();
+
+	if (target_volume_down())
+		keys_post_event(KEY_VOLUMEDOWN, 1);
+
+	if (target_volume_up())
+		keys_post_event(KEY_VOLUMEUP, 1);
+}
+
+/* Set up params for h/w CE. */
+void target_crypto_init_params()
+{
+	struct crypto_init_params ce_params;
+
+	/* Set up base addresses and instance. */
+	ce_params.crypto_instance  = CE_INSTANCE;
+	ce_params.crypto_base      = MSM_CE2_BASE;
+	ce_params.bam_base         = MSM_CE2_BAM_BASE;
+
+	/* Set up BAM config. */
+	ce_params.bam_ee               = CE_EE;
+	ce_params.pipes.read_pipe      = CE_READ_PIPE;
+	ce_params.pipes.write_pipe     = CE_WRITE_PIPE;
+	ce_params.pipes.read_pipe_grp  = CE_READ_PIPE_LOCK_GRP;
+	ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
+
+	/* Assign buffer sizes. */
+	ce_params.num_ce           = CE_ARRAY_SIZE;
+	ce_params.read_fifo_size   = CE_FIFO_SIZE;
+	ce_params.write_fifo_size  = CE_FIFO_SIZE;
+
+	/* BAM is initialized by TZ for this platform.
+	 * Do not do it again as the initialization address space
+	 * is locked.
+	 */
+	ce_params.do_bam_init      = 0;
+
+	crypto_init_params(&ce_params);
+}
+
+crypto_engine_type board_ce_type(void)
+{
+	return CRYPTO_ENGINE_TYPE_HW;
+}
+
+#if MMC_SDHCI_SUPPORT
+static void target_mmc_sdhci_init()
+{
+	struct mmc_config_data config = {0};
+
+	config.bus_width = DATA_BUS_WIDTH_8BIT;
+	config.max_clk_rate = MMC_CLK_200MHZ;
+
+	/* Trying Slot 1*/
+	config.slot = 1;
+	config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+	config.pwrctl_base = mmc_sdc_base[config.slot - 1];
+	config.pwr_irq     = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+	if (!(dev = mmc_init(&config))) {
+		/* Trying Slot 2 next */
+		config.slot = 2;
+		config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+		config.pwrctl_base = mmc_sdc_base[config.slot - 1];
+		config.pwr_irq     = mmc_sdc_pwrctl_irq[config.slot - 1];
+
+		if (!(dev = mmc_init(&config))) {
+			dprintf(CRITICAL, "mmc init failed!");
+			ASSERT(0);
+		}
+	}
+
+	/*
+	 * MMC initialization is complete, read the partition table info
+	 */
+	if (partition_read_table()) {
+		dprintf(CRITICAL, "Error reading the partition table info\n");
+		ASSERT(0);
+	}
+}
+
+struct mmc_device *target_mmc_device()
+{
+	return dev;
+}
+
+#else
+
+static void target_mmc_mci_init()
+{
+	uint32_t base_addr;
+	uint8_t slot;
+
+	/* Trying Slot 1 */
+	slot = 1;
+	base_addr = mmc_sdc_base[slot - 1];
+
+	if (mmc_boot_main(slot, base_addr))
+	{
+		/* Trying Slot 2 next */
+		slot = 2;
+		base_addr = mmc_sdc_base[slot - 1];
+		if (mmc_boot_main(slot, base_addr)) {
+			dprintf(CRITICAL, "mmc init failed!");
+			ASSERT(0);
+		}
+	}
+}
+
+/*
+ * Function to set the capabilities for the host
+ */
+void target_mmc_caps(struct mmc_host *host)
+{
+	host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
+	host->caps.ddr_mode = 1;
+	host->caps.hs200_mode = 1;
+	host->caps.hs_clk_rate = MMC_CLK_96MHZ;
+}
+
+#endif
+
+void target_init(void)
+{
+	dprintf(INFO, "target_init()\n");
+
+	target_keystatus();
+
+	if (target_use_signed_kernel())
+		target_crypto_init_params();
+
+	/*
+	 * Set drive strength & pull ctrl for
+	 * emmc
+	 */
+	set_sdc_power_ctrl();
+
+#if MMC_SDHCI_SUPPORT
+	target_mmc_sdhci_init();
+#else
+	target_mmc_mci_init();
+#endif
+}
+
+unsigned board_machtype(void)
+{
+	return target_id;
+}
+
+/* Do any target specific intialization needed before entering fastboot mode */
+#ifdef SSD_ENABLE
+static void ssd_load_keystore_from_emmc()
+{
+	uint64_t           ptn    = 0;
+	int                index  = -1;
+	uint32_t           size   = SSD_PARTITION_SIZE;
+	int                ret    = -1;
+
+	uint32_t *buffer = (uint32_t *)memalign(CACHE_LINE,
+								   ROUNDUP(SSD_PARTITION_SIZE, CACHE_LINE));
+
+	if (!buffer) {
+		dprintf(CRITICAL, "Error Allocating memory for SSD buffer\n");
+		ASSERT(0);
+	}
+
+	index = partition_get_index("ssd");
+
+	ptn   = partition_get_offset(index);
+	if(ptn == 0){
+		dprintf(CRITICAL,"ERROR: ssd parition not found");
+		return;
+	}
+
+	if(mmc_read(ptn, buffer, size)){
+		dprintf(CRITICAL,"ERROR:Cannot read data\n");
+		return;
+	}
+
+	ret = scm_protect_keystore((uint32_t *)&buffer[0],size);
+	if(ret != 0)
+		dprintf(CRITICAL,"ERROR: scm_protect_keystore Failed");
+
+	free(buffer);
+}
+#endif
+
+void target_fastboot_init(void)
+{
+#ifdef SSD_ENABLE
+	clock_ce_enable(SSD_CE_INSTANCE_1);
+	ssd_load_keystore_from_emmc();
+#endif
+}
+
+/* Detect the target type */
+void target_detect(struct board_data *board)
+{
+	board->target = LINUX_MACHTYPE_UNKNOWN;
+}
+
+/* Detect the modem type */
+void target_baseband_detect(struct board_data *board)
+{
+	uint32_t platform;
+	uint32_t platform_subtype;
+
+	platform = board->platform;
+	platform_subtype = board->platform_subtype;
+
+	/*
+	 * Look for platform subtype if present, else
+	 * check for platform type to decide on the
+	 * baseband type
+	 */
+	switch (platform_subtype) {
+	case HW_PLATFORM_SUBTYPE_UNKNOWN:
+		break;
+	default:
+		dprintf(CRITICAL, "Platform Subtype : %u is not supported\n",platform_subtype);
+		ASSERT(0);
+	};
+
+	switch (platform) {
+	case FSM9900:
+		board->baseband = BASEBAND_MSM;
+		break;
+	default:
+		dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
+		ASSERT(0);
+	};
+}
+
+unsigned target_baseband()
+{
+	return board_baseband();
+}
+
+void target_serialno(unsigned char *buf)
+{
+	unsigned int serialno;
+	if (target_is_emmc_boot()) {
+		serialno = mmc_get_psn();
+		snprintf((char *)buf, 13, "%x", serialno);
+	}
+}
+
+unsigned check_reboot_mode(void)
+{
+	uint32_t restart_reason = 0;
+	uint32_t restart_reason_addr;
+
+	restart_reason_addr = RESTART_REASON_ADDR;
+
+	/* Read reboot reason and scrub it */
+	restart_reason = readl(restart_reason_addr);
+	writel(0x00, restart_reason_addr);
+
+	return restart_reason;
+}
+
+void reboot_device(unsigned reboot_reason)
+{
+	/* Write the reboot reason */
+	writel(reboot_reason, RESTART_REASON_ADDR);
+
+	/* Disable Watchdog Debug.
+	 * Required becuase of a H/W bug which causes the system to
+	 * reset partially even for non watchdog resets.
+	 */
+	writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
+
+	dsb();
+
+	/* Wait until the write takes effect. */
+	while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
+
+	/* Drop PS_HOLD for MSM */
+	writel(0x00, MPM2_MPM_PS_HOLD);
+
+	mdelay(5000);
+
+	dprintf(CRITICAL, "Rebooting failed\n");
+}
+
+int set_download_mode(enum dload_mode mode)
+{
+	dload_util_write_cookie(mode == NORMAL_DLOAD ?
+		DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
+
+	return 0;
+}
+
+/* Check if MSM needs VBUS mimic for USB */
+static int target_needs_vbus_mimic()
+{
+	return 0;
+}
+
+/* Do target specific usb initialization */
+void target_usb_init(void)
+{
+}
+
+/* Returns 1 if target supports continuous splash screen. */
+int target_cont_splash_screen()
+{
+	return 0;
+}
+
+unsigned target_pause_for_battery_charge(void)
+{
+	return 0;
+}
+
+void target_uninit(void)
+{
+#if MMC_SDHCI_SUPPORT
+	mmc_put_card_to_sleep(dev);
+#else
+	mmc_put_card_to_sleep();
+#endif
+#ifdef SSD_ENABLE
+	clock_ce_disable(SSD_CE_INSTANCE_1);
+#endif
+}
+
+void shutdown_device()
+{
+	dprintf(CRITICAL, "Going down for shutdown.\n");
+
+	/* Drop PS_HOLD for MSM */
+	writel(0x00, MPM2_MPM_PS_HOLD);
+
+	mdelay(5000);
+
+	dprintf(CRITICAL, "Shutdown failed\n");
+}
+
+static void set_sdc_power_ctrl()
+{
+	/* Drive strength configs for sdc pins */
+	struct tlmm_cfgs sdc1_hdrv_cfg[] =
+	{
+		{ SDC1_CLK_HDRV_CTL_OFF,  TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
+		{ SDC1_CMD_HDRV_CTL_OFF,  TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+		{ SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
+	};
+
+	/* Pull configs for sdc pins */
+	struct tlmm_cfgs sdc1_pull_cfg[] =
+	{
+		{ SDC1_CLK_PULL_CTL_OFF,  TLMM_NO_PULL, TLMM_PULL_MASK },
+		{ SDC1_CMD_PULL_CTL_OFF,  TLMM_PULL_UP, TLMM_PULL_MASK },
+		{ SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
+	};
+
+	/* Set the drive strength & pull control values */
+	tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
+	tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
+}
+
+int emmc_recovery_init(void)
+{
+	return _emmc_recovery_init();
+}
+
+void target_usb_stop(void)
+{
+}
diff --git a/target/fsm9900/meminfo.c b/target/fsm9900/meminfo.c
new file mode 100644
index 0000000..5f9c490
--- /dev/null
+++ b/target/fsm9900/meminfo.c
@@ -0,0 +1,89 @@
+/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of The Linux Foundation nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if DEVICE_TREE /* If using device tree */
+
+#include <reg.h>
+#include <debug.h>
+#include <malloc.h>
+#include <smem.h>
+#include <stdint.h>
+#include <libfdt.h>
+#include <platform/iomap.h>
+#include <dev_tree.h>
+
+/* Funtion to add the ram partition entries into device tree.
+ * The function assumes that all the entire fixed memory regions should
+ * be listed in the first bank of the passed in ddr regions.
+ */
+uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
+{
+    struct smem_ram_ptable ram_ptable;
+    unsigned int i;
+	int ret = 0;
+
+	/* Make sure RAM partition table is initialized */
+	ASSERT(smem_ram_ptable_init(&ram_ptable));
+
+     /* Calculating the size of the mem_info_ptr */
+    for (i = 0 ; i < ram_ptable.len; i++)
+    {
+        if((ram_ptable.parts[i].category == SDRAM) &&
+           (ram_ptable.parts[i].type == SYS_MEMORY))
+        {
+
+			/* Pass along all other usable memory regions to Linux */
+			ret = dev_tree_add_mem_info(fdt,
+										memory_node_offset,
+										ram_ptable.parts[i].start,
+										ram_ptable.parts[i].size);
+
+			if (ret)
+			{
+				dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n");
+				goto target_dev_tree_mem_err;
+			}
+
+       }
+    }
+
+target_dev_tree_mem_err:
+
+    return ret;
+}
+
+void *target_get_scratch_address(void)
+{
+	return ((void *)SCRATCH_ADDR);
+}
+
+unsigned target_get_max_flash_size(void)
+{
+	return (512 * 1024 * 1024);
+}
+#endif /* DEVICE_TREE */
diff --git a/target/fsm9900/rules.mk b/target/fsm9900/rules.mk
new file mode 100644
index 0000000..64f97aa
--- /dev/null
+++ b/target/fsm9900/rules.mk
@@ -0,0 +1,35 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared
+
+PLATFORM := fsm9900
+
+MEMBASE := 0x0F900000 # SDRAM
+MEMSIZE := 0x00100000 # 1MB
+
+BASE_ADDR        := 0x00000
+
+TAGS_ADDR        := BASE_ADDR+0x00000100
+KERNEL_ADDR      := BASE_ADDR+0x00008000
+RAMDISK_ADDR     := BASE_ADDR+0x01000000
+SCRATCH_ADDR     := 0x11000000
+
+MODULES += \
+	dev/keys \
+	dev/panel/msm \
+    lib/ptable \
+    lib/libfdt
+
+DEFINES += \
+	MEMSIZE=$(MEMSIZE) \
+	MEMBASE=$(MEMBASE) \
+	BASE_ADDR=$(BASE_ADDR) \
+	TAGS_ADDR=$(TAGS_ADDR) \
+	KERNEL_ADDR=$(KERNEL_ADDR) \
+	RAMDISK_ADDR=$(RAMDISK_ADDR) \
+	SCRATCH_ADDR=$(SCRATCH_ADDR)
+
+
+OBJS += \
+    $(LOCAL_DIR)/init.o \
+    $(LOCAL_DIR)/meminfo.o
diff --git a/target/fsm9900/tools/makefile b/target/fsm9900/tools/makefile
new file mode 100644
index 0000000..2757e07
--- /dev/null
+++ b/target/fsm9900/tools/makefile
@@ -0,0 +1,44 @@
+#Makefile to generate appsboot.mbn
+
+ifeq ($(BOOTLOADER_OUT),.)
+APPSBOOTHEADER_DIR  := $(BUILDDIR)
+else
+APPSBOOTHEADER_DIR  := $(BOOTLOADER_OUT)/../..
+endif
+
+SRC_DIR  := target/$(TARGET)/tools
+COMPILER := gcc
+
+ifeq ($(EMMC_BOOT), 1)
+  APPSBOOTHDR_FILES := EMMCBOOT.MBN
+else
+  ifeq ($(BUILD_NANDWRITE), 1)
+    APPSBOOTHDR_FILES :=
+  else
+    APPSBOOTHDR_FILES := appsboot.mbn
+  endif
+endif
+
+APPSBOOTHEADER: $(APPSBOOTHDR_FILES)
+
+
+appsboot.mbn: appsboothd.mbn $(OUTBIN)
+	cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboot.raw
+	cat $(APPSBOOTHEADER_DIR)/appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/appsboot.mbn
+	rm -f $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+appsboothd.mbn: mkheader $(OUTBIN)
+	$(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/appsboothd.mbn
+
+EMMCBOOT.MBN: emmc_appsboothd.mbn $(OUTBIN)
+	cp $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboot.raw
+	cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/EMMCBOOT.MBN
+	cat $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn $(OUTBIN) > $(APPSBOOTHEADER_DIR)/emmc_appsboot.mbn
+	rm -f $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+emmc_appsboothd.mbn: mkheader $(OUTBIN)
+	$(BUILDDIR)/mkheader $(OUTBIN) $(APPSBOOTHEADER_DIR)/emmc_appsboothd.mbn
+
+mkheader: $(SRC_DIR)/mkheader.c
+	@mkdir -p $(BUILDDIR)
+	${COMPILER} -DMEMBASE=$(MEMBASE) $(SRC_DIR)/mkheader.c -o $(BUILDDIR)/mkheader
diff --git a/target/fsm9900/tools/mkheader.c b/target/fsm9900/tools/mkheader.c
new file mode 100644
index 0000000..4a84bd6
--- /dev/null
+++ b/target/fsm9900/tools/mkheader.c
@@ -0,0 +1,344 @@
+/*
+ * Copyright (c) 2007, Google Inc.
+ * All rights reserved.
+ *
+ * Copyright (c) 2009-2011, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name of Google, Inc. nor the names of its contributors
+ *    may be used to endorse or promote products derived from this
+ *    software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <string.h>
+
+#include <sys/stat.h>
+
+int print_usage()
+{
+	fprintf(stderr, "usage: mkheader <bin> <hdr> <none|unified-boot>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <unsecure-boot>"
+		" <outbin>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <secure-boot> <outbin>"
+		" <maxsize>\n");
+	fprintf(stderr, "       mkheader <bin> <hdr> <secure-boot> <outbin>"
+		" <maxsize> <certchain> <files...>\n\n");
+	fprintf(stderr, "bin:               Input raw appsbl binary\n");
+	fprintf(stderr,
+		"hdr:               Output of appsbl header location\n");
+	fprintf(stderr,
+		"outbin:            Output of the signed or unsigned"
+		" apps boot location\n");
+	fprintf(stderr,
+		"maxsize:           Maximum size for certificate" " chain\n");
+	fprintf(stderr,
+		"certchain:         Output of the certchain location\n");
+	fprintf(stderr,
+		"files:             Input format <bin signature>"
+		" <certifcate file(s) for certificate chain>...\n");
+	fprintf(stderr,
+		"certificate chain: Files will be concatenated in order"
+		" to create the certificate chain\n\n");
+	return -1;
+}
+
+int cat(FILE * in, FILE * out, unsigned size, unsigned buff_size)
+{
+	unsigned bytes_left = size;
+	char buf[buff_size];
+	int ret = 0;
+
+	while (bytes_left) {
+		fread(buf, sizeof(char), buff_size, in);
+		if (!feof(in)) {
+			bytes_left -= fwrite(buf, sizeof(char), buff_size, out);
+		} else
+			bytes_left = 0;
+	}
+	ret = ferror(in) | ferror(out);
+	if (ret)
+		fprintf(stderr, "ERROR: Occured during file concatenation\n");
+	return ret;
+}
+
+int main(int argc, char *argv[])
+{
+	struct stat s;
+	unsigned size, base;
+	int unified_boot = 0;
+	unsigned unified_boot_magic[20];
+	unsigned non_unified_boot_magic[10];
+	unsigned magic_len = 0;
+	unsigned *magic;
+	unsigned cert_chain_size = 0;
+	unsigned signature_size = 0;
+	int secure_boot = 0;
+	int fd;
+
+	if (argc < 3) {
+		return print_usage();
+	}
+
+	if (argc == 4) {
+		if (!strcmp("unified-boot", argv[3])) {
+			unified_boot = 1;
+		} else if (!strcmp("secure-boot", argv[3])) {
+			fprintf(stderr,
+				"ERROR: Missing arguments: [outbin maxsize] |"
+				" [outbin, maxsize, certchain,"
+				" signature + certifcate(s)]\n");
+			return print_usage();
+		} else if (!strcmp("unsecure-boot", argv[3])) {
+			fprintf(stderr, "ERROR: Missing arguments:"
+				" outbin directory\n");
+			return print_usage();
+		}
+	}
+
+	if (argc > 4) {
+		if (!strcmp("secure-boot", argv[3])) {
+			if (argc < 9 && argc != 6) {
+				fprintf(stderr,
+					"ERROR: Missing argument(s):"
+					" [outbin maxsize] | [outbin, maxsize,"
+					" certchain,"
+					" signature + certifcate(s)]\n");
+				return print_usage();
+			}
+			secure_boot = 1;
+			signature_size = 256;	//Support SHA 256
+			cert_chain_size = atoi(argv[5]);
+		}
+	}
+
+	if (stat(argv[1], &s)) {
+		perror("cannot stat binary");
+		return -1;
+	}
+
+	if (unified_boot) {
+		magic = unified_boot_magic;
+		magic_len = sizeof(unified_boot_magic);
+	} else {
+		magic = non_unified_boot_magic;
+		magic_len = sizeof(non_unified_boot_magic);
+	}
+
+	size = s.st_size;
+#if MEMBASE
+	base = MEMBASE;
+#else
+	base = 0;
+#endif
+
+	printf("Image Destination Pointer: 0x%x\n", base);
+
+	magic[0] = 0x00000005;	/* appsbl */
+	magic[1] = 0x00000003;	//Flash_partition_version /* nand */
+	magic[2] = 0x00000000;	//image source pointer
+	magic[3] = base;	//image destination pointer
+	magic[4] = size + cert_chain_size + signature_size;	//image size
+	magic[5] = size;	//code size
+	magic[6] = base + size;
+	magic[7] = signature_size;
+	magic[8] = size + base + signature_size;
+	magic[9] = cert_chain_size;
+
+	if (unified_boot == 1) {
+		magic[10] = 0x33836685;	/* cookie magic number */
+		magic[11] = 0x00000001;	/* cookie version */
+		magic[12] = 0x00000002;	/* file formats */
+		magic[13] = 0x00000000;
+		magic[14] = 0x00000000;	/* not setting size for boot.img */
+		magic[15] = 0x00000000;
+		magic[16] = 0x00000000;
+		magic[17] = 0x00000000;
+		magic[18] = 0x00000000;
+		magic[19] = 0x00000000;
+	}
+
+	fd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, 0644);
+	if (fd < 0) {
+		perror("cannot open header for writing");
+		return -1;
+	}
+	if (write(fd, magic, magic_len) != magic_len) {
+		perror("cannot write header");
+		close(fd);
+		unlink(argv[2]);
+		return -1;
+	}
+	close(fd);
+
+	if (secure_boot && argc > 6) {
+		FILE *input_file;
+		FILE *output_file;
+		unsigned buff_size = 1;
+		char buf[buff_size];
+		unsigned bytes_left;
+		unsigned current_cert_chain_size = 0;
+		int padding_size = 0;
+		int i;
+
+		if ((output_file = fopen(argv[6], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Certificate Chain Output File: %s\n", argv[6]);
+
+		for (i = 8; i < argc; i++) {
+			if ((input_file = fopen(argv[i], "rb")) == NULL) {
+				perror("ERROR: Occured during fopen");
+				return -1;
+			}
+			stat(argv[i], &s);
+			bytes_left = s.st_size;
+			current_cert_chain_size += bytes_left;
+			if (cat(input_file, output_file, bytes_left, buff_size))
+				return -1;
+			fclose(input_file);
+		}
+
+		//Pad certifcate chain to the max expected size from input
+		memset(buf, 0xFF, sizeof(buf));
+		padding_size = cert_chain_size - current_cert_chain_size;
+
+		if (padding_size < 0) {
+			fprintf(stderr, "ERROR: Input certificate chain"
+				" (Size=%d) is larger than the maximum"
+				" specified (Size=%d)\n",
+				current_cert_chain_size, cert_chain_size);
+			return -1;
+		}
+
+		bytes_left = (padding_size > 0) ? padding_size : 0;
+		while (bytes_left) {
+			if (!ferror(output_file))
+				bytes_left -= fwrite(buf,
+						     sizeof(buf),
+						     buff_size, output_file);
+			else {
+				fprintf(stderr, "ERROR: Occured during"
+					" certifcate chain padding\n");
+				return -1;
+			}
+		}
+		fclose(output_file);
+
+		/* Concat and combine to signed image.
+		 * Format [HDR][RAW APPSBOOT][PADDED CERT CHAIN]
+		 */
+		if ((output_file = fopen(argv[4], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Image Output File: %s\n", argv[4]);
+
+		//Header
+		if ((input_file = fopen(argv[2], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[2], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Raw Appsbl
+		if ((input_file = fopen(argv[1], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[1], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Signature
+		if ((input_file = fopen(argv[7], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[7], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Certifcate Chain
+		if ((input_file = fopen(argv[6], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		if (cat(input_file, output_file,
+			(current_cert_chain_size + padding_size), buff_size))
+			return -1;
+		fclose(input_file);
+
+		fclose(output_file);
+
+	} else if (argc == 5 || argc == 6) {
+		FILE *input_file;
+		FILE *output_file;
+		unsigned buff_size = 1;
+		char buf[buff_size];
+
+		/* Concat and combine to unsigned image.
+		 * Format [HDR][RAW APPSBOOT]
+		 */
+		if ((output_file = fopen(argv[4], "wb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		printf("Image Output File: %s\n", argv[4]);
+
+		//Header
+		if ((input_file = fopen(argv[2], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[2], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+
+		//Raw Appsbl
+		if ((input_file = fopen(argv[1], "rb")) == NULL) {
+			perror("ERROR: Occured during fopen");
+			return -1;
+		}
+		stat(argv[1], &s);
+		if (cat(input_file, output_file, s.st_size, buff_size))
+			return -1;
+		fclose(input_file);
+		fclose(output_file);
+	}
+
+	printf("Done execution\n");
+
+	return 0;
+}
diff --git a/target/msm8226/target_display.c b/target/msm8226/target_display.c
index 2da792e..a30b568 100755
--- a/target/msm8226/target_display.c
+++ b/target/msm8226/target_display.c
@@ -43,12 +43,10 @@
 #include "include/display_resource.h"
 
 static struct pm8x41_wled_data wled_ctrl = {
-	.mod_scheme      = 0xC3,
+	.mod_scheme      = 0x00,
 	.led1_brightness = (0x0F << 8) | 0xEF,
-	.led2_brightness = (0x0F << 8) | 0xEF,
-	.led3_brightness = (0x0F << 8) | 0xEF,
 	.max_duty_cycle  = 0x01,
-	.ovp = 0x2,
+	.ovp = 0x0,
 	.full_current_scale = 0x19
 };
 
diff --git a/target/msm8974/target_display.c b/target/msm8974/target_display.c
index d612015..2329965 100644
--- a/target/msm8974/target_display.c
+++ b/target/msm8974/target_display.c
@@ -48,7 +48,7 @@
 extern int mdss_sharp_dsi_uniphy_pll_config(uint32_t ctl_base);
 
 static struct pm8x41_wled_data wled_ctrl = {
-	.mod_scheme      = 0xC3,
+	.mod_scheme      = 0x00,
 	.led1_brightness = (0x0F << 8) | 0xEF,
 	.led2_brightness = (0x0F << 8) | 0xEF,
 	.led3_brightness = (0x0F << 8) | 0xEF,