tree b9febb99cb65dc46fa55466f7902d839bac77cd5
parent 53d5f1fe9a2764a2df4e0a848926fb824af30950
author Kuogee Hsieh <khsieh@codeaurora.org> 1441050278 -0700
committer Kuogee Hsieh <khsieh@codeaurora.org> 1441318177 -0700

dev: gcdb: display: fix pclk calculation

Fix DSI pixel clock calculation by using vco_clk as
the dividend. Also, fix the possibility of overflow
when using 32 bit unsigned integer.

Change-Id: I61896a8bc1cf7ab6106d75868156730a446516f4