[arch] factor out the debug_cycle_count to arch specific code
Conflicts:
arch/arm/ops.S
Change-Id: Id0d9baa3e669cc59822819c797ce913dba1606d6
diff --git a/arch/arm/arch.c b/arch/arm/arch.c
index 37b557c..7a5f85b 100644
--- a/arch/arm/arch.c
+++ b/arch/arm/arch.c
@@ -64,6 +64,19 @@
val = (1<<30);
__asm__ volatile("mcr p10, 7, %0, c8, c0, 0" :: "r" (val));
#endif
+
+#if ARM_CPU_CORTEX_A8
+ /* enable the cycle count register */
+ uint32_t en;
+ __asm__ volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (en));
+ en &= ~(1<<3); /* cycle count every cycle */
+ en |= 1; /* enable all performance counters */
+ __asm__ volatile("mcr p15, 0, %0, c9, c12, 0" :: "r" (en));
+
+ /* enable cycle counter */
+ en = (1<<31);
+ __asm__ volatile("mcr p15, 0, %0, c9, c12, 1" :: "r" (en));
+#endif
}
void arch_init(void)
diff --git a/arch/arm/ops.S b/arch/arm/ops.S
index 96b7445..c9660e7 100644
--- a/arch/arm/ops.S
+++ b/arch/arm/ops.S
@@ -221,3 +221,15 @@
mcr p15, 0, r0, c7, c10, 4
#endif
bx lr
+
+/* uint32_t arm_read_cycle_count(void); */
+FUNCTION(arm_read_cycle_count)
+
+/* uint32_t arch_cycle_count(void); */
+FUNCTION(arch_cycle_count)
+#if ARM_CPU_CORTEX_A8
+ mrc p15, 0, r0, c9, c13, 0
+#else
+ mov r0, #0
+#endif
+ bx lr
diff --git a/arch/x86/arch.c b/arch/x86/arch.c
index 99ca572..bb6a17b 100644
--- a/arch/x86/arch.c
+++ b/arch/x86/arch.c
@@ -60,3 +60,11 @@
{
}
+uint32_t arch_cycle_count(void)
+{
+ uint32_t timestamp;
+ rdtscl(timestamp);
+
+ return timestamp;
+}
+