diff --git a/app/aboot/aboot.c b/app/aboot/aboot.c
index b51d450..25755a1 100644
--- a/app/aboot/aboot.c
+++ b/app/aboot/aboot.c
@@ -1904,24 +1904,25 @@
 	lun = partition_get_lun(index);
 	mmc_set_lun(lun);
 
-#if MMC_SDHCI_SUPPORT
-	if (mmc_erase_card(ptn, size)) {
-		fastboot_fail("failed to erase partition\n");
-		return;
-	}
-#else
-	BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
-	size = partition_get_size(index);
-	if (size > DEFAULT_ERASE_SIZE)
-		size = DEFAULT_ERASE_SIZE;
+	if (platform_boot_dev_isemmc())
+	{
+		if (mmc_erase_card(ptn, size)) {
+			fastboot_fail("failed to erase partition\n");
+			return;
+		}
+	} else {
+		BUF_DMA_ALIGN(out, DEFAULT_ERASE_SIZE);
+		size = partition_get_size(index);
+		if (size > DEFAULT_ERASE_SIZE)
+			size = DEFAULT_ERASE_SIZE;
 
-	/* Simple inefficient version of erase. Just writing
-       0 in first several blocks */
-	if (mmc_write(ptn , size, (unsigned int *)out)) {
-		fastboot_fail("failed to erase partition");
-		return;
+		/* Simple inefficient version of erase. Just writing
+	       0 in first several blocks */
+		if (mmc_write(ptn , size, (unsigned int *)out)) {
+			fastboot_fail("failed to erase partition");
+			return;
+		}
 	}
-#endif
 	fastboot_okay("");
 }
 
diff --git a/app/aboot/fastboot.c b/app/aboot/fastboot.c
index 9dac985..4dc955d 100644
--- a/app/aboot/fastboot.c
+++ b/app/aboot/fastboot.c
@@ -456,6 +456,10 @@
 	snprintf((char *)response, MAX_RSP_SIZE, "DATA%08x", len);
 	if (usb_if.usb_write(response, strlen((const char *)response)) < 0)
 		return;
+	/*
+	 * Discard the cache contents before starting the download
+	 */
+	arch_invalidate_cache_range((addr_t) download_base, sz);
 
 	r = usb_if.usb_read(download_base, len);
 	if ((r < 0) || ((unsigned) r != len)) {
diff --git a/dev/gcdb/display/include/panel_hx8394d_720p_video.h b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
index 3ab32f8..ac4806f 100644
--- a/dev/gcdb/display/include/panel_hx8394d_720p_video.h
+++ b/dev/gcdb/display/include/panel_hx8394d_720p_video.h
@@ -283,6 +283,6 @@
   1, 1, 4095, 100, 1, "PMIC_8941"
 };
 
-#define HX8394D_720P_VIDEO_SIGNATURE 0xFFFF
+#define HX8394D_720P_VIDEO_SIGNATURE 0xa0087
 
 #endif /*_HX8394D_720P_VIDEO_H_*/
diff --git a/dev/gcdb/display/include/panel_r61318_hd_video.h b/dev/gcdb/display/include/panel_r61318_hd_video.h
index 72c27c2..7662312 100644
--- a/dev/gcdb/display/include/panel_r61318_hd_video.h
+++ b/dev/gcdb/display/include/panel_r61318_hd_video.h
@@ -181,20 +181,25 @@
 };
 
 static char r61318_hd_video_on_cmd19[] = {
-	0x02, 0x00, 0x39, 0xC0,
-	0x53, 0x24, 0xFF, 0xFF,
+	0x02, 0x00, 0x29, 0xC0,
+	0xBB, 0x2E, 0xFF, 0xFF
 };
 
 static char r61318_hd_video_on_cmd20[] = {
 	0x02, 0x00, 0x39, 0xC0,
-	0x51, 0xff, 0xFF, 0xFF,
+	0x53, 0x2C, 0xFF, 0xFF
 };
 
 static char r61318_hd_video_on_cmd21[] = {
-	0x11, 0x00, 0x05, 0x80
+	0x02, 0x00, 0x39, 0xC0,
+	0x51, 0xff, 0xFF, 0xFF,
 };
 
 static char r61318_hd_video_on_cmd22[] = {
+	0x11, 0x00, 0x05, 0x80
+};
+
+static char r61318_hd_video_on_cmd23[] = {
 	0x29, 0x00, 0x05, 0x80
 };
 
@@ -220,11 +225,12 @@
 	{0x8, r61318_hd_video_on_cmd18, 0x00},
 	{0x8, r61318_hd_video_on_cmd19, 0x00},
 	{0x8, r61318_hd_video_on_cmd20, 0x00},
-	{0x4, r61318_hd_video_on_cmd21, 0x78},
-	{0x4, r61318_hd_video_on_cmd22, 0x32}
+	{0x8, r61318_hd_video_on_cmd21, 0x00},
+	{0x4, r61318_hd_video_on_cmd22, 0x78},
+	{0x4, r61318_hd_video_on_cmd23, 0x32}
 };
 
-#define R61318_HD_VIDEO_ON_COMMAND 23
+#define R61318_HD_VIDEO_ON_COMMAND 24
 
 
 static char r61318_hd_videooff_cmd0[] = {
diff --git a/lib/libc/malloc.c b/lib/libc/malloc.c
index 6f05f63..9cec44c 100644
--- a/lib/libc/malloc.c
+++ b/lib/libc/malloc.c
@@ -24,6 +24,7 @@
 #include <malloc.h>
 #include <string.h>
 #include <lib/heap.h>
+#include <arch/ops.h>
 
 void *malloc(size_t size)
 {
@@ -32,7 +33,11 @@
 
 void *memalign(size_t boundary, size_t size)
 {
-	return heap_alloc(size, boundary);
+	void *ptr;
+	ptr = heap_alloc(size, boundary);
+	/* Clean the cache before giving the memory */
+	arch_invalidate_cache_range((addr_t) ptr, size);
+	return ptr;
 }
 
 void *calloc(size_t count, size_t size)
diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index e2a66fe..bca7c54 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -280,4 +280,5 @@
 #define SECURITY_CONTROL_CORE_FEATURE_CONFIG0    0x0005E004
 /* EBI2 */
 #define TLMM_EBI2_EMMC_GPIO_CFG     (TLMM_BASE_ADDR + 0x00111000)
+#define TCSR_BOOT_MISC_DETECT       0x193D100
 #endif
diff --git a/platform/msm8916/include/platform/iomap.h b/platform/msm8916/include/platform/iomap.h
index fd56c0e..d98bbdf 100644
--- a/platform/msm8916/include/platform/iomap.h
+++ b/platform/msm8916/include/platform/iomap.h
@@ -265,4 +265,5 @@
 #define HS_TIMER_CTRL               0x0BC
 
 #define TCSR_TZ_WONCE               0x193D000
+#define TCSR_BOOT_MISC_DETECT       0x193D100
 #endif
diff --git a/platform/msm8994/platform.c b/platform/msm8994/platform.c
index 507158b..eaaadc0 100644
--- a/platform/msm8994/platform.c
+++ b/platform/msm8994/platform.c
@@ -40,7 +40,7 @@
 #define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
 
 /* LK memory - cacheable, write through */
-#define LK_MEMORY         (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+#define LK_MEMORY         (MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
                            MMU_MEMORY_AP_READ_WRITE)
 
 /* Peripherals - non-shared device */
@@ -123,7 +123,7 @@
 										sections * MB,
 										ptn_entry.start +
 										sections * MB,
-										(MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+										(MMU_MEMORY_TYPE_NORMAL_WRITE_BACK_ALLOCATE | \
 										 MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
 				}
 			}
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index 283f1cc..83685d5 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -256,6 +256,7 @@
 
 #define PRNG_CMD_ID                 0x01
 #define IS_CALL_AVAIL_CMD           0x01
+#define IS_SECURE_BOOT_ENABLED      0x04
 
 /* Download Mode specific arguments to be passed to TZ */
 #define SCM_EDLOAD_MODE 0x01
@@ -337,6 +338,7 @@
 
 #define SCM_SVC_PWR                     0x9
 #define SCM_IO_DISABLE_PMIC_ARBITER     0x1
+#define SCM_IO_DISABLE_PMIC_ARBITER1    0x2
 
 #define SCM_SVC_MILESTONE_32_64_ID      0x1
 #define SCM_SVC_MILESTONE_CMD_ID        0xf
@@ -349,6 +351,11 @@
 /* Apps CE resource. */
 #define TZ_RESOURCE_CE_AP  2
 
+/* Secure IO Service IDs */
+#define SCM_IO_READ     0x1
+#define SCM_IO_WRITE    0x2
+#define SCM_SVC_IO      0x5
+
 uint8_t switch_ce_chn_cmd(enum ap_ce_channel_type channel);
 
 /**
@@ -443,4 +450,5 @@
  * Used for checking if armv8 SCM support present
  */
 void scm_init();
+bool is_secure_boot_enable();
 #endif
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index bcec0ad..fcd0cef 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are
@@ -124,6 +124,12 @@
 	if (data_len % block_size)
 		data_len = ROUNDUP(data_len, block_size);
 
+	/*
+	 * Flush the cache before handing over the data to
+	 * storage driver
+	 */
+	arch_clean_invalidate_cache_range((addr_t)in, data_len);
+
 	if (platform_boot_dev_isemmc())
 	{
 		/* TODO: This function is aware of max data that can be
@@ -151,8 +157,6 @@
 	}
 	else
 	{
-		arch_clean_invalidate_cache_range((addr_t)in, data_len);
-
 		ret = ufs_write((struct ufs_dev *)dev, data_addr, (addr_t)in, (data_len / block_size));
 
 		if (ret)
@@ -296,6 +300,9 @@
 
 	memset((void *)out, 0, erase_size);
 
+	/* Flush the data to memory before writing to storage */
+	arch_clean_invalidate_cache_range((addr_t) out , erase_size);
+
 	if (mmc_sdhci_write(dev, out, blk_addr, num_blks))
 	{
 		dprintf(CRITICAL, "failed to erase the partition: %x\n", blk_addr);
@@ -614,7 +621,8 @@
 			return 1;
 		}
 
-		size = partition_get_size(index);
+		/* Convert the size to blocks */
+		size = partition_get_size(index) / block_size;
 
 		/*
 		 * For read only partitions the minimum size allocated on the disk is
@@ -623,6 +631,7 @@
 		 */
 		if (partition_read_only(index) && size < card->wp_grp_size)
 		{
+			/* Write protect api takes the size in bytes, convert size to bytes */
 			size = card->wp_grp_size * block_size;
 		}
 		/* Set the power on WP bit */
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index b45fd3d..681b238 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -34,6 +34,8 @@
 #include <arch/ops.h>
 #include <rand.h>
 #include <image_verify.h>
+#include <dload_util.h>
+#include <platform/iomap.h>
 #include "scm.h"
 
 #pragma GCC optimize ("O0")
@@ -54,6 +56,7 @@
 
 /* SCM interface as per ARM spec present? */
 bool scm_arm_support;
+static uint32_t scm_io_write(uint32_t address, uint32_t val);
 
 static void scm_arm_support_available(uint32_t svc_id, uint32_t cmd_id)
 {
@@ -958,14 +961,29 @@
 int scm_halt_pmic_arbiter()
 {
 	int ret = 0;
+	scmcall_arg scm_arg = {0};
 
-	if (scm_arm_support)
-	{
-		dprintf(INFO, "%s:SCM call is not supported\n",__func__);
-		return -1;
+	if (scm_arm_support) {
+		scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER);
+		scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+		scm_arg.x2 = 0;
+		scm_arg.atomic = true;
+		ret = scm_call2(&scm_arg, NULL);
+	} else {
+		ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER, 0);
 	}
 
-	ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER, 0);
+	/* Retry with the SCM_IO_DISABLE_PMIC_ARBITER1 func ID if the above Func ID fails*/
+	if(ret) {
+		if (scm_arm_support) {
+			scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER1);
+			scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+			scm_arg.x2 = 0;
+			scm_arg.atomic = true;
+			ret = scm_call2(&scm_arg, NULL);
+		} else
+			ret = scm_call_atomic(SCM_SVC_PWR, SCM_IO_DISABLE_PMIC_ARBITER1, 0);
+	}
 
 	return ret;
 }
@@ -1178,3 +1196,133 @@
 
 	return 0;
 }
+
+static bool secure_boot_enable = false;
+static bool wdog_debug_fuse_disable = false;
+
+void scm_check_boot_fuses()
+{
+	uint32_t ret = 0;
+	uint32_t resp;
+	scmcall_arg scm_arg = {0};
+	scmcall_ret scm_ret = {0};
+
+	if (!scm_arm_support) {
+		ret = scm_call(TZBSP_SVC_INFO, IS_SECURE_BOOT_ENABLED, NULL, 0, &resp, sizeof(resp));
+	} else {
+		scm_arg.x0 = MAKE_SIP_SCM_CMD(TZBSP_SVC_INFO, IS_SECURE_BOOT_ENABLED);
+		ret = scm_call2(&scm_arg, &scm_ret);
+		resp = scm_ret.x1;
+	}
+
+	/* Parse Bit 0 and Bit 2 of the response */
+	if(!ret) {
+		/* Bit 0 - SECBOOT_ENABLE_CHECK */
+		if(resp & 0x1)
+			secure_boot_enable = true;
+		/* Bit 2 - DEBUG_DISABLE_CHECK */
+		if(resp & 0x4)
+			wdog_debug_fuse_disable = true;
+	} else
+		dprintf(CRITICAL, "scm call to check secure boot fuses failed\n");
+}
+
+bool is_secure_boot_enable()
+{
+	scm_check_boot_fuses();
+	return secure_boot_enable;
+}
+
+static uint32_t scm_io_read(addr_t address)
+{
+	uint32_t ret;
+	scmcall_arg scm_arg = {0};
+	scmcall_ret scm_ret = {0};
+
+	if (!scm_arm_support) {
+		ret = scm_call_atomic(SCM_SVC_IO, SCM_IO_READ, address);
+	} else {
+		scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_IO, SCM_IO_READ);
+		scm_arg.x1 = MAKE_SCM_ARGS(0x1);
+		scm_arg.x2 = address;
+		scm_arg.atomic = true;
+		ret = scm_call2(&scm_arg, &scm_ret);
+	}
+	return ret;
+}
+
+static uint32_t scm_io_write(uint32_t address, uint32_t val)
+{
+	uint32_t ret;
+	scmcall_arg scm_arg = {0};
+	scmcall_ret scm_ret = {0};
+
+	if (!scm_arm_support) {
+		ret = scm_call_atomic2(SCM_SVC_IO, SCM_IO_WRITE, address, val);
+	} else {
+		scm_arg.x0 = MAKE_SIP_SCM_CMD(SCM_SVC_IO, SCM_IO_WRITE);
+		scm_arg.x1 = MAKE_SCM_ARGS(0x2);
+		scm_arg.x2 = address;
+		scm_arg.x3 = val;
+		scm_arg.atomic = true;
+		ret = scm_call2(&scm_arg, &scm_ret);
+	}
+	return ret;
+}
+
+static int scm_call2_atomic(uint32_t svc, uint32_t cmd, uint32_t arg1, uint32_t arg2)
+{
+	uint32_t ret = 0;
+	scmcall_arg scm_arg = {0};
+	scmcall_ret scm_ret = {0};
+
+	if (!scm_arm_support)
+	{
+		ret = scm_call_atomic2(svc, cmd, arg1, arg2);
+	} else {
+		scm_arg.x0 = MAKE_SIP_SCM_CMD(svc, cmd);
+		scm_arg.x1 = MAKE_SCM_ARGS(0x2);
+		scm_arg.x2 = arg1;
+		scm_arg.x3 = arg2;
+		ret =  scm_call2(&scm_arg, &scm_ret);
+	}
+	return ret;
+}
+
+#if PLATFORM_USE_SCM_DLOAD
+int scm_dload_mode(int mode)
+{
+	int ret = 0;
+	uint32_t dload_type;
+
+	dprintf(SPEW, "DLOAD mode: %d\n", mode);
+	if (mode == NORMAL_DLOAD)
+		dload_type = SCM_DLOAD_MODE;
+	else if(mode == EMERGENCY_DLOAD)
+		dload_type = SCM_EDLOAD_MODE;
+	else
+		dload_type = 0;
+
+	/* Write to the Boot MISC register */
+	ret = scm_call2_atomic(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
+
+	if (ret) {
+		ret = scm_io_write(TCSR_BOOT_MISC_DETECT,dload_type);
+		if(ret) {
+			dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
+			return ret;
+		}
+	}
+
+	scm_check_boot_fuses();
+
+	/* Make WDOG_DEBUG DISABLE scm call only in non-secure boot */
+	if(!(secure_boot_enable || wdog_debug_fuse_disable)) {
+		ret = scm_call2_atomic(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
+		if(ret)
+			dprintf(CRITICAL, "Failed to disable the wdog debug \n");
+	}
+
+	return ret;
+}
+#endif
diff --git a/project/msm8909.mk b/project/msm8909.mk
index afc40f6..3eea90b 100644
--- a/project/msm8909.mk
+++ b/project/msm8909.mk
@@ -65,3 +65,6 @@
 ifeq ($(ENABLE_BOOT_CONFIG_SUPPORT),1)
 DEFINES += BOOT_CONFIG_SUPPORT=1
 endif
+
+#SCM call before entering DLOAD mode
+DEFINES += PLATFORM_USE_SCM_DLOAD=1
diff --git a/project/msm8916.mk b/project/msm8916.mk
index 5f51f80..2dff5df 100644
--- a/project/msm8916.mk
+++ b/project/msm8916.mk
@@ -51,3 +51,6 @@
 
 #enable user force reset feature
 DEFINES += USER_FORCE_RESET_SUPPORT=1
+
+#SCM call before entering DLOAD mode
+DEFINES += PLATFORM_USE_SCM_DLOAD=1
diff --git a/target/fsm9010/init.c b/target/fsm9010/init.c
index 7e47d47..e5c50bb 100644
--- a/target/fsm9010/init.c
+++ b/target/fsm9010/init.c
@@ -288,7 +288,10 @@
 	};
 
 	switch (platform) {
+	case FSM9008:
 	case FSM9010:
+	case FSM9016:
+	case FSM9055:
 		board->baseband = BASEBAND_MSM;
 		break;
 	default:
diff --git a/target/fsm9010/meminfo.c b/target/fsm9010/meminfo.c
index fa0f96a..3c1fc98 100644
--- a/target/fsm9010/meminfo.c
+++ b/target/fsm9010/meminfo.c
@@ -90,6 +90,6 @@
 
 unsigned target_get_max_flash_size(void)
 {
-	return (86 * 1024 * 1024);
+	return (222 * 1024 * 1024);
 }
 #endif /* DEVICE_TREE */
diff --git a/target/fsm9010/rules.mk b/target/fsm9010/rules.mk
index 17a1b1d..8e7fd48 100644
--- a/target/fsm9010/rules.mk
+++ b/target/fsm9010/rules.mk
@@ -12,7 +12,7 @@
 TAGS_ADDR        := BASE_ADDR+0x01e00000
 KERNEL_ADDR      := BASE_ADDR+0x00008000
 RAMDISK_ADDR     := BASE_ADDR+0x02000000
-SCRATCH_ADDR     := 0x0e000000
+SCRATCH_ADDR     := 0x32200000
 
 MODULES += \
 	dev/keys \
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 96232fe..7b055a5 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -378,30 +378,6 @@
 	return restart_reason;
 }
 
-static int scm_dload_mode(int mode)
-{
-	int ret = 0;
-	uint32_t dload_type;
-
-	dprintf(SPEW, "DLOAD mode: %d\n", mode);
-	if (mode == NORMAL_DLOAD)
-		dload_type = SCM_DLOAD_MODE;
-	else if(mode == EMERGENCY_DLOAD)
-		dload_type = SCM_EDLOAD_MODE;
-	else
-		dload_type = 0;
-
-	ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
-	if (ret)
-		dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
-
-	ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
-	if (ret)
-		dprintf(CRITICAL, "Failed to disable the wdog debug \n");
-
-	return ret;
-}
-
 /* Configure PMIC and Drop PS_HOLD for shutdown */
 void shutdown_device()
 {
diff --git a/target/msm8916/init.c b/target/msm8916/init.c
index fbc45e4..3bdd5ac 100644
--- a/target/msm8916/init.c
+++ b/target/msm8916/init.c
@@ -257,29 +257,6 @@
 	return hard_restart_reason;
 }
 
-static int scm_dload_mode(int mode)
-{
-	int ret = 0;
-	uint32_t dload_type;
-
-	dprintf(SPEW, "DLOAD mode: %d\n", mode);
-	if (mode == NORMAL_DLOAD)
-		dload_type = SCM_DLOAD_MODE;
-	else if(mode == EMERGENCY_DLOAD)
-		dload_type = SCM_EDLOAD_MODE;
-	else
-		dload_type = 0;
-
-	ret = scm_call_atomic2(SCM_SVC_BOOT, SCM_DLOAD_CMD, dload_type, 0);
-	if (ret)
-		dprintf(CRITICAL, "Failed to write to boot misc: %d\n", ret);
-
-	ret = scm_call_atomic2(SCM_SVC_BOOT, WDOG_DEBUG_DISABLE, 1, 0);
-	if (ret)
-		dprintf(CRITICAL, "Failed to disable the wdog debug \n");
-
-	return ret;
-}
 /* Configure PMIC and Drop PS_HOLD for shutdown */
 void shutdown_device()
 {
diff --git a/target/msm8916/oem_panel.c b/target/msm8916/oem_panel.c
index ae2725d..9e4349d 100644
--- a/target/msm8916/oem_panel.c
+++ b/target/msm8916/oem_panel.c
@@ -634,6 +634,9 @@
 				panel_id = JDI_1080P_VIDEO_PANEL;
 				break;
 			case 1:
+				panel_id = HX8394D_720P_VIDEO_PANEL;
+				break;
+			case 2:
 				panel_id = NT35590_720P_VIDEO_PANEL;
 				break;
 			default:
diff --git a/target/msm8916/target_display.c b/target/msm8916/target_display.c
index 0ddaec1..43a2903 100644
--- a/target/msm8916/target_display.c
+++ b/target/msm8916/target_display.c
@@ -62,33 +62,124 @@
 	mdelay(1);
 }
 
-static uint32_t dsi_pll_enable_seq_8916(uint32_t pll_base)
+static void dsi_pll_toggle_lock_detect_8916(uint32_t pll_base)
 {
-	uint32_t pll_locked = 0;
+	writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
+	udelay(1);
+	writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
+	udelay(512);
+}
 
+static void dsi_pll_sw_reset_8916(uint32_t pll_base)
+{
 	writel(0x01, pll_base + 0x0068); /* PLL TEST CFG */
 	udelay(1);
 	writel(0x00, pll_base + 0x0068); /* PLL TEST CFG */
+}
+
+static uint32_t gf_1_dsi_pll_enable_sequence_8916(uint32_t pll_base)
+{
+	uint32_t rc;
+
+	dsi_pll_sw_reset_8916(pll_base);
 
 	/*
 	 * Add hardware recommended delays between register writes for
 	 * the updates to take effect. These delays are necessary for the
 	 * PLL to successfully lock
 	 */
-	writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
-	udelay(1);
+	writel(0x14, pll_base + 0x0070); /* CAL CFG1*/
 	writel(0x01, pll_base + 0x0020); /* GLB CFG */
-	udelay(1);
 	writel(0x05, pll_base + 0x0020); /* GLB CFG */
-	udelay(1);
+	udelay(3);
 	writel(0x0f, pll_base + 0x0020); /* GLB CFG */
-	udelay(1);
+	udelay(500);
 
-	writel(0x04, pll_base + 0x0064); /* LKDetect CFG2 */
-	udelay(1);
-	writel(0x05, pll_base + 0x0064); /* LKDetect CFG2 */
-	udelay(512);
-	pll_locked = readl(pll_base + 0x00c0) & 0x01;
+	dsi_pll_toggle_lock_detect_8916(pll_base);
+	rc = readl(pll_base + 0x00c0) & 0x01;
+
+	return rc;
+}
+
+static uint32_t gf_2_dsi_pll_enable_sequence_8916(uint32_t pll_base)
+{
+	uint32_t rc;
+
+	dsi_pll_sw_reset_8916(pll_base);
+
+	/*
+	 * Add hardware recommended delays between register writes for
+	 * the updates to take effect. These delays are necessary for the
+	 * PLL to successfully lock
+	 */
+	writel(0x04, pll_base + 0x0070); /* CAL CFG1*/
+	writel(0x01, pll_base + 0x0020); /* GLB CFG */
+	writel(0x05, pll_base + 0x0020); /* GLB CFG */
+	udelay(3);
+	writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+	udelay(500);
+
+	dsi_pll_toggle_lock_detect_8916(pll_base);
+	rc = readl(pll_base + 0x00c0) & 0x01;
+
+	return rc;
+}
+
+static uint32_t tsmc_dsi_pll_enable_sequence_8916(uint32_t pll_base)
+{
+	uint32_t rc;
+
+	dsi_pll_sw_reset_8916(pll_base);
+	/*
+	 * Add hardware recommended delays between register writes for
+	 * the updates to take effect. These delays are necessary for the
+	 * PLL to successfully lock
+	 */
+
+	writel(0x34, pll_base + 0x0070); /* CAL CFG1*/
+	writel(0x01, pll_base + 0x0020); /* GLB CFG */
+	writel(0x05, pll_base + 0x0020); /* GLB CFG */
+	writel(0x0f, pll_base + 0x0020); /* GLB CFG */
+	udelay(500);
+
+	dsi_pll_toggle_lock_detect_8916(pll_base);
+	rc = readl(pll_base + 0x00c0) & 0x01;
+
+	return rc;
+}
+
+
+static uint32_t dsi_pll_enable_seq_8916(uint32_t pll_base)
+{
+	uint32_t pll_locked = 0;
+	uint32_t counter = 0;
+
+	do {
+		pll_locked = tsmc_dsi_pll_enable_sequence_8916(pll_base);
+
+		dprintf(SPEW, "TSMC pll locked status is %d\n", pll_locked);
+		++counter;
+	} while (!pll_locked && (counter < 3));
+
+	if(!pll_locked) {
+		counter = 0;
+		do {
+			pll_locked = gf_1_dsi_pll_enable_sequence_8916(pll_base);
+
+			dprintf(SPEW, "GF P1 pll locked status is %d\n", pll_locked);
+			++counter;
+		} while (!pll_locked && (counter < 3));
+	}
+
+	if(!pll_locked) {
+		counter = 0;
+		do {
+			pll_locked = gf_2_dsi_pll_enable_sequence_8916(pll_base);
+
+			dprintf(SPEW, "GF P2 pll locked status is %d\n", pll_locked);
+			++counter;
+		} while (!pll_locked && (counter < 3));
+	}
 
 	return pll_locked;
 }
diff --git a/target/msm8994/init.c b/target/msm8994/init.c
index 5df2874..6dc9ce9 100644
--- a/target/msm8994/init.c
+++ b/target/msm8994/init.c
@@ -446,9 +446,15 @@
 void reboot_device(unsigned reboot_reason)
 {
 	uint8_t reset_type = 0;
+	uint32_t restart_reason_addr;
+
+	if (platform_is_msm8994())
+		restart_reason_addr = RESTART_REASON_ADDR;
+	else
+		restart_reason_addr = RESTART_REASON_ADDR2;
 
 	/* Write the reboot reason */
-	writel(reboot_reason, RESTART_REASON_ADDR);
+	writel(reboot_reason, restart_reason_addr);
 
 	if(reboot_reason == FASTBOOT_MODE)
 		reset_type = PON_PSHOLD_WARM_RESET;
diff --git a/target/msm8994/regulator.c b/target/msm8994/regulator.c
index 8a8d1e1..c28afa2 100644
--- a/target/msm8994/regulator.c
+++ b/target/msm8994/regulator.c
@@ -35,15 +35,15 @@
 	{
 		LDOA_RES_TYPE, 2,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 0,
+		KEY_CURRENT, 4, 0,
 	},
 
 	{
 		LDOA_RES_TYPE, 2,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 1250000,
+		KEY_CURRENT, 4, 16,
 	},
 };
 
@@ -52,15 +52,15 @@
 	{
 		LDOA_RES_TYPE, 12,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 0,
+		KEY_CURRENT, 4, 0,
 	},
 
 	{
 		LDOA_RES_TYPE, 12,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 1800000,
+		KEY_CURRENT, 4, 11,
 	},
 };
 
@@ -69,32 +69,32 @@
 	{
 		LDOA_RES_TYPE, 14,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 0,
+		KEY_CURRENT, 4, 0,
 	},
 
 	{
 		LDOA_RES_TYPE, 14,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 1800000,
+		KEY_CURRENT, 4, 52,
 	},
 };
 
-static uint32_t ldo28[][11]=
+static uint32_t ldo28[][14]=
 {
 	{
 		LDOA_RES_TYPE, 28,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_DISABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 0,
+		KEY_CURRENT, 4, 0,
 	},
 
 	{
 		LDOA_RES_TYPE, 28,
 		KEY_SOFTWARE_ENABLE, 4, GENERIC_ENABLE,
-		KEY_LDO_SOFTWARE_MODE, 4, SW_MODE_LDO_IPEAK,
 		KEY_MICRO_VOLT, 4, 1000000,
+		KEY_CURRENT, 4, 72,
 	},
 
 };