commit d119ebc4b0e8567e0b00bf2d68cd29f31b47926e
author Unnati Gandhi <ugandhi@codeaurora.org> Tue Oct 14 03:41:46 2014 -0700
committer Aparna Mallavarapu <aparnam@codeaurora.org> Thu Oct 23 13:05:21 2014 -0700
tree b69f7fe2358549e0481ce519072f729ff61239d9
parent 5f80cbfdf54aea5b1e276161310750e8255786ad

platform: msm8909: Update UART to UART0

Add registers and update the clock names
to support UART0.

Change-Id: I9ae2a7ddb0d31c8255ff30592125cf66d9aeb195

platform/msm8909/include/platform/iomap.h

diff --git a/platform/msm8909/include/platform/iomap.h b/platform/msm8909/include/platform/iomap.h
index 024e53f..a44396d 100644
--- a/platform/msm8909/include/platform/iomap.h
+++ b/platform/msm8909/include/platform/iomap.h
@@ -143,6 +143,12 @@
 #define BLSP1_UART2_APPS_N          (CLK_CTL_BASE + 0x3040)
 #define BLSP1_UART2_APPS_D          (CLK_CTL_BASE + 0x3044)
 
+#define BLSP1_UART1_APPS_CBCR       (CLK_CTL_BASE + 0x203C)
+#define BLSP1_UART1_APPS_CMD_RCGR   (CLK_CTL_BASE + 0x2044)
+#define BLSP1_UART1_APPS_CFG_RCGR   (CLK_CTL_BASE + 0x2048)
+#define BLSP1_UART1_APPS_M          (CLK_CTL_BASE + 0x204C)
+#define BLSP1_UART1_APPS_N          (CLK_CTL_BASE + 0x2050)
+#define BLSP1_UART1_APPS_D          (CLK_CTL_BASE + 0x2054)
 
 /* USB */
 #define USB_HS_BCR                  (CLK_CTL_BASE + 0x41000)