[msm8x60] Add support for uart in 8660 bootloader.
Initialize and configure UART_DM in legacy mode (without
Data Mover) to support UARt in bootloader.
Features currently supported/unsupported:
- Legacy mode - no Data Mover
- Support RX/TX path
- No TX/RX Flow control
- Polling mechanism rather than Interrupt based
- Watchdog timeout not handled during long wait
Host Configuration:
Speed: 115200
Data bits: 8
Stop bits: 1
Parity: None
Flow control: None
CRs-fixed: 243843
Change-Id: I0296f77a40bf3e2f0e4040774a9820e836ca588e
diff --git a/platform/msm7k/platform.c b/platform/msm7k/platform.c
old mode 100755
new mode 100644
index a7d2746..6ce150c
--- a/platform/msm7k/platform.c
+++ b/platform/msm7k/platform.c
@@ -52,7 +52,7 @@
void platform_early_init(void)
{
//uart3_clock_init();
- uart_init();
+ //uart_init();
platform_init_interrupts();
platform_init_timer();
diff --git a/platform/msm8x60/platform.c b/platform/msm8x60/platform.c
index 6761390..4b65583 100644
--- a/platform/msm8x60/platform.c
+++ b/platform/msm8x60/platform.c
@@ -69,6 +69,7 @@
void platform_early_init(void)
{
+ uart_init();
platform_init_interrupts();
platform_init_timer();
}
diff --git a/platform/msm_shared/include/uart_dm.h b/platform/msm_shared/include/uart_dm.h
new file mode 100644
index 0000000..bf386c4
--- /dev/null
+++ b/platform/msm_shared/include/uart_dm.h
@@ -0,0 +1,273 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __UART_DM_H__
+#define __UART_DM_H__
+
+#define MSM_BOOT_UART_DM_EXTR_BITS(value, start_pos, end_pos) \
+ ((value << (32 - end_pos))\
+ >> (32 - (end_pos - start_pos)))
+
+/* GPIO pins - 2 wire using UART2 */
+#define MSM_BOOT_UART_DM_RX_GPIO 117
+#define MSM_BOOT_UART_DM_TX_GPIO 118
+
+
+/* UART Parity Mode */
+enum MSM_BOOT_UART_DM_PARITY_MODE
+{
+ MSM_BOOT_UART_DM_NO_PARITY,
+ MSM_BOOT_UART_DM_ODD_PARITY,
+ MSM_BOOT_UART_DM_EVEN_PARITY,
+ MSM_BOOT_UART_DM_SPACE_PARITY
+};
+
+/* UART Stop Bit Length */
+enum MSM_BOOT_UART_DM_STOP_BIT_LEN
+{
+ MSM_BOOT_UART_DM_SBL_9_16,
+ MSM_BOOT_UART_DM_SBL_1,
+ MSM_BOOT_UART_DM_SBL_1_9_16,
+ MSM_BOOT_UART_DM_SBL_2
+};
+
+/* UART Bits per Char */
+enum MSM_BOOT_UART_DM_BITS_PER_CHAR
+{
+ MSM_BOOT_UART_DM_5_BPS,
+ MSM_BOOT_UART_DM_6_BPS,
+ MSM_BOOT_UART_DM_7_BPS,
+ MSM_BOOT_UART_DM_8_BPS
+};
+
+/* 8-N-1 Configuration */
+#define MSM_BOOT_UART_DM_8_N_1_MODE (MSM_BOOT_UART_DM_NO_PARITY | \
+ (MSM_BOOT_UART_DM_SBL_1 << 2) | \
+ (MSM_BOOT_UART_DM_8_BPS << 4))
+
+/* CSR is used to further divide fundamental frequency.
+ * Using EE we are dividing gsbi_uart_clk by 2 so as to get
+ * 115.2k bit rate for fundamental frequency of 3.6864 MHz */
+#define MSM_BOOT_UART_DM_RX_TX_BIT_RATE 0xEE
+
+/*
+ * Define Macros for GSBI and UARTDM Registers
+ */
+
+/* Clocks */
+
+#define MSM_BOOT_CLK_CTL_BASE 0x00900000
+
+#define MSM_BOOT_PLL_ENABLE_SC0 (MSM_BOOT_CLK_CTL_BASE + 0x34C0)
+
+#define MSM_BOOT_PLL8_STATUS (MSM_BOOT_CLK_CTL_BASE + 0x3158)
+
+#define MSM_BOOT_GSBIn_HCLK_CTL(n) (MSM_BOOT_CLK_CTL_BASE + 0x29A0 +\
+ ( 32 * n ))
+
+#define MSM_BOOT_GSBIn_UART_APPS_MD(n) (MSM_BOOT_CLK_CTL_BASE + 0x29B0 +\
+ ( 32 * n))
+
+#define MSM_BOOT_GSBIn_UART_APPS_NS(n) (MSM_BOOT_CLK_CTL_BASE + 0x29B4 +\
+ (32 * n))
+
+#define MSM_BOOT_UART_DM_GSBI_HCLK_CTL MSM_BOOT_GSBIn_HCLK_CTL(12)
+
+#define MSM_BOOT_UART_DM_APPS_MD MSM_BOOT_GSBIn_UART_APPS_MD(12)
+
+#define MSM_BOOT_UART_DM_APPS_NS MSM_BOOT_GSBIn_UART_APPS_NS(12)
+
+
+/* Using GSBI12 for UART */
+#define MSM_BOOT_GSBI_BASE 0x19C00000
+
+#define MSM_BOOT_GSBI_CTRL_REG MSM_BOOT_GSBI_BASE
+
+#define MSM_BOOT_UART_DM_BASE (MSM_BOOT_GSBI_BASE+0x40000)
+
+#define MSM_BOOT_UART_DM_REG(offset) (MSM_BOOT_UART_DM_BASE + offset)
+
+/* UART Operational Mode Register */
+#define MSM_BOOT_UART_DM_MR1 MSM_BOOT_UART_DM_REG(0x0000)
+#define MSM_BOOT_UART_DM_MR2 MSM_BOOT_UART_DM_REG(0x0004)
+#define MSM_BOOT_UART_DM_RXBRK_ZERO_CHAR_OFF (1 << 8)
+#define MSM_BOOT_UART_DM_LOOPBACK (1 << 7)
+
+/* UART Clock Selection Register */
+#define MSM_BOOT_UART_DM_CSR MSM_BOOT_UART_DM_REG(0x0008)
+
+/* UART DM TX FIFO Registers - 4 */
+#define MSM_BOOT_UART_DM_TF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
+
+/* UART Command Register */
+#define MSM_BOOT_UART_DM_CR MSM_BOOT_UART_DM_REG(0x0010)
+#define MSM_BOOT_UART_DM_CR_RX_ENABLE (1 << 0)
+#define MSM_BOOT_UART_DM_CR_RX_DISABLE (1 << 1)
+#define MSM_BOOT_UART_DM_CR_TX_ENABLE (1 << 2)
+#define MSM_BOOT_UART_DM_CR_TX_DISABLE (1 << 3)
+
+/* UART Channel Command */
+#define MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4)
+#define MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 )
+#define MSM_BOOT_UART_DM_CR_CH_CMD(x) (MSM_BOOT_UART_DM_CR_CH_CMD_LSB(x) | \
+ MSM_BOOT_UART_DM_CR_CH_CMD_MSB(x))
+#define MSM_BOOT_UART_DM_CMD_NULL MSM_BOOT_UART_DM_CR_CH_CMD(0)
+#define MSM_BOOT_UART_DM_CMD_RESET_RX MSM_BOOT_UART_DM_CR_CH_CMD(1)
+#define MSM_BOOT_UART_DM_CMD_RESET_TX MSM_BOOT_UART_DM_CR_CH_CMD(2)
+#define MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT MSM_BOOT_UART_DM_CR_CH_CMD(3)
+#define MSM_BOOT_UART_DM_CMD_RES_BRK_CHG_INT MSM_BOOT_UART_DM_CR_CH_CMD(4)
+#define MSM_BOOT_UART_DM_CMD_START_BRK MSM_BOOT_UART_DM_CR_CH_CMD(5)
+#define MSM_BOOT_UART_DM_CMD_STOP_BRK MSM_BOOT_UART_DM_CR_CH_CMD(6)
+#define MSM_BOOT_UART_DM_CMD_RES_CTS_N MSM_BOOT_UART_DM_CR_CH_CMD(7)
+#define MSM_BOOT_UART_DM_CMD_RES_STALE_INT MSM_BOOT_UART_DM_CR_CH_CMD(8)
+#define MSM_BOOT_UART_DM_CMD_PACKET_MODE MSM_BOOT_UART_DM_CR_CH_CMD(9)
+#define MSM_BOOT_UART_DM_CMD_MODE_RESET MSM_BOOT_UART_DM_CR_CH_CMD(C)
+#define MSM_BOOT_UART_DM_CMD_SET_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(D)
+#define MSM_BOOT_UART_DM_CMD_RES_RFR_N MSM_BOOT_UART_DM_CR_CH_CMD(E)
+#define MSM_BOOT_UART_DM_CMD_RES_TX_ERR MSM_BOOT_UART_DM_CR_CH_CMD(10)
+#define MSM_BOOT_UART_DM_CMD_CLR_TX_DONE MSM_BOOT_UART_DM_CR_CH_CMD(11)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKSTRT_INT MSM_BOOT_UART_DM_CR_CH_CMD(12)
+#define MSM_BOOT_UART_DM_CMD_RES_BRKEND_INT MSM_BOOT_UART_DM_CR_CH_CMD(13)
+#define MSM_BOOT_UART_DM_CMD_RES_PER_FRM_INT MSM_BOOT_UART_DM_CR_CH_CMD(14)
+
+/*UART General Command */
+#define MSM_BOOT_UART_DM_CR_GENERAL_CMD(x) ((x) << 8)
+
+#define MSM_BOOT_UART_DM_GCMD_NULL MSM_BOOT_UART_DM_CR_GENERAL_CMD(0)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_EN MSM_BOOT_UART_DM_CR_GENERAL_CMD(1)
+#define MSM_BOOT_UART_DM_GCMD_CR_PROT_DIS MSM_BOOT_UART_DM_CR_GENERAL_CMD(2)
+#define MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT MSM_BOOT_UART_DM_CR_GENERAL_CMD(3)
+#define MSM_BOOT_UART_DM_GCMD_SW_FORCE_STALE MSM_BOOT_UART_DM_CR_GENERAL_CMD(4)
+#define MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(5)
+#define MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT MSM_BOOT_UART_DM_CR_GENERAL_CMD(6)
+
+/* UART Interrupt Mask Register */
+#define MSM_BOOT_UART_DM_IMR MSM_BOOT_UART_DM_REG(0x0014)
+#define MSM_BOOT_UART_DM_TXLEV (1 << 0)
+#define MSM_BOOT_UART_DM_RXHUNT (1 << 1)
+#define MSM_BOOT_UART_DM_RXBRK_CHNG (1 << 2)
+#define MSM_BOOT_UART_DM_RXSTALE (1 << 3)
+#define MSM_BOOT_UART_DM_RXLEV (1 << 4)
+#define MSM_BOOT_UART_DM_DELTA_CTS (1 << 5)
+#define MSM_BOOT_UART_DM_CURRENT_CTS (1 << 6)
+#define MSM_BOOT_UART_DM_TX_READY (1 << 7)
+#define MSM_BOOT_UART_DM_TX_ERROR (1 << 8)
+#define MSM_BOOT_UART_DM_TX_DONE (1 << 9)
+#define MSM_BOOT_UART_DM_RXBREAK_START (1 << 10)
+#define MSM_BOOT_UART_DM_RXBREAK_END (1 << 11)
+#define MSM_BOOT_UART_DM_PAR_FRAME_ERR_IRQ (1 << 12)
+
+#define MSM_BOOT_UART_DM_IMR_ENABLED (MSM_BOOT_UART_DM_TX_READY | \
+ MSM_BOOT_UART_DM_TXLEV | \
+ MSM_BOOT_UART_DM_RXLEV | \
+ MSM_BOOT_UART_DM_RXSTALE)
+
+/* UART Interrupt Programming Register */
+#define MSM_BOOT_UART_DM_IPR MSM_BOOT_UART_DM_REG(0x0018)
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB 0x0f
+#define MSM_BOOT_UART_DM_STALE_TIMEOUT_MSB 0 /* Not used currently */
+
+/* UART Transmit/Receive FIFO Watermark Register */
+#define MSM_BOOT_UART_DM_TFWR MSM_BOOT_UART_DM_REG(0x001C)
+/* Interrupt is generated when FIFO level is less than or equal to this value */
+#define MSM_BOOT_UART_DM_TFW_VALUE 0
+
+#define MSM_BOOT_UART_DM_RFWR MSM_BOOT_UART_DM_REG(0x0020)
+/*Interrupt generated when no of words in RX FIFO is greater than this value */
+#define MSM_BOOT_UART_DM_RFW_VALUE 0
+
+/* UART Hunt Character Register */
+#define MSM_BOOT_UART_DM_HCR MSM_BOOT_UART_DM_REG(0x0024)
+
+/* Used for RX transfer initialization */
+#define MSM_BOOT_UART_DM_DMRX MSM_BOOT_UART_DM_REG(0x0034)
+
+/* Default DMRX value - any value bigger than FIFO size would be fine */
+#define MSM_BOOT_UART_DM_DMRX_DEF_VALUE 0x220
+
+/* Register to enable IRDA function */
+#define MSM_BOOT_UART_DM_IRDA MSM_BOOT_UART_DM_REG(0x0038)
+
+/* UART Data Mover Enable Register */
+#define MSM_BOOT_UART_DM_DMEN MSM_BOOT_UART_DM_REG(0x003C)
+
+/* Number of characters for Transmission */
+#define MSM_BOOT_UART_DM_NO_CHARS_FOR_TX MSM_BOOT_UART_DM_REG(0x0040)
+
+/* UART RX FIFO Base Address */
+#define MSM_BOOT_UART_DM_BADR MSM_BOOT_UART_DM_REG(0x0044)
+
+/* UART Status Register */
+#define MSM_BOOT_UART_DM_SR MSM_BOOT_UART_DM_REG(0x0008)
+#define MSM_BOOT_UART_DM_SR_RXRDY (1 << 0)
+#define MSM_BOOT_UART_DM_SR_RXFULL (1 << 1)
+#define MSM_BOOT_UART_DM_SR_TXRDY (1 << 2)
+#define MSM_BOOT_UART_DM_SR_TXEMT (1 << 3)
+#define MSM_BOOT_UART_DM_SR_UART_OVERRUN (1 << 4)
+#define MSM_BOOT_UART_DM_SR_PAR_FRAME_ERR (1 << 5)
+#define MSM_BOOT_UART_DM_RX_BREAK (1 << 6)
+#define MSM_BOOT_UART_DM_HUNT_CHAR (1 << 7)
+#define MSM_BOOT_UART_DM_RX_BRK_START_LAST (1 << 8)
+
+/* UART Receive FIFO Registers - 4 in numbers */
+#define MSM_BOOT_UART_DM_RF(x) MSM_BOOT_UART_DM_REG(0x0070+(4*x))
+
+/* UART Masked Interrupt Status Register */
+#define MSM_BOOT_UART_DM_MISR MSM_BOOT_UART_DM_REG(0x0010)
+
+/* UART Interrupt Status Register */
+#define MSM_BOOT_UART_DM_ISR MSM_BOOT_UART_DM_REG(0x0014)
+
+/* Number of characters received since the end of last RX transfer */
+#define MSM_BOOT_UART_DM_RX_TOTAL_SNAP MSM_BOOT_UART_DM_REG(0x0038)
+
+/* UART TX FIFO Status Register */
+#define MSM_BOOT_UART_DM_TXFS MSM_BOOT_UART_DM_REG(0x004C)
+#define MSM_BOOT_UART_DM_TXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
+#define MSM_BOOT_UART_DM_TXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
+#define MSM_BOOT_UART_DM_TXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
+#define MSM_BOOT_UART_DM_TXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
+
+/* UART RX FIFO Status Register */
+#define MSM_BOOT_UART_DM_RXFS MSM_BOOT_UART_DM_REG(0x0050)
+#define MSM_BOOT_UART_DM_RXFS_STATE_LSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,0,6)
+#define MSM_BOOT_UART_DM_RXFS_STATE_MSB(x) MSM_BOOT_UART_DM_EXTR_BITS(x,14,31)
+#define MSM_BOOT_UART_DM_RXFS_BUF_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,7,9)
+#define MSM_BOOT_UART_DM_RXFS_ASYNC_STATE(x) MSM_BOOT_UART_DM_EXTR_BITS(x,10,13)
+
+
+
+/* Macros for Common Errors */
+#define MSM_BOOT_UART_DM_E_SUCCESS 0
+#define MSM_BOOT_UART_DM_E_FAILURE 1
+#define MSM_BOOT_UART_DM_E_TIMEOUT 2
+#define MSM_BOOT_UART_DM_E_INVAL 3
+#define MSM_BOOT_UART_DM_E_MALLOC_FAIL 4
+#define MSM_BOOT_UART_DM_E_RX_NOT_READY 5
+
+#endif /* __UART_DM_H__*/
diff --git a/platform/msm_shared/rules.mk b/platform/msm_shared/rules.mk
index b1795ea..394b2f3 100644
--- a/platform/msm_shared/rules.mk
+++ b/platform/msm_shared/rules.mk
@@ -7,7 +7,6 @@
DEFINES += $(TARGET_YRES)
OBJS += \
- $(LOCAL_DIR)/uart.o \
$(LOCAL_DIR)/timer.o \
$(LOCAL_DIR)/proc_comm.o \
$(LOCAL_DIR)/debug.o \
@@ -25,4 +24,8 @@
OBJS += $(LOCAL_DIR)/i2c_qup.o
endif
-
+ifeq ($(PLATFORM),msm8x60)
+ OBJS += $(LOCAL_DIR)/uart_dm.o
+else
+ OBJS += $(LOCAL_DIR)/uart.o
+endif
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
new file mode 100644
index 0000000..9e06cd0
--- /dev/null
+++ b/platform/msm_shared/uart_dm.c
@@ -0,0 +1,526 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <string.h>
+#include <stdlib.h>
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/irqs.h>
+#include <platform/interrupts.h>
+#include <platform/gpio_hw.h>
+#include <dev/uart.h>
+#include "uart_dm.h"
+
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+/* Note:
+ * This is a basic implementation of UART_DM protocol. More focus has been
+ * given on simplicity than efficiency. Few of the things to be noted are:
+ * - RX path may not be suitable for multi-threaded scenaraio because of the
+ * use of static variables. TX path shouldn't have any problem though. If
+ * multi-threaded support is required, a simple data-structure can
+ * be maintained for each thread.
+ * - Right now we are using polling method than interrupt based.
+ * - We are using legacy UART protocol without Data Mover.
+ * - Not all interrupts and error events are handled.
+ * - While waiting Watchdog hasn't been taken into consideration.
+ */
+
+
+#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \
+ word = 0; \
+ for(int j=0; j < (int)cnt; j++) \
+ { \
+ word |= (a[j] & 0xff) \
+ << (j * 8); \
+ } \
+ }
+
+
+/* Static Function Prototype Declarations */
+static unsigned int msm_boot_uart_config_gpios(void);
+static unsigned int msm_boot_uart_dm_config_clock(void);
+static unsigned int msm_boot_uart_dm_gsbi_init(void);
+static unsigned int msm_boot_uart_replace_lr_with_cr(char* data_in,
+ int num_of_chars,
+ char *data_out,
+ int *num_of_chars_out);
+static unsigned int msm_boot_uart_dm_init(void);
+static unsigned int msm_boot_uart_dm_read(unsigned int* data,
+ int wait);
+static unsigned int msm_boot_uart_dm_write(char* data,
+ unsigned int num_of_chars);
+static unsigned int msm_boot_uart_dm_init_rx_transfer(void);
+static unsigned int msm_boot_uart_dm_reset(void);
+
+
+/* Extern functions */
+void clock_config(unsigned int ns, unsigned int md,
+ unsigned int ns_addr, unsigned int md_addr);
+
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable );
+
+void udelay(unsigned usecs);
+
+
+/*
+ * Helper function to replace Line Feed char "\n" with
+ * Carriage Return "\r\n".
+ * Currently keeping it simple than efficient
+ */
+static unsigned int msm_boot_uart_replace_lr_with_cr(char* data_in,
+ int num_of_chars,
+ char *data_out,
+ int *num_of_chars_out )
+{
+ int i = 0, j = 0;
+
+ if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0))
+ {
+ return MSM_BOOT_UART_DM_E_INVAL;
+ }
+
+ for (i=0, j=0; i < num_of_chars; i++, j++)
+ {
+ if ( data_in[i] == '\n' )
+ {
+ data_out[j++] = '\r';
+ }
+
+ data_out[j] = data_in[i];
+ }
+
+ *num_of_chars_out = j;
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+
+static unsigned int msm_boot_uart_dm_config_gpios(void)
+{
+ /* GPIO Pin: MSM_BOOT_UART_DM_RX_GPIO (117)
+ Function: 2
+ Direction: IN
+ Pull: No PULL
+ Drive Strength: 8 ma
+ Output Enable: Disable
+ */
+ gpio_tlmm_config(MSM_BOOT_UART_DM_RX_GPIO, 2, GPIO_INPUT,
+ GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+
+ /* GPIO Pin: MSM_BOOT_UART_DM_TX_GPIO (118)
+ Function: 2
+ Direction: OUT
+ Pull: No PULL
+ Drive Strength: 8 ma
+ Output Enable: Disable
+ */
+ gpio_tlmm_config(MSM_BOOT_UART_DM_TX_GPIO, 2, GPIO_OUTPUT,
+ GPIO_NO_PULL, GPIO_8MA, GPIO_DISABLE);
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+
+
+static unsigned int msm_boot_uart_dm_config_clock(void)
+{
+ unsigned int curr_value = 0;
+
+ /* Vote for PLL8 to be enabled */
+ curr_value = readl(MSM_BOOT_PLL_ENABLE_SC0);
+ curr_value |= (1 << 8);
+ writel(curr_value, MSM_BOOT_PLL_ENABLE_SC0);
+
+ /* Proceed only after PLL is enabled */
+ while (!(readl(MSM_BOOT_PLL8_STATUS) & (1<<16)));
+
+ /* PLL8 is enabled. Enable gsbi_uart_clk */
+
+ /* GSBI clock frequencies for UART protocol
+ * Operating mode gsbi_uart_clk
+ * UART up to 115.2 Kbps 1.8432 MHz
+ * UART up to 460.8 Kbps 7.3728 MHz
+ * UART up to 4 Mbit/s 64 MHz
+ *
+
+ * Choosing lowest supported value
+ * Rate (KHz) NS MD
+ * 3686400 0xFD940043 0x0006FD8E
+ */
+
+ clock_config(0xFD940043, 0x0006FD8E,
+ MSM_BOOT_UART_DM_APPS_NS,
+ MSM_BOOT_UART_DM_APPS_MD);
+
+ /* Enable gsbi_pclk */
+ writel(0x10, MSM_BOOT_UART_DM_GSBI_HCLK_CTL);
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+
+/*
+ * Initialize and configure GSBI for operation
+ */
+static unsigned int msm_boot_uart_dm_gsbi_init(void)
+{
+ /* Configure the clock block */
+ msm_boot_uart_dm_config_clock();
+
+ /* Configure TLMM/GPIO to provide connectivity between GSBI
+ product ports and chip pads */
+ msm_boot_uart_dm_config_gpios();
+
+
+ /* Configure Data Mover for GSBI operation.
+ * Currently not supported. */
+
+ /* Configure GSBI for UART_DM protocol.
+ * I2C on 2 ports, UART (without HS flow control) on the other 2. */
+ writel(0x60, MSM_BOOT_GSBI_CTRL_REG);
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * Reset the UART
+ */
+static unsigned int msm_boot_uart_dm_reset(void)
+{
+ writel(MSM_BOOT_UART_DM_CMD_RESET_RX, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_TX, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RES_TX_ERR, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR);
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+
+/*
+ * Initialize UART_DM - configure clock and required registers.
+ */
+static unsigned int msm_boot_uart_dm_init(void)
+{
+ /* Configure GSB12 for uart dm */
+ msm_boot_uart_dm_gsbi_init();
+
+
+ /* Configure clock selection register for tx and rx rates.
+ * Selecting 115.2k for both RX and TX */
+ writel(MSM_BOOT_UART_DM_RX_TX_BIT_RATE, MSM_BOOT_UART_DM_CSR);
+
+ /* Configure UART mode registers MR1 and MR2 */
+ /* Hardware flow control isn't supported */
+ writel(0x0, MSM_BOOT_UART_DM_MR1);
+
+ /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
+ writel(MSM_BOOT_UART_DM_8_N_1_MODE, MSM_BOOT_UART_DM_MR2);
+
+ /* Configure Interrupt Mask register IMR */
+ writel(MSM_BOOT_UART_DM_IMR_ENABLED, MSM_BOOT_UART_DM_IMR);
+
+ /* Configure Tx and Rx watermarks configuration registers */
+ /* TX watermark value is set to 0 - interrupt is generated when
+ * FIFO level is less than or equal to 0 */
+ writel(MSM_BOOT_UART_DM_TFW_VALUE, MSM_BOOT_UART_DM_TFWR);
+
+ /* RX watermark value*/
+ writel(MSM_BOOT_UART_DM_RFW_VALUE, MSM_BOOT_UART_DM_RFWR);
+
+ /* Configure Interrupt Programming Register*/
+ /* Set initial Stale timeout value*/
+ writel(MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB, MSM_BOOT_UART_DM_IPR);
+
+ /* Configure IRDA if required */
+ /* Disabling IRDA mode */
+ writel(0x0, MSM_BOOT_UART_DM_IRDA);
+
+ /* Configure and enable sim interface if required */
+
+ /* Configure hunt character value in HCR register */
+ /* Keep it in reset state */
+ writel(0x0, MSM_BOOT_UART_DM_HCR);
+
+ /* Configure Rx FIFO base address */
+ /* Both TX/RX shares same SRAM and default is half-n-half.
+ * Sticking with default value now.
+ * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
+ * We have found RAM_ADDR_WIDTH = 0x7f */
+
+ /* Issue soft reset command */
+ msm_boot_uart_dm_reset();
+
+ /* Enable/Disable Rx/Tx DM interfaces */
+ /* Data Mover not currently utilized. */
+ writel(0x0, MSM_BOOT_UART_DM_DMEN);
+
+
+ /* Enable transmitter and receiver */
+ writel(MSM_BOOT_UART_DM_CR_RX_ENABLE, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CR_TX_ENABLE, MSM_BOOT_UART_DM_CR);
+
+ /* Initialize Receive Path */
+ msm_boot_uart_dm_init_rx_transfer();
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+
+/*
+ * Initialize Receive Path
+ */
+static unsigned int msm_boot_uart_dm_init_rx_transfer(void)
+{
+ writel(MSM_BOOT_UART_DM_GCMD_DIS_STALE_EVT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR);
+ writel(MSM_BOOT_UART_DM_DMRX_DEF_VALUE, MSM_BOOT_UART_DM_DMRX);
+ writel(MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT, MSM_BOOT_UART_DM_CR);
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+/*
+ * UART Receive operation
+ * Reads a word from the RX FIFO.
+ */
+static unsigned int msm_boot_uart_dm_read(unsigned int* data, int wait)
+{
+ static int rx_last_snap_count = 0;
+ static int rx_chars_read_since_last_xfer = 0;
+
+ if (data == NULL)
+ {
+ return MSM_BOOT_UART_DM_E_INVAL;
+ }
+
+
+
+ /* We will be polling RXRDY status bit */
+ while (!(readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_RXRDY))
+ {
+ /* if this is not a blocking call, we'll just return */
+ if (!wait)
+ {
+ return MSM_BOOT_UART_DM_E_RX_NOT_READY;
+ }
+ }
+
+ /* Check for Overrun error. We'll just reset Error Status */
+ if (readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_UART_OVERRUN)
+ {
+ writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT, MSM_BOOT_UART_DM_CR);
+ }
+
+ /* RX FIFO is ready; read a word. */
+ *data = readl(MSM_BOOT_UART_DM_RF(0));
+
+ /* increment the total count of chars we've read so far */
+ rx_chars_read_since_last_xfer += 4;
+
+ /* Rx transfer ends when one of the conditions is met:
+ * - The number of characters received since the end of the previous xfer
+ * equals the value written to DMRX at Transfer Initialization
+ * - A stale event occurred
+ */
+
+ /* If RX transfer has not ended yet */
+ if (rx_last_snap_count == 0)
+ {
+ /* Check if we've received stale event */
+ if (readl(MSM_BOOT_UART_DM_MISR) & MSM_BOOT_UART_DM_RXSTALE)
+ {
+ /* Send command to reset stale interrupt */
+ writel(MSM_BOOT_UART_DM_CMD_RES_STALE_INT, MSM_BOOT_UART_DM_CR);
+ }
+
+ /* Check if we haven't read more than DMRX value */
+ else if ((unsigned int)rx_chars_read_since_last_xfer <
+ readl(MSM_BOOT_UART_DM_DMRX))
+ {
+ /* We can still continue reading before initializing RX transfer */
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+ }
+
+ /* If we've reached here it means RX xfer end conditions been met */
+
+ /* Read UART_DM_RX_TOTAL_SNAP register to know how many valid chars
+ * we've read so far since last transfer */
+ rx_last_snap_count = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP);
+
+ }
+
+ /* If there are still data left in FIFO we'll read them before
+ * initializing RX Transfer again */
+ if ((rx_last_snap_count - rx_chars_read_since_last_xfer) >= 0 )
+ {
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+ }
+
+ msm_boot_uart_dm_init_rx_transfer();
+ rx_last_snap_count = 0;
+ rx_chars_read_since_last_xfer = 0;
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+
+/*
+ * UART transmit operation
+ */
+static unsigned int msm_boot_uart_dm_write(char* data,
+ unsigned int num_of_chars)
+{
+ unsigned int tx_word_count = 0;
+ unsigned int tx_char_left = 0, tx_char = 0;
+ unsigned int tx_word = 0;
+ int i = 0;
+ char* tx_data = NULL;
+ char new_data[1024];
+
+ if ((data == NULL) || (num_of_chars <= 0))
+ {
+ return MSM_BOOT_UART_DM_E_INVAL;
+ }
+
+ /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */
+
+ msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i);
+
+ tx_data = new_data;
+ num_of_chars = i;
+
+ /* Write to NO_CHARS_FOR_TX register number of characters
+ * to be transmitted. However, before writing TX_FIFO must
+ * be empty as indicated by TX_READY interrupt in IMR register
+ */
+
+ /* Check if transmit FIFO is empty.
+ * If not we'll wait for TX_READY interrupt. */
+ if (!(readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_TXEMT))
+ {
+ while (!(readl(MSM_BOOT_UART_DM_ISR) & MSM_BOOT_UART_DM_TX_READY))
+ {
+ udelay(1);
+ /* Kick watchdog? */
+ }
+ }
+
+ /* We are here. FIFO is ready to be written. */
+ /* Write number of characters to be written */
+ writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX);
+
+ /* Clear TX_READY interrupt */
+ writel(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, MSM_BOOT_UART_DM_CR);
+
+ /* We use four-character word FIFO. So we need to divide data into
+ * four characters and write in UART_DM_TF register */
+ tx_word_count = (num_of_chars % 4)? ((num_of_chars / 4) + 1) :
+ (num_of_chars / 4);
+ tx_char_left = num_of_chars;
+
+ for (i = 0; i < (int)tx_word_count; i++)
+ {
+ tx_char = (tx_char_left < 4)? tx_char_left : 4;
+ PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word);
+
+ /* Wait till TX FIFO has space */
+ while (!(readl(MSM_BOOT_UART_DM_SR) & MSM_BOOT_UART_DM_SR_TXRDY))
+ {
+ udelay(1);
+ }
+
+ /* TX FIFO has space. Write the chars */
+ writel(tx_word, MSM_BOOT_UART_DM_TF(0));
+ tx_char_left = num_of_chars - (i+1)*4;
+ tx_data = tx_data + 4;
+ }
+
+ return MSM_BOOT_UART_DM_E_SUCCESS;
+}
+
+
+/* Defining functions that's exposed to outside world and in coformance to
+ * existing uart implemention. These functions are being called to initialize
+ * UART and print debug messages in bootloader. */
+
+void uart_init(void)
+{
+ char *data = "Android Bootloader - UART_DM Initialized!!!\n";
+
+ msm_boot_uart_dm_init();
+ msm_boot_uart_dm_write(data, 44);
+
+}
+
+/* UART_DM uses four character word FIFO where as UART core
+ * uses a character FIFO. so it's really inefficient to try
+ * to write single character. But that's how dprintf has been
+ * implemented.
+ */
+int uart_putc(int port, char c)
+{
+
+ msm_boot_uart_dm_write(&c, 1);
+
+ return 0;
+}
+
+/* UART_DM uses four character word FIFO whereas uart_getc
+ * is supposed to read only one character. So we need to
+ * read a word and keep track of each character in the word.
+ */
+int uart_getc(int port, bool wait)
+{
+ int byte;
+ static unsigned int word = 0;
+
+ if (!word)
+ {
+ /* Read from FIFO only if it's a first read or all the four
+ * characters out of a word have been read */
+ if (msm_boot_uart_dm_read( &word, wait) != MSM_BOOT_UART_DM_E_SUCCESS)
+ {
+ return -1;
+ }
+
+ }
+
+ byte = (int) word & 0xff;
+ word = word >> 8;
+
+ return byte;
+}
+
diff --git a/platform/qsd8650a/platform.c b/platform/qsd8650a/platform.c
index 9fb28ef..5a64ca0 100644
--- a/platform/qsd8650a/platform.c
+++ b/platform/qsd8650a/platform.c
@@ -46,7 +46,7 @@
void platform_early_init(void)
{
//uart3_clock_init();
- uart_init();
+ //uart_init();
platform_init_interrupts();
platform_init_timer();
diff --git a/platform/qsd8k/platform.c b/platform/qsd8k/platform.c
index 1ba0d8a..c0d4e5e 100644
--- a/platform/qsd8k/platform.c
+++ b/platform/qsd8k/platform.c
@@ -49,7 +49,7 @@
void platform_early_init(void)
{
//uart3_clock_init();
- uart_init();
+ //uart_init();
platform_init_interrupts();
platform_init_timer();