diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c
index a8dec50..61e7cb4 100644
--- a/dev/fbcon/fbcon.c
+++ b/dev/fbcon/fbcon.c
@@ -226,6 +226,10 @@
 		    SPLASH_IMAGE_HEIGHT * bytes_per_bpp);
 	}
     }
+    fbcon_flush();
+    if(is_cmd_mode_enabled())
+        mipi_dsi_cmd_mode_trigger();
+
 #else
     if (bytes_per_bpp == 2)
     {
@@ -236,7 +240,6 @@
 		    SPLASH_IMAGE_HEIGHT * bytes_per_bpp);
 	}
     }
-#endif
-
     fbcon_flush();
+#endif
 }
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index f6c7e73..1849ec8 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -33,6 +33,10 @@
 #define PASS                        0
 #define FAIL                        1
 
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+#define MIPI_DSI_BASE                         (0x04700000)
+
 #define DSI_CLKOUT_TIMING_CTRL                (0x047000C0)
 #define MMSS_DSI_PIXEL_MD                     (0x04000134)
 #define MMSS_DSI_PIXEL_NS                     (0x04000138)
@@ -100,9 +104,14 @@
 #define DSI_TRIG_CTRL                         (0x04700080)
 #define DSI_CTRL                              (0x04700000)
 #define DSI_COMMAND_MODE_DMA_CTRL             (0x04700038)
+#define DSI_COMMAND_MODE_MDP_CTRL             (0x0470003C)
+#define DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL     (0x04700040)
 #define DSI_DMA_CMD_OFFSET                    (0x04700044)
 #define DSI_DMA_CMD_LENGTH                    (0x04700048)
-#define DSI_COMMAND_MODE_DMA_CTRL             (0x04700038)
+#define DSI_COMMAND_MODE_MDP_STREAM0_CTRL     (0x04700054)
+#define DSI_COMMAND_MODE_MDP_STREAM0_TOTAL    (0x04700058)
+#define DSI_COMMAND_MODE_MDP_STREAM1_CTRL     (0x0470005C)
+#define DSI_COMMAND_MODE_MDP_STREAM1_TOTAL    (0x04700060)
 #define DSI_ERR_INT_MASK0                     (0x04700108)
 #define DSI_INT_CTRL                          (0x0470010C)
 
@@ -113,16 +122,24 @@
 #define DSI_VIDEO_MODE_VSYNC                  (0x04700030)
 #define DSI_VIDEO_MODE_VSYNC_VPOS             (0x04700034)
 
+#define DSI_MISR_CMD_CTRL                     (0x0470009C)
 #define DSI_MISR_VIDEO_CTRL                   (0x047000A0)
 #define DSI_EOT_PACKET_CTRL                   (0x047000C8)
 #define DSI_VIDEO_MODE_CTRL                   (0x0470000C)
 #define DSI_CAL_STRENGTH_CTRL                 (0x04700100)
 #define DSI_CMD_MODE_DMA_SW_TRIGGER           (0x0470008C)
+#define DSI_CMD_MODE_MDP_SW_TRIGGER           (0x04700090)
 
+#define MDP_OVERLAYPROC0_START                (0x05100004)
+#define MDP_DMA_P_START                       (0x0510000C)
+#define MDP_DMA_S_START                       (0x05100010)
 #define MDP_AXI_RDMASTER_CONFIG               (0x05100028)
 #define MDP_AXI_WRMASTER_CONFIG               (0x05100030)
-#define MDP_MAX_RD_PENDING_CMD_CONFIG         (0x0510004C)
 #define MDP_DISP_INTF_SEL                     (0x05100038)
+#define MDP_MAX_RD_PENDING_CMD_CONFIG         (0x0510004C)
+#define MDP_INTR_ENABLE                       (0x05100050)
+#define MDP_DSI_CMD_MODE_ID_MAP               (0x051000A0)
+#define MDP_DSI_CMD_MODE_TRIGGER_EN           (0x051000A4)
 #define MDP_OVERLAYPROC0_CFG                  (0x05110004)
 #define MDP_DMA_P_CONFIG                      (0x05190000)
 #define MDP_DMA_P_OUT_XY                      (0x05190010)
@@ -148,54 +165,54 @@
 
 //BEGINNING OF Tochiba Config- video mode
 
-static const unsigned char dsi_toshiba_display_config_MCAP_off[8] = {
+static const unsigned char toshiba_panel_mcap_off[8] = {
     0x02, 0x00, 0x29, 0xc0,
     0xb2, 0x00, 0xff, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_ena_test_reg[8] = {
+static const unsigned char toshiba_panel_ena_test_reg[8] = {
     0x03, 0x00, 0x29, 0xc0,
     0xEF, 0x01, 0x01, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_ena_test_reg_wvga[8] = {
+static const unsigned char toshiba_panel_ena_test_reg_wvga[8] = {
     0x03, 0x00, 0x29, 0xc0,
     0xEF, 0x01, 0x01, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_num_of_2lane[8] = {
+static const unsigned char toshiba_panel_num_of_2lane[8] = {
     0x03, 0x00, 0x29, 0xc0,     // 63:2lane
     0xEF, 0x60, 0x63, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_num_of_1lane[8] = {
+static const unsigned char toshiba_panel_num_of_1lane[8] = {
     0x03, 0x00, 0x29, 0xc0,     // 62:1lane
     0xEF, 0x60, 0x62, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_non_burst_sync_pulse[8] = {
+static const unsigned char toshiba_panel_non_burst_sync_pulse[8] = {
     0x03, 0x00, 0x29, 0xc0,
     0xef, 0x61, 0x09, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_set_DMODE_WQVGA[8] = {
+static const unsigned char toshiba_panel_set_DMODE_WQVGA[8] = {
     0x02, 0x00, 0x29, 0xc0,
     0xB3, 0x01, 0xFF, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_set_DMODE_WVGA[8] = {
+static const unsigned char toshiba_panel_set_DMODE_WVGA[8] = {
     0x02, 0x00, 0x29, 0xc0,
     0xB3, 0x00, 0xFF, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_set_intern_WR_clk1_wvga[8]
+static const unsigned char toshiba_panel_set_intern_WR_clk1_wvga[8]
     = {
 
     0x03, 0x00, 0x29, 0xC0,     // 1 last packet
     0xef, 0x2f, 0xcc, 0xff,
 };
 
-static const unsigned char dsi_toshiba_display_config_set_intern_WR_clk2_wvga[8]
+static const unsigned char toshiba_panel_set_intern_WR_clk2_wvga[8]
     = {
 
     0x03, 0x00, 0x29, 0xC0,     // 1 last packet
@@ -203,20 +220,20 @@
 };
 
 static const unsigned char
-    dsi_toshiba_display_config_set_intern_WR_clk1_wqvga[8] = {
+    toshiba_panel_set_intern_WR_clk1_wqvga[8] = {
 
     0x03, 0x00, 0x29, 0xC0,     // 1 last packet
     0xef, 0x2f, 0x22, 0xff,
 };
 
 static const unsigned char
-    dsi_toshiba_display_config_set_intern_WR_clk2_wqvga[8] = {
+    toshiba_panel_set_intern_WR_clk2_wqvga[8] = {
 
     0x03, 0x00, 0x29, 0xC0,     // 1 last packet
     0xef, 0x6e, 0x33, 0xff,
 };
 
-static const unsigned char dsi_toshiba_display_config_set_hor_addr_2A_wvga[12] = {
+static const unsigned char toshiba_panel_set_hor_addr_2A_wvga[12] = {
 
     0x05, 0x00, 0x39, 0xC0,     // 1 last packet
     // 0x2A, 0x00, 0x08, 0x00,//100 = 64h
@@ -225,7 +242,7 @@
     0xdf, 0xFF, 0xFF, 0xFF,
 };
 
-static const unsigned char dsi_toshiba_display_config_set_hor_addr_2B_wvga[12] = {
+static const unsigned char toshiba_panel_set_hor_addr_2B_wvga[12] = {
 
     0x05, 0x00, 0x39, 0xC0,     // 1 last packet
     // 0x2B, 0x00, 0x08, 0x00,//0X355 = 854-1; 0X1DF = 480-1
@@ -234,7 +251,7 @@
     0x55, 0xFF, 0xFF, 0xFF,
 };
 
-static const unsigned char dsi_toshiba_display_config_set_hor_addr_2A_wqvga[12]
+static const unsigned char toshiba_panel_set_hor_addr_2A_wqvga[12]
     = {
 
     0x05, 0x00, 0x39, 0xC0,     // 1 last packet
@@ -242,7 +259,7 @@
     0xef, 0xFF, 0xFF, 0xFF,
 };
 
-static const unsigned char dsi_toshiba_display_config_set_hor_addr_2B_wqvga[12]
+static const unsigned char toshiba_panel_set_hor_addr_2B_wqvga[12]
     = {
 
     0x05, 0x00, 0x39, 0xC0,     // 1 last packet
@@ -250,22 +267,22 @@
     0xaa, 0xFF, 0xFF, 0xFF,
 };
 
-static const unsigned char dsi_toshiba_display_config_IFSEL[8] = {
+static const unsigned char toshiba_panel_IFSEL[8] = {
     0x02, 0x00, 0x29, 0xc0,
     0x53, 0x01, 0xff, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_IFSEL_cmd_mode[8] = {
+static const unsigned char toshiba_panel_IFSEL_cmd_mode[8] = {
     0x02, 0x00, 0x29, 0xc0,
     0x53, 0x00, 0xff, 0xff
 };
 
-static const unsigned char dsi_toshiba_display_config_exit_sleep[4] = {
+static const unsigned char toshiba_panel_exit_sleep[4] = {
     0x11, 0x00, 0x05, 0x80,     // 25 Reg 0x29 < Display On>; generic write 1
                                 // params
 };
 
-static const unsigned char dsi_toshiba_display_config_display_on[4] = {
+static const unsigned char toshiba_panel_display_on[4] = {
     // 0x29, 0x00, 0x05, 0x80,//25 Reg 0x29 < Display On>; generic write 1
     // params
     0x29, 0x00, 0x05, 0x80,     // 25 Reg 0x29 < Display On>; generic write 1
@@ -284,4 +301,149 @@
 
 //the end OF Tochiba Config- video mode
 
+/* NOVATEK BLUE panel */
+static char novatek_panel_sw_reset[4] = {0x01, 0x00, 0x05, 0x00}; /* DTYPE_DCS_WRITE */
+static char novatek_panel_enter_sleep[4] = {0x10, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
+static char novatek_panel_exit_sleep[4] = {0x11, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
+static char novatek_panel_display_off[4] = {0x28, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
+static char novatek_panel_display_on[4] = {0x29, 0x00, 0x05, 0x80}; /* DTYPE_DCS_WRITE */
+
+static char novatek_panel_set_onelane[4] = {0xae, 0x01, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
+static char novatek_panel_rgb_888[4] = {0x3A, 0x77, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
+static char novatek_panel_set_twolane[4] = {0xae, 0x03, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
+
+/* commands by Novatke */
+static char novatek_panel_f4[4] = {0xf4, 0x55, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
+static char novatek_panel_8c[20] = { /* DTYPE_DCS_LWRITE */
+  0x10, 0x00, 0x39, 0xC0, 0x8C, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x08, 0x08, 0x00, 0x30, 0xC0, 0xB7, 0x37};
+static char novatek_panel_ff[4] = {0xff, 0x55, 0x15, 0x80}; /* DTYPE_DCS_WRITE1 */
+
+static char novatek_panel_set_width[12] = { /* DTYPE_DCS_LWRITE */
+  0x05, 0x00, 0x39, 0xC0,//1 last packet
+  0x2A, 0x00, 0x00, 0x02,//clmn:0 - 0x21B=539
+  0x1B, 0xFF, 0xFF, 0xFF
+}; /* 540 - 1 */
+static char novatek_panel_set_height[12] = { /* DTYPE_DCS_LWRITE */
+  0x05, 0x00, 0x39, 0xC0,//1 last packet
+  0x2B, 0x00, 0x00, 0x03,//row:0 - 0x3BF=959
+  0xBF, 0xFF, 0xFF, 0xFF,
+}; /* 960 - 1 */
+/* End of Novatek Blue panel commands */
+
+
+#define MIPI_VIDEO_MODE	        1
+#define MIPI_CMD_MODE           2
+
+struct mipi_dsi_phy_ctrl {
+    uint32_t regulator[4];
+    uint32_t timing[12];
+    uint32_t ctrl[4];
+    uint32_t strength[4];
+    uint32_t pll[21];
+};
+
+struct mipi_dsi_cmd {
+    int size;
+    char *payload;
+};
+
+struct mipi_dsi_panel_config {
+    char mode;
+    char num_of_lanes;
+    struct mipi_dsi_phy_ctrl *dsi_phy_config;
+    struct mipi_dsi_cmd *panel_cmds;
+    int num_of_panel_cmds;
+};
+
+static struct mipi_dsi_cmd toshiba_panel_video_mode_cmds[] = {
+    {sizeof(toshiba_panel_mcap_off), toshiba_panel_mcap_off},
+    {sizeof(toshiba_panel_ena_test_reg), toshiba_panel_ena_test_reg},
+    {sizeof(toshiba_panel_num_of_1lane), toshiba_panel_num_of_1lane},
+    {sizeof(toshiba_panel_non_burst_sync_pulse), toshiba_panel_non_burst_sync_pulse},
+    {sizeof(toshiba_panel_set_DMODE_WVGA), toshiba_panel_set_DMODE_WVGA},
+    {sizeof(toshiba_panel_set_intern_WR_clk1_wvga), toshiba_panel_set_intern_WR_clk1_wvga},
+    {sizeof(toshiba_panel_set_intern_WR_clk2_wvga), toshiba_panel_set_intern_WR_clk2_wvga},
+    {sizeof(toshiba_panel_set_hor_addr_2A_wvga), toshiba_panel_set_hor_addr_2A_wvga},
+    {sizeof(toshiba_panel_set_hor_addr_2B_wvga), toshiba_panel_set_hor_addr_2B_wvga},
+    {sizeof(toshiba_panel_IFSEL), toshiba_panel_IFSEL},
+    {sizeof(toshiba_panel_exit_sleep), toshiba_panel_exit_sleep},
+    {sizeof(toshiba_panel_display_on), toshiba_panel_display_on},
+    {sizeof(dsi_display_config_color_mode_on), dsi_display_config_color_mode_on},
+    {sizeof(dsi_display_config_color_mode_off), dsi_display_config_color_mode_off},
+};
+
+static struct mipi_dsi_phy_ctrl mipi_dsi_toshiba_panel_phy_ctrl = {
+	/* 480*854, RGB888, 1 Lane 60 fps video mode */
+		{0x03, 0x01, 0x01, 0x00},	/* regulator */
+		/* timing   */
+		{0x50, 0x0f, 0x14, 0x19, 0x23, 0x0e, 0x12, 0x16,
+		0x1b, 0x1c, 0x04},
+		{0x7f, 0x00, 0x00, 0x00},	/* phy ctrl */
+		{0xee, 0x03, 0x86, 0x03},	/* strength */
+		/* pll control */
+
+#if defined(DSI_BIT_CLK_366MHZ)
+		{0x41, 0xdb, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
+		0x31, 0x0f, 0x07,
+		0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
+#elif defined(DSI_BIT_CLK_380MHZ)
+		{0x41, 0xf7, 0xb2, 0xf5, 0x00, 0x50, 0x48, 0x63,
+		0x31, 0x0f, 0x07,
+		0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
+#elif defined(DSI_BIT_CLK_400MHZ)
+		{0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
+		0x31, 0x0f, 0x07,
+		0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
+#else		/* 200 mhz */
+		{0x41, 0x8f, 0xb1, 0xda, 0x00, 0x50, 0x48, 0x63,
+		 0x33, 0x1f, 0x1f /* for 1 lane ; 0x0f for 2 lanes*/,
+		0x05, 0x14, 0x03, 0x03, 0x03, 0x54, 0x06, 0x10, 0x04, 0x03 },
+#endif
+};
+
+static struct mipi_dsi_cmd novatek_panel_cmd_mode_cmds[] = {
+    {sizeof(novatek_panel_sw_reset), novatek_panel_sw_reset},
+    {sizeof(novatek_panel_exit_sleep), novatek_panel_exit_sleep},
+    {sizeof(novatek_panel_display_on), novatek_panel_display_on},
+    {sizeof(novatek_panel_f4), novatek_panel_f4},
+    {sizeof(novatek_panel_8c), novatek_panel_8c},
+    {sizeof(novatek_panel_ff), novatek_panel_ff},
+    {sizeof(novatek_panel_set_twolane), novatek_panel_set_twolane},
+    {sizeof(novatek_panel_set_width), novatek_panel_set_width},
+    {sizeof(novatek_panel_set_height), novatek_panel_set_height},
+    {sizeof(novatek_panel_rgb_888), novatek_panel_rgb_888}
+};
+
+static struct mipi_dsi_phy_ctrl mipi_dsi_novatek_panel_phy_ctrl = {
+  /* DSI_BIT_CLK at 500MHz, 2 lane, RGB888 */
+  {0x03, 0x01, 0x01, 0x00},       /* regulator */
+  /* timing   */
+  {0x96, 0x26, 0x23, 0x00, 0x50, 0x4B, 0x1e,
+   0x28, 0x28, 0x03, 0x04},
+  {0x7f, 0x00, 0x00, 0x00},       /* phy ctrl */
+  {0xee, 0x02, 0x86, 0x00},       /* strength */
+  /* pll control */
+  {0x40, 0xf9, 0xb0, 0xda, 0x00, 0x50, 0x48, 0x63,
+   /* 0x30, 0x07, 0x07,  --> One lane configuration */
+   0x30, 0x07, 0x03, /*  --> Two lane configuration */
+   0x05, 0x14, 0x03, 0x0, 0x0, 0x54, 0x06, 0x10, 0x04, 0x0},
+};
+
+struct mipi_dsi_panel_config toshiba_panel_info = {
+    .mode = MIPI_VIDEO_MODE,
+    .num_of_lanes = 1,
+    .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl,
+    .panel_cmds = toshiba_panel_video_mode_cmds,
+    .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds),
+};
+
+struct mipi_dsi_panel_config novatek_panel_info = {
+    .mode = MIPI_CMD_MODE,
+    .num_of_lanes = 2,
+    .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl,
+    .panel_cmds = novatek_panel_cmd_mode_cmds,
+    .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds),
+};
+
 #endif
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index 660db66..8f2c4e7 100755
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -91,7 +91,7 @@
 /* If set waits for CmdPend before starting to send a command */
 #define MMC_BOOT_MCI_CMD_PENDING          (1 << 9)
 /* CPSM is enabled if set */
-#define MMC_BOT_MCI_CMD_ENABLE            (1 << 10)
+#define MMC_BOOT_MCI_CMD_ENABLE           (1 << 10)
 /* If set PROG_DONE status bit asserted when busy is de-asserted */
 #define MMC_BOOT_MCI_CMD_PROG_ENA         (1 << 11)
 /* To indicate that this is a Command with Data (for SDIO interrupts) */
@@ -276,6 +276,9 @@
 #define CMD18_READ_MULTIPLE_BLOCK        18
 #define CMD24_WRITE_SINGLE_BLOCK         24
 #define CMD25_WRITE_MULTIPLE_BLOCK       25
+#define CMD28_SET_WRITE_PROTECT          28
+#define CMD29_CLEAR_WRITE_PROTECT        29
+#define CMD31_SEND_WRITE_PROT_TYPE       31
 #define CMD32_ERASE_WR_BLK_START         32
 #define CMD33_ERASE_WR_BLK_END           33
 #define CMD38_ERASE                      38
@@ -369,6 +372,20 @@
 #define MMC_BOOT_EXT_CMMC_HS_TIMING       185
 #define MMC_BOOT_EXT_CMMC_BUS_WIDTH       183
 
+#define MMC_BOOT_EXT_USER_WP              171
+#define MMC_BOOT_EXT_ERASE_GROUP_DEF      175
+#define MMC_BOOT_EXT_HC_WP_GRP_SIZE       221
+#define MMC_BOOT_EXT_HC_ERASE_GRP_SIZE    224
+
+#define IS_BIT_SET_EXT_CSD(val, bit)      ((ext_csd_buf[val]) & (1<<(bit)))
+#define IS_ADDR_OUT_OF_RANGE(resp)        ((resp >> 31) & 0x01)
+
+#define MMC_BOOT_US_PERM_WP_EN            2
+#define MMC_BOOT_US_PWR_WP_DIS            3
+
+#define MMC_BOOT_US_PERM_WP_DIS           (1<<4)
+#define MMC_BOOT_US_PWR_WP_EN             1
+
 /* For SD */
 #define MMC_BOOT_SD_HC_VOLT_SUPPLIED      0x000001AA
 #define MMC_BOOT_SD_NEG_OCR               0x00FF8000
@@ -408,6 +425,12 @@
     unsigned int nsac_clk_cycle;
     unsigned int taac_ns;
     unsigned int tran_speed;
+    unsigned int erase_grp_size;
+    unsigned int erase_grp_mult;
+    unsigned int wp_grp_size;
+    unsigned int wp_grp_enable:1;
+    unsigned int perm_wp:1;
+    unsigned int temp_wp:1;
     unsigned int erase_blk_len:1;
     unsigned int read_blk_misalign:1;
     unsigned int write_blk_misalign:1;
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 88df541..4d2a515 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -34,6 +34,7 @@
 
 #define MIPI_FB_ADDR  0x43E00000
 
+#if DISPLAY_MIPI_PANEL_TOSHIBA
 static struct fbcon_config mipi_fb_cfg = {
     .height = TSH_MIPI_FB_HEIGHT,
     .width = TSH_MIPI_FB_WIDTH,
@@ -43,16 +44,39 @@
     .update_start = NULL,
     .update_done = NULL,
 };
+#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
+static struct fbcon_config mipi_fb_cfg = {
+    .height = NOV_MIPI_FB_HEIGHT,
+    .width = NOV_MIPI_FB_WIDTH,
+    .stride = NOV_MIPI_FB_WIDTH,
+    .format = FB_FORMAT_RGB888,
+    .bpp = 24,
+    .update_start = NULL,
+    .update_done = NULL,
+};
+#else
+static struct fbcon_config mipi_fb_cfg = {
+    .height = 0,
+    .width = 0,
+    .stride = 0,
+    .format = 0,
+    .bpp = 0,
+    .update_start = NULL,
+    .update_done = NULL,
+};
+#endif
+
+static int cmd_mode_status = 0;
 
 void configure_dsicore_dsiclk()
 {
     unsigned char mnd_mode, root_en, clk_en;
-    unsigned long src_sel = 0x3;    //dsi_phy_pll0_src
+    unsigned long src_sel = 0x3;    // dsi_phy_pll0_src
     unsigned long pre_div_func = 0x00;  // predivide by 1
     unsigned long pmxo_sel;
 
     writel(pre_div_func << 14 | src_sel, MMSS_DSI_NS);
-    mnd_mode = 0;               //Bypass MND
+    mnd_mode = 0;               // Bypass MND
     root_en = 1;
     clk_en = 1;
     pmxo_sel = 0;
@@ -69,93 +93,87 @@
 
 void configure_dsicore_pclk(void)
 {
-
     unsigned char mnd_mode, root_en, clk_en;
     unsigned long src_sel = 0x3;    // dsi_phy_pll0_src
     unsigned long pre_div_func = 0x01;  // predivide by 2
 
     writel(pre_div_func << 12 | src_sel, MMSS_DSI_PIXEL_NS);
 
-    mnd_mode = 0;              // Bypass MND
+    mnd_mode = 0;               // Bypass MND
     root_en = 1;
     clk_en = 1;
     writel(mnd_mode << 6, MMSS_DSI_PIXEL_CC);
     writel(readl(MMSS_DSI_PIXEL_CC) | root_en << 2, MMSS_DSI_PIXEL_CC);
     writel(readl(MMSS_DSI_PIXEL_CC) | clk_en, MMSS_DSI_PIXEL_CC);
-
 }
 
-int dsi_dsiphy_reg_bitclk_200MHz_toshiba_rgb888(unsigned char lane_num_hs)
+int mipi_dsi_phy_ctrl_config(struct mipi_dsi_panel_config *pinfo)
 {
 
     unsigned char lane_1 = 1;
     unsigned char lane_2 = 2;
+    unsigned i;
+    unsigned off = 0;
+    struct mipi_dsi_phy_ctrl *pd;
 
     writel(0x00000001, DSI_PHY_SW_RESET);
-    mdelay(100);
+    mdelay(50);
     writel(0x00000000, DSI_PHY_SW_RESET);
 
-    writel(0x00000003, DSIPHY_REGULATOR_CTRL_0);
-    writel(0x00000001, DSIPHY_REGULATOR_CTRL_1);
-    writel(0x00000001, DSIPHY_REGULATOR_CTRL_2);
-    writel(0x00000000, DSIPHY_REGULATOR_CTRL_3);
+    pd = (pinfo->dsi_phy_config);
 
-    writel(0x50, DSIPHY_TIMING_CTRL_0);
-    writel(0x0f, DSIPHY_TIMING_CTRL_1);
-    writel(0x14, DSIPHY_TIMING_CTRL_2);
-    writel(0x19, DSIPHY_TIMING_CTRL_4);
-    writel(0x23, DSIPHY_TIMING_CTRL_5);
-    writel(0x0e, DSIPHY_TIMING_CTRL_6);
-    writel(0x12, DSIPHY_TIMING_CTRL_7);
-    writel(0x16, DSIPHY_TIMING_CTRL_8);
-    writel(0x1b, DSIPHY_TIMING_CTRL_9);
-    writel(0x1c, DSIPHY_TIMING_CTRL_10);
+    off = 0x02cc;               /* regulator ctrl 0 */
+    for (i = 0; i < 4; i++) {
+        writel(pd->regulator[i], MIPI_DSI_BASE + off);
+        off += 4;
+    }
+
+    off = 0x0260;               /* phy timig ctrl 0 */
+    for (i = 0; i < 11; i++) {
+        writel(pd->timing[i], MIPI_DSI_BASE + off);
+        off += 4;
+    }
 
     // T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing length should >
     // data lane HS timing length
-    writel(0x90f, DSI_CLKOUT_TIMING_CTRL);
+    writel(0xa1e, DSI_CLKOUT_TIMING_CTRL);
 
-    writel(0x7f, DSIPHY_CTRL_0);
-    writel(0x00, DSIPHY_CTRL_1);
-    writel(0x00, DSIPHY_CTRL_2);
-    writel(0x00, DSIPHY_CTRL_3);
-
-    writel(0xEE, DSIPHY_STRENGTH_CTRL_0);
-    writel(0x86, DSIPHY_STRENGTH_CTRL_0);
-
-    writel(0x8f, DSIPHY_PLL_CTRL_1);    // vco=400*2=800Mhz
-
-    writel(0xb1, DSIPHY_PLL_CTRL_2);
-    writel(0xda, DSIPHY_PLL_CTRL_3);
-    writel(0x00, DSIPHY_PLL_CTRL_4);
-    writel(0x50, DSIPHY_PLL_CTRL_5);
-    writel(0x48, DSIPHY_PLL_CTRL_6);
-    writel(0x63, DSIPHY_PLL_CTRL_7);
-
-    writel(0x33, DSIPHY_PLL_CTRL_8);    // bit clk 800/4=200mhz
-    writel(0x1f, DSIPHY_PLL_CTRL_9);    // byte clk 800/32=25mhz (200/8=25)
-
-    if (lane_num_hs == lane_1) {
-        printf("\nData Lane: 1 lane");
-        writel(0x1f, DSIPHY_PLL_CTRL_10);   // 1 lane dsi clk 800/32=25mhz
-    } else if (lane_num_hs == lane_2) {
-        printf("\nData Lane: 2 lane");
-        writel(0x0f, DSIPHY_PLL_CTRL_10);   // 2 lane dsi clk 800/16=50mhz
+    off = 0x0290;               /* ctrl 0 */
+    for (i = 0; i < 4; i++) {
+        writel(pd->ctrl[i], MIPI_DSI_BASE + off);
+        off += 4;
     }
 
-    writel(0x05, DSIPHY_PLL_CTRL_11);
-    writel(0x14, DSIPHY_PLL_CTRL_12);
-    writel(0x03, DSIPHY_PLL_CTRL_13);
-    writel(0x54, DSIPHY_PLL_CTRL_16);
-    writel(0x06, DSIPHY_PLL_CTRL_17);
-    writel(0x10, DSIPHY_PLL_CTRL_18);
-    writel(0x04, DSIPHY_PLL_CTRL_19);
-    writel(0x00000040, DSIPHY_PLL_CTRL_0);
-    writel(0x00000041, DSIPHY_PLL_CTRL_0);  // dsipll en
+    off = 0x02a0;               /* strength 0 */
+    for (i = 0; i < 4; i++) {
+        writel(pd->strength[i], MIPI_DSI_BASE + off);
+        off += 4;
+    }
+
+    off = 0x0204;               /* pll ctrl 1, skip 0 */
+    for (i = 1; i < 21; i++) {
+        writel(pd->pll[i], MIPI_DSI_BASE + off);
+        off += 4;
+    }
+
+    /* pll ctrl 0 */
+    writel(pd->pll[0], MIPI_DSI_BASE + 0x200);
+    writel((pd->pll[0] | 0x01), MIPI_DSI_BASE + 0x200);
 
     return (0);
 }
 
+struct mipi_dsi_panel_config *get_panel_info(void)
+{
+#if  DISPLAY_MIPI_PANEL_TOSHIBA
+    return &toshiba_panel_info;
+#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
+    return &novatek_panel_info;
+#endif
+    return NULL;
+
+}
+
 int dsi_cmd_dma_trigger_for_panel()
 {
     unsigned long ReadValue;
@@ -163,7 +181,7 @@
     int status = 0;
 
     writel(0x03030303, DSI_INT_CTRL);
-    mdelay(1);
+    mdelay(10);
     writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
     ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
     while (ReadValue != 0x00000001) {
@@ -182,9 +200,26 @@
     return status;
 }
 
-int dsi_toshiba_panel_config_video_mode_wvga(unsigned char lane_num)
+int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
 {
+    int ret = 0;
+    struct mipi_dsi_cmd *cm;
+    int i = 0;
 
+    cm = cmds;
+    for (i = 0; i < count; i++) {
+        memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL, (cm->payload), cm->size);
+        writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
+        writel(cm->size, DSI_DMA_CMD_LENGTH);   // reg 0x48 for this build
+        ret += dsi_cmd_dma_trigger_for_panel();
+        mdelay(10);
+        cm++;
+    }
+    return ret;
+}
+
+int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
+{
     unsigned char DMA_STREAM1 = 0;  // for mdp display processor path
     unsigned char EMBED_MODE1 = 1;  // from frame buffer
     unsigned char POWER_MODE2 = 1;  // from frame buffer
@@ -193,119 +228,36 @@
     unsigned char DT1 = 0;      // non embedded mode
     unsigned short WC1 = 0;     // for non embedded mode only
     int status = 0;
-    unsigned char DLNx_EN = 1;
+    unsigned char DLNx_EN;
     unsigned char lane_1 = 1;
     unsigned char lane_2 = 2;
 
+    switch (pinfo->num_of_lanes) {
+    default:
+    case 1:
+        DLNx_EN = 1;            // 1 lane
+        break;
+    case 2:
+        DLNx_EN = 3;            // 2 lane
+        break;
+    case 3:
+        DLNx_EN = 7;            // 3 lane
+        break;
+    }
+
+    writel(0x0001, DSI_SOFT_RESET);
+    writel(0x0000, DSI_SOFT_RESET);
+
     writel((0 << 16) | 0x3f, DSI_CLK_CTRL); // reg:0x118
     writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw
-                                                    // trigger 0x4; dma stream1
+    // trigger 0x4; dma stream1
     writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL);   // reg 0x00 for this
-                                                        // build
+    // build
     writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26
            | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
            DSI_COMMAND_MODE_DMA_CTRL);
-    writel(0x15000000, DSI_COMMAND_MODE_DMA_CTRL);  // reg 0x38 wc=4; DT=09;
-                                                    // embedded mode=0 from the
-                                                    // reg.
 
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_MCAP_off, 8);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_ena_test_reg, 8);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    if (lane_num == lane_1) {
-        memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-               &dsi_toshiba_display_config_num_of_1lane, 8);
-    } else if (lane_num == lane_2) {
-
-        memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-               &dsi_toshiba_display_config_num_of_2lane, 8);
-    }
-
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_non_burst_sync_pulse, 8);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_set_DMODE_WVGA, 8);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_set_intern_WR_clk1_wvga, 8);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_set_intern_WR_clk2_wvga, 8);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_set_hor_addr_2A_wvga, 12);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(12, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_set_hor_addr_2B_wvga, 12);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(12, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL, &dsi_toshiba_display_config_IFSEL,
-           8);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(8, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_exit_sleep, 4);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(4, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    writel(0x14000000, DSI_COMMAND_MODE_DMA_CTRL);
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL,
-           &dsi_toshiba_display_config_display_on, 4);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(4, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    // dsi_display_config_color_mode_on - low power
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL, &dsi_display_config_color_mode_on,
-           4);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(4, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    // dsi_display_config_color_mode_off - back to normal
-    memcpy(DSI_CMD_DMA_MEM_START_ADDR_PANEL, &dsi_display_config_color_mode_off,
-           4);
-    writel(DSI_CMD_DMA_MEM_START_ADDR_PANEL, DSI_DMA_CMD_OFFSET);
-    writel(4, DSI_DMA_CMD_LENGTH);  // reg 0x48 for this build
-    status += dsi_cmd_dma_trigger_for_panel();
-
-    writel(0x0000, DSI_CTRL);
-    writel(0x0001, DSI_SOFT_RESET);
-    writel(0x0000, DSI_SOFT_RESET);
+    status = mipi_dsi_cmds_tx(pinfo->panel_cmds, pinfo->num_of_panel_cmds);
 
     return status;
 }
@@ -395,11 +347,82 @@
 
     writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4
            | 0x103, DSI_CTRL);
-    mdelay(1);
+    mdelay(10);
 
     return status;
 }
 
+int config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height,
+                        unsigned short img_width, unsigned short img_height,
+                        unsigned short dst_format,
+                        unsigned short traffic_mode,
+                        unsigned short datalane_num)
+{
+    unsigned char DST_FORMAT;
+    unsigned char TRAFIC_MODE;
+    unsigned char DLNx_EN;
+    // video mode data ctrl
+    int status = 0;
+    unsigned long low_pwr_stop_mode = 0;
+    unsigned char eof_bllp_pwr = 0x9;
+    unsigned char interleav = 0;
+    unsigned char ystride = 0x03;
+    // disable mdp first
+
+    writel(0x00000000, DSI_CLK_CTRL);
+    writel(0x00000000, DSI_CLK_CTRL);
+    writel(0x00000000, DSI_CLK_CTRL);
+    writel(0x00000000, DSI_CLK_CTRL);
+    writel(0x00000002, DSI_CLK_CTRL);
+    writel(0x00000006, DSI_CLK_CTRL);
+    writel(0x0000000e, DSI_CLK_CTRL);
+    writel(0x0000001e, DSI_CLK_CTRL);
+    writel(0x0000003e, DSI_CLK_CTRL);
+
+    writel(0x10000000, DSI_ERR_INT_MASK0);
+
+    // writel(0, DSI_CTRL);
+
+    // writel(0, DSI_ERR_INT_MASK0);
+
+    DST_FORMAT = 8;             // RGB888
+    printf("\nDSI_Cmd_Mode - Dst Format: RGB888");
+
+    DLNx_EN = 3;                // 2 lane with clk programming
+    printf("\nData Lane: 2 lane\n");
+
+    TRAFIC_MODE = 0;            // non burst mode with sync pulses
+    printf("\nTraffic mode: non burst mode with sync pulses\n");
+
+    writel(0x02020202, DSI_INT_CTRL);
+
+    writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
+    writel((img_width * ystride + 1) << 16 | 0x0039,
+           DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
+    writel((img_width * ystride + 1) << 16 | 0x0039,
+           DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
+    writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
+    writel(img_height << 16 | img_width, DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
+    writel(0xEE, DSI_CAL_STRENGTH_CTRL);
+    writel(0x80000000, DSI_CAL_CTRL);
+    writel(0x40, DSI_TRIG_CTRL);
+    writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
+    writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
+           DSI_CTRL);
+    mdelay(10);
+    writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
+    writel(0x10000000, DSI_MISR_CMD_CTRL);
+    writel(0x00000040, DSI_ERR_INT_MASK0);
+    writel(0x1, DSI_EOT_PACKET_CTRL);
+    // writel(0x0, MDP_OVERLAYPROC0_START);
+    writel(0x00000001, MDP_DMA_P_START);
+    mdelay(10);
+    writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
+
+    status = 1;
+    return status;
+}
+
 int mdp_setup_dma_p_video_mode(unsigned short disp_width,
                                unsigned short disp_height,
                                unsigned short img_width,
@@ -464,17 +487,17 @@
     return status;
 }
 
-int mipi_dsi_config(unsigned short num_of_lanes)
+int mipi_dsi_video_config(unsigned short num_of_lanes)
 {
 
     int status = 0;
     unsigned long ReadValue;
     unsigned long count = 0;
     unsigned long low_pwr_stop_mode = 0;    // low power mode 0x1111 start from
-                                            // bit16, high spd mode 0x0
+    // bit16, high spd mode 0x0
     unsigned char eof_bllp_pwr = 0x9;   // bit 12, 15, 1:low power stop mode or
-                                        // let cmd mode eng send packets in hs
-                                        // or lp mode
+    // let cmd mode eng send packets in hs
+    // or lp mode
     unsigned short display_wd = mipi_fb_cfg.width;
     unsigned short display_ht = mipi_fb_cfg.height;
     unsigned short image_wd = mipi_fb_cfg.width;
@@ -491,10 +514,10 @@
     unsigned char ystride = 3;
 
     low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA,
-                                // bit24:HFP, bit28:PULSE MODE, need enough
-                                // time for swithc from LP to HS
+    // bit24:HFP, bit28:PULSE MODE, need enough
+    // time for swithc from LP to HS
     eof_bllp_pwr = 0x9;         // low power stop mode or let cmd mode eng send
-                                // packets in hs or lp mode
+    // packets in hs or lp mode
 
     status += config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht,
                                     hsync_porch_fp, hsync_porch_bp,
@@ -524,6 +547,80 @@
     return status;
 }
 
+int mipi_dsi_cmd_config(unsigned short num_of_lanes)
+{
+
+    int status = 0;
+    unsigned long ReadValue;
+    unsigned long count = 0;
+    unsigned long input_img_addr = MIPI_FB_ADDR;
+    unsigned long low_pwr_stop_mode = 0;    // low power mode 0x1111 start from
+    // bit16, high spd mode 0x0
+    unsigned char eof_bllp_pwr = 0x9;   // bit 12, 15, 1:low power stop mode or
+    // let cmd mode eng send packets in hs
+    // or lp mode
+    unsigned short display_wd = mipi_fb_cfg.width;
+    unsigned short display_ht = mipi_fb_cfg.height;
+    unsigned short image_wd = mipi_fb_cfg.width;
+    unsigned short image_ht = mipi_fb_cfg.height;
+    unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK;
+    unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK;
+    unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES;
+    unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES;
+    unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH;
+    unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH;
+    unsigned short dst_format = 0;
+    unsigned short traffic_mode = 0;
+    unsigned short pack_pattern = 0x12;
+    unsigned char ystride = 3;
+
+    writel(0x03ffffff, MDP_INTR_ENABLE);
+    writel(0x0000000b, MDP_OVERLAYPROC0_CFG);
+
+    // ------------- programming MDP_DMA_P_CONFIG ---------------------
+    writel(pack_pattern << 8 | 0x3f | (0 << 25), MDP_DMA_P_CONFIG); // rgb888
+
+    writel(0x00000000, MDP_DMA_P_OUT_XY);
+    writel(image_ht << 16 | image_wd, MDP_DMA_P_SIZE);
+    writel(input_img_addr, MDP_DMA_P_BUF_ADDR);
+
+    writel(image_wd * ystride, MDP_DMA_P_BUF_Y_STRIDE);
+
+    writel(0x00000000, MDP_DMA_P_OP_MODE);
+
+    writel(0x10, MDP_DSI_CMD_MODE_ID_MAP);
+    writel(0x01, MDP_DSI_CMD_MODE_TRIGGER_EN);
+
+    writel(0x0001a000, MDP_AXI_RDMASTER_CONFIG);
+    writel(0x00000004, MDP_AXI_WRMASTER_CONFIG);
+    writel(0x00007777, MDP_MAX_RD_PENDING_CMD_CONFIG);
+    writel(0x8a, MDP_DISP_INTF_SEL);
+
+    return status;
+}
+
+int is_cmd_mode_enabled(void)
+{
+    return cmd_mode_status;
+}
+
+void mipi_dsi_cmd_mode_trigger(void)
+{
+    int status = 0;
+    unsigned short display_wd = mipi_fb_cfg.width;
+    unsigned short display_ht = mipi_fb_cfg.height;
+    unsigned short image_wd = mipi_fb_cfg.width;
+    unsigned short image_ht = mipi_fb_cfg.height;
+    unsigned short dst_format = 0;
+    unsigned short traffic_mode = 0;
+    struct mipi_dsi_panel_config *panel_info = &novatek_panel_info;
+    status += mipi_dsi_cmd_config(panel_info->num_of_lanes);
+    mdelay(50);
+    config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht,
+                        dst_format, traffic_mode,
+                        panel_info->num_of_lanes /* num_of_lanes */ );
+}
+
 void mipi_dsi_shutdown(void)
 {
     writel(0, DSI_CTRL);
@@ -536,14 +633,20 @@
 {
     int status = 0;
     unsigned char num_of_lanes = 1;
+    struct mipi_dsi_panel_config *panel_info = get_panel_info();
     writel(0x00001800, MMSS_SFPB_GPREG);
     configure_dsicore_dsiclk();
     configure_dsicore_byteclk();
     configure_dsicore_pclk();
-    dsi_dsiphy_reg_bitclk_200MHz_toshiba_rgb888(num_of_lanes);
-    status += dsi_toshiba_panel_config_video_mode_wvga(num_of_lanes);
+    mipi_dsi_phy_ctrl_config(panel_info);
+    status += mipi_dsi_panel_initialize(panel_info);
     mipi_fb_cfg.base = MIPI_FB_ADDR;
 
-    status += mipi_dsi_config(num_of_lanes);
+    if (panel_info->mode == MIPI_VIDEO_MODE)
+        status += mipi_dsi_video_config(panel_info->num_of_lanes);
+
+    if (panel_info->mode == MIPI_CMD_MODE)
+        cmd_mode_status = 1;
+
     return &mipi_fb_cfg;
 }
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index 96ff275..5451a59 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -62,6 +62,9 @@
 unsigned char mmc_slot = 0;
 unsigned int mmc_boot_mci_base = 0;
 
+static unsigned char ext_csd_buf[512];
+static unsigned char wp_status_buf[8];
+
 int mmc_clock_enable_disable(unsigned id, unsigned enable);
 int mmc_clock_get_rate(unsigned id);
 int mmc_clock_set_rate(unsigned id, unsigned rate);
@@ -71,9 +74,10 @@
 struct mmc_boot_card mmc_card;
 struct mbr_entry mbr[MAX_PARTITIONS];
 unsigned mmc_partition_count = 0;
+
 static void mbr_fill_name (struct mbr_entry *mbr_ent, unsigned int type);
 unsigned int mmc_read (unsigned long long data_addr, unsigned int* out, unsigned int data_len);
-
+static unsigned int mmc_wp(unsigned int addr, unsigned int size, unsigned char set_clear_wp);
 
 unsigned int SWAP_ENDIAN(unsigned int val)
 {
@@ -324,6 +328,13 @@
         card->capacity = mmc_temp * mmc_csd.read_blk_len;
     }
 
+    mmc_csd.erase_grp_size = UNPACK_BITS( raw_csd, 42, 5, mmc_sizeof );
+    mmc_csd.erase_grp_mult = UNPACK_BITS( raw_csd, 37, 5, mmc_sizeof );
+    mmc_csd.wp_grp_size = UNPACK_BITS( raw_csd, 32, 5, mmc_sizeof );
+    mmc_csd.wp_grp_enable = UNPACK_BITS( raw_csd, 31, 1, mmc_sizeof );
+    mmc_csd.perm_wp = UNPACK_BITS( raw_csd, 13, 1, mmc_sizeof );
+    mmc_csd.temp_wp = UNPACK_BITS( raw_csd, 12, 1, mmc_sizeof );
+
     /* save the information in card structure */
     memcpy( (struct mmc_boot_csd *)&card->csd, (struct mmc_boot_csd *)&mmc_csd,
             sizeof(struct mmc_boot_csd) );
@@ -445,7 +456,7 @@
     }
 
     /* 2f. Set ENABLE bit to 1 */
-    mmc_cmd |= MMC_BOT_MCI_CMD_ENABLE;
+    mmc_cmd |= MMC_BOOT_MCI_CMD_ENABLE;
 
     /* 2g. Set PROG_ENA bit to 1 for CMD12, CMD13 issued at the end of
        write data transfer */
@@ -947,24 +958,69 @@
         return mmc_ret;
     }
 
+    /* Checking ADDR_OUT_OF_RANGE error in CMD13 response */
+    if(IS_ADDR_OUT_OF_RANGE(cmd.resp[0]))
+    {
+        return MMC_BOOT_E_FAILURE;
+    }
+
     *status = cmd.resp[0];
     return MMC_BOOT_E_SUCCESS;
 }
+
+/*
+ * Decode type of error caused during read and write
+ */
+static unsigned int mmc_boot_status_error(unsigned mmc_status)
+{
+    unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+
+    /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by
+       card/device during the data transfer */
+    if( mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL )
+    {
+        mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL;
+    }
+    /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded
+       the data timeout period without completing the transfer */
+    else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT )
+    {
+        mmc_ret = MMC_BOOT_E_DATA_TIMEOUT;
+    }
+    /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from
+       the card before empty storage for new received data was available.
+       Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
+    else if( mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN )
+    {
+        /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify
+           for now */
+        mmc_ret = MMC_BOOT_E_RX_OVRRUN;
+    }
+    /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send data to
+       the card before new data for sending was available. Verify that bit
+       FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
+    else if( mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN )
+    {
+        /* Note: We've set FLOW_ENA bit in MCI_CLK to 1.so skipping it now*/
+        mmc_ret = MMC_BOOT_E_RX_OVRRUN;
+    }
+    return mmc_ret;
+}
+
 /*
  * Send ext csd command.
  */
-static unsigned int mmc_boot_send_ext_cmd (struct mmc_boot_card* card)
+static unsigned int mmc_boot_send_ext_cmd (struct mmc_boot_card* card, unsigned char* buf)
 {
     struct mmc_boot_command cmd;
     unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
     unsigned int mmc_reg = 0;
-    unsigned char buf[512];
     unsigned int mmc_status = 0;
     unsigned int* mmc_ptr = (unsigned int *)buf;
     unsigned int mmc_count = 0;
+    unsigned int read_error;
 
-    // start from the back
-    mmc_ptr += ( (512/sizeof(int)) - 1 );
+    memset(buf,0, 512);
 
     /* basic check */
     if( card == NULL )
@@ -973,12 +1029,15 @@
     }
 
     /* set block len */
-    mmc_ret = mmc_boot_set_block_len( card, 512);
-    if( mmc_ret != MMC_BOOT_E_SUCCESS )
+    if( (card->type != MMC_BOOT_TYPE_MMCHC) && (card->type != MMC_BOOT_TYPE_SDHC) )
     {
-        dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
-                mmc_ret, (char *)(card->rca) );
-        return mmc_ret;
+        mmc_ret = mmc_boot_set_block_len( card, 512);
+        if( mmc_ret != MMC_BOOT_E_SUCCESS )
+        {
+            dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card (RCA:%s)\n",
+                    mmc_ret, (char *)(card->rca) );
+            return mmc_ret;
+        }
     }
 
     /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
@@ -1012,46 +1071,44 @@
         return mmc_ret;
     }
 
+    read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | \
+                 MMC_BOOT_MCI_STAT_DATA_TIMEOUT  | \
+                 MMC_BOOT_MCI_STAT_RX_OVRRUN;
+
+    /* Read the transfer data from SDCC2 FIFO. If Data Mover is not used
+       read the data from the MCI_FIFO register as long as RXDATA_AVLBL
+       bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL,
+       DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0.
+       Continue the reads until the whole transfer data is received */
+
     do
     {
         mmc_ret = MMC_BOOT_E_SUCCESS;
         mmc_status = readl( MMC_BOOT_MCI_STATUS );
 
-        /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by
-           card/device during the data transfer */
-        if( mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL )
+        if( mmc_status & read_error )
         {
-            mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL;
-            break;
-        }
-        /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded
-           the data timeout period without completing the transfer */
-        else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT )
-        {
-            mmc_ret = MMC_BOOT_E_DATA_TIMEOUT;
-            break;
-        }
-        /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from
-           the card before empty storage for new received data was available.
-           Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
-        else if( mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN )
-        {
-            /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify
-               for now */
-            mmc_ret = MMC_BOOT_E_RX_OVRRUN;
+            mmc_ret = mmc_boot_status_error(mmc_status);
             break;
         }
 
         if( mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL )
         {
-            /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
-            *mmc_ptr = SWAP_ENDIAN(readl( MMC_BOOT_MCI_FIFO +
-                        ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) ));
-            mmc_ptr--;
+            unsigned read_count = 1;
+            if ( mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL)
+            {
+                read_count = MMC_BOOT_MCI_HFIFO_COUNT;
+            }
 
-            /* increase mmc_count by word size */
-            mmc_count += sizeof( unsigned int );
-
+            for (int i=0; i<read_count; i++)
+            {
+                /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
+                *mmc_ptr = readl( MMC_BOOT_MCI_FIFO +
+                        ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
+                mmc_ptr++;
+                /* increase mmc_count by word size */
+                mmc_count += sizeof( unsigned int );
+            }
             /* quit if we have read enough of data */
             if (mmc_count >= 512)
                 break;
@@ -1060,15 +1117,12 @@
         {
             break;
         }
-
     }while(1);
 
     return MMC_BOOT_E_SUCCESS;
 
 }
 
-
-
 /*
  * Switch command
  */
@@ -1130,7 +1184,7 @@
         mmc_width = width-1;
     }
 
-    mmc_boot_send_ext_cmd (card);
+    mmc_boot_send_ext_cmd (card, ext_csd_buf);
 
     do
     {
@@ -1295,44 +1349,6 @@
     return MMC_BOOT_E_SUCCESS;
 }
 
-/*
- * Decode type of error caused during read and write
- */
-static unsigned int mmc_boot_status_error(unsigned mmc_status)
-{
-    unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
-
-    /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by
-       card/device during the data transfer */
-    if( mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL )
-    {
-        mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL;
-    }
-    /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded
-       the data timeout period without completing the transfer */
-    else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT )
-    {
-        mmc_ret = MMC_BOOT_E_DATA_TIMEOUT;
-    }
-    /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from
-       the card before empty storage for new received data was available.
-       Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
-    else if( mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN )
-    {
-        /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify
-           for now */
-        mmc_ret = MMC_BOOT_E_RX_OVRRUN;
-    }
-    /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send data to
-       the card before new data for sending was available. Verify that bit
-       FLOW_ENA in MCI_CLK is set to 1 during the data xfer.*/
-    else if( mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN )
-    {
-        /* Note: We've set FLOW_ENA bit in MCI_CLK to 1.so skipping it now*/
-        mmc_ret = MMC_BOOT_E_RX_OVRRUN;
-    }
-    return mmc_ret;
-}
 
 /*
  * Write data_len data to address specified by data_addr. data_len is
@@ -1474,6 +1490,9 @@
     {
         dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
                 Card(RCA:%x)\n", mmc_ret, card->rca );
+        /* In case of any failure happening for multi block transfer */
+        if( xfer_type == MMC_BOOT_XFER_MULTI_BLOCK )
+            mmc_boot_send_stop_transmission( card, 1 );
         return mmc_ret;
     }
 
@@ -1526,7 +1545,7 @@
 {
     int mmc_ret;
 
-    mmc_boot_send_ext_cmd (card);
+    mmc_boot_send_ext_cmd (card, ext_csd_buf);
 
     /* Setting HS_TIMING in EXT_CSD (CMD6) */
     mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, MMC_BOOT_EXT_CMMC_HS_TIMING, 1);
@@ -2262,6 +2281,7 @@
     return ret;
 }
 
+
 /*
  * Entry point to MMC boot process
  */
@@ -2296,6 +2316,9 @@
         return MMC_BOOT_E_FAILURE;
     }
 
+    mmc_display_csd();
+    mmc_display_ext_csd();
+
     /* Read MBR of the card */
     mmc_ret = mmc_boot_read_MBR();
     if( mmc_ret != MMC_BOOT_E_SUCCESS )
@@ -2430,3 +2453,325 @@
     }
     return 0;
 }
+
+/*
+ * Function to read registers from MMC or SD card
+ */
+static unsigned int mmc_boot_read_reg(struct mmc_boot_card *card,
+                                      unsigned int data_len,
+                                      unsigned int command, unsigned int addr,
+                                      unsigned int *out)
+{
+    struct mmc_boot_command cmd;
+    unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+    unsigned int mmc_status = 0;
+    unsigned int* mmc_ptr = out;
+    unsigned int mmc_count = 0;
+    unsigned int mmc_reg = 0;
+    unsigned int xfer_type;
+    unsigned int read_error;
+
+    /* Set the FLOW_ENA bit of MCI_CLK register to 1 */
+    mmc_reg = readl( MMC_BOOT_MCI_CLK );
+    mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW ;
+    writel( mmc_reg, MMC_BOOT_MCI_CLK );
+
+    /* Write data timeout period to MCI_DATA_TIMER register. */
+    /* Data timeout period should be in card bus clock periods */
+    mmc_reg =0xFFFFFFFF;
+    writel( mmc_reg, MMC_BOOT_MCI_DATA_TIMER );
+    writel( data_len, MMC_BOOT_MCI_DATA_LENGTH );
+
+    /* Set appropriate fields and write the MCI_DATA_CTL register. */
+    /* Set ENABLE bit to 1 to enable the data transfer. */
+    mmc_reg = MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (data_len << MMC_BOOT_MCI_BLKSIZE_POS);
+    writel( mmc_reg, MMC_BOOT_MCI_DATA_CTL );
+
+    memset( (struct mmc_boot_command *)&cmd, 0,
+            sizeof(struct mmc_boot_command) );
+
+    cmd.cmd_index = command;
+    cmd.argument = addr;
+    cmd.cmd_type  = MMC_BOOT_CMD_ADDRESS;
+    cmd.resp_type = MMC_BOOT_RESP_R1;
+
+    /* send command */
+    mmc_ret = mmc_boot_send_command( &cmd );
+    if( mmc_ret != MMC_BOOT_E_SUCCESS )
+    {
+        return mmc_ret;
+    }
+
+    read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | \
+                 MMC_BOOT_MCI_STAT_DATA_TIMEOUT  | \
+                 MMC_BOOT_MCI_STAT_RX_OVRRUN;
+
+    do
+    {
+        mmc_ret = MMC_BOOT_E_SUCCESS;
+        mmc_status = readl( MMC_BOOT_MCI_STATUS );
+
+        if( mmc_status & read_error )
+        {
+            mmc_ret = mmc_boot_status_error(mmc_status);
+            break;
+        }
+
+        if( mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL )
+        {
+            unsigned read_count = 1;
+            if ( mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL)
+            {
+                read_count = MMC_BOOT_MCI_HFIFO_COUNT;
+            }
+
+            for (int i=0; i<read_count; i++)
+            {
+                /* FIFO contains 16 32-bit data buffer on 16 sequential addresses*/
+                *mmc_ptr = readl( MMC_BOOT_MCI_FIFO +
+                        ( mmc_count % MMC_BOOT_MCI_FIFO_SIZE ) );
+                mmc_ptr++;
+                /* increase mmc_count by word size */
+                mmc_count += sizeof( unsigned int );
+            }
+            /* quit if we have read enough of data */
+            if (mmc_count == data_len)
+                break;
+        }
+        else if( mmc_status & MMC_BOOT_MCI_STAT_DATA_END )
+        {
+            break;
+        }
+    }while(1);
+
+    if( mmc_ret != MMC_BOOT_E_SUCCESS )
+    {
+        dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \
+                Card(RCA:%x)\n", mmc_ret, card->rca );
+        return mmc_ret;
+    }
+
+    return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Function to set/clear power-on write protection for the user area partitions
+ */
+static unsigned int mmc_boot_set_clr_power_on_wp_user(struct mmc_boot_card* card,
+                                                      unsigned int addr,
+                                                      unsigned int size,
+                                                      unsigned char set_clear_wp)
+{
+    struct mmc_boot_command cmd;
+    unsigned int mmc_ret = MMC_BOOT_E_SUCCESS;
+    unsigned int wp_group_size, loop_count;
+    unsigned int status;
+
+    memset( (struct mmc_boot_command *)&cmd, 0,
+            sizeof(struct mmc_boot_command) );
+
+    /* Disabling PERM_WP for USER AREA (CMD6) */
+    mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+                                  MMC_BOOT_EXT_USER_WP,
+                                  MMC_BOOT_US_PERM_WP_DIS);
+
+    if(mmc_ret != MMC_BOOT_E_SUCCESS)
+    {
+        return mmc_ret;
+    }
+
+    /* Sending CMD13 to check card status */
+    do
+    {
+        mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
+        if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+            break;
+    } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
+        (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+    if( mmc_ret != MMC_BOOT_E_SUCCESS )
+    {
+        return mmc_ret;
+    }
+
+    mmc_ret = mmc_boot_send_ext_cmd (card,ext_csd_buf);
+
+    if(mmc_ret != MMC_BOOT_E_SUCCESS)
+    {
+        return mmc_ret;
+    }
+
+    /* Make sure power-on write protection for user area is not disabled
+       and permanent write protection for user area is not enabled */
+
+    if((IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PERM_WP_EN)) ||
+       (IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PWR_WP_DIS)))
+    {
+        return MMC_BOOT_E_FAILURE;
+    }
+
+    if(ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF])
+    {
+        /* wp_group_size = 512KB * HC_WP_GRP_SIZE * HC_ERASE_GRP_SIZE.
+           Getting write protect group size in sectors here. */
+
+        wp_group_size = (512*1024) * ext_csd_buf[MMC_BOOT_EXT_HC_WP_GRP_SIZE] *
+                    ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] /
+                    MMC_BOOT_WR_BLOCK_LEN;
+    }
+    else
+    {
+        /* wp_group_size = (WP_GRP_SIZE + 1) * (ERASE_GRP_SIZE + 1)
+                                             * (ERASE_GRP_MULT + 1).
+           This is defined as the number of write blocks directly */
+
+        wp_group_size = (card->csd.erase_grp_size + 1) *
+                    (card->csd.erase_grp_mult + 1) *
+                    (card->csd.wp_grp_size + 1);
+    }
+
+    if(wp_group_size == 0)
+    {
+        return MMC_BOOT_E_FAILURE;
+    }
+
+    /* Setting POWER_ON_WP for USER AREA (CMD6) */
+
+    mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE,
+                                  MMC_BOOT_EXT_USER_WP,
+                                  MMC_BOOT_US_PWR_WP_EN);
+
+    if(mmc_ret != MMC_BOOT_E_SUCCESS)
+    {
+        return mmc_ret;
+    }
+
+    /* Sending CMD13 to check card status */
+    do
+    {
+        mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
+        if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+            break;
+    } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
+        (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+    if( mmc_ret != MMC_BOOT_E_SUCCESS )
+    {
+        return mmc_ret;
+    }
+
+    /* Calculating the loop count for sending SET_WRITE_PROTECT (CMD28)
+       or CLEAR_WRITE_PROTECT (CMD29).
+       We are write protecting the partitions in blocks of write protect
+       group sizes only */
+
+    if(size % wp_group_size)
+    {
+        loop_count = (size / wp_group_size) + 1;
+    }
+    else
+    {
+        loop_count = (size / wp_group_size);
+    }
+
+    if(set_clear_wp)
+        cmd.cmd_index = CMD28_SET_WRITE_PROTECT;
+    else
+        cmd.cmd_index = CMD29_CLEAR_WRITE_PROTECT;
+
+    cmd.cmd_type = MMC_BOOT_CMD_ADDRESS;
+    cmd.resp_type = MMC_BOOT_RESP_R1B;
+
+    for(int i=0;i<loop_count;i++)
+    {
+        /* Sending CMD28 for each WP group size
+           address is in sectors already */
+        cmd.argument = (addr + (i * wp_group_size));
+
+        mmc_ret = mmc_boot_send_command( &cmd );
+
+        if(mmc_ret != MMC_BOOT_E_SUCCESS)
+        {
+            return mmc_ret;
+        }
+
+        /* Checking ADDR_OUT_OF_RANGE error in CMD28 response */
+        if(IS_ADDR_OUT_OF_RANGE(cmd.resp[0]))
+        {
+            return MMC_BOOT_E_FAILURE;
+        }
+
+        /* Sending CMD13 to check card status */
+        do
+        {
+            mmc_ret = mmc_boot_get_card_status( card, 0 ,&status);
+            if(MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE)
+                break;
+        } while( (mmc_ret == MMC_BOOT_E_SUCCESS) &&
+            (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE));
+
+        if( mmc_ret != MMC_BOOT_E_SUCCESS )
+        {
+            return mmc_ret;
+        }
+    }
+
+    return MMC_BOOT_E_SUCCESS;
+}
+
+/*
+ * Function to get Write Protect status of the given sector
+ */
+static unsigned int mmc_boot_get_wp_status (struct mmc_boot_card* card,
+                                            unsigned int sector)
+{
+    unsigned int rc = MMC_BOOT_E_SUCCESS;
+    memset(wp_status_buf,0, 8);
+
+    rc = mmc_boot_read_reg(card,8,CMD31_SEND_WRITE_PROT_TYPE,sector,wp_status_buf);
+
+    return rc;
+}
+
+/*
+ * Test Function for setting Write protect for given sector
+ */
+static unsigned int mmc_wp(unsigned int sector, unsigned int size,
+                           unsigned char set_clear_wp)
+{
+    unsigned int rc = MMC_BOOT_E_SUCCESS;
+
+    /* Checking whether group write protection feature is available */
+    if(mmc_card.csd.wp_grp_enable)
+    {
+        rc = mmc_boot_get_wp_status(&mmc_card,sector);
+        rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card,sector,size,set_clear_wp);
+        rc = mmc_boot_get_wp_status(&mmc_card,sector);
+        return rc;
+    }
+    else
+        return MMC_BOOT_E_FAILURE;
+}
+
+void mmc_wp_test(void)
+{
+    unsigned int mmc_ret=0;
+    mmc_ret = mmc_wp(0xE06000,0x5000,1);
+}
+
+void mmc_display_ext_csd(void)
+{
+    dprintf(ALWAYS,  "part_config: %x\n", ext_csd_buf[179] );
+    dprintf(ALWAYS,  "erase_group_def: %x\n", ext_csd_buf[175] );
+    dprintf(ALWAYS,  "user_wp: %x\n", ext_csd_buf[171] );
+}
+
+void mmc_display_csd(void)
+{
+    dprintf(ALWAYS,  "erase_grpsize: %d\n", mmc_card.csd.erase_grp_size );
+    dprintf(ALWAYS,  "erase_grpmult: %d\n", mmc_card.csd.erase_grp_mult );
+    dprintf(ALWAYS,  "wp_grpsize: %d\n", mmc_card.csd.wp_grp_size );
+    dprintf(ALWAYS,  "wp_grpen: %d\n", mmc_card.csd.wp_grp_enable );
+    dprintf(ALWAYS,  "perm_wp: %d\n", mmc_card.csd.perm_wp );
+    dprintf(ALWAYS,  "temp_wp: %d\n", mmc_card.csd.temp_wp );
+}
diff --git a/target/msm8660_surf/include/target/display.h b/target/msm8660_surf/include/target/display.h
index 924d02a..1a1eab0 100644
--- a/target/msm8660_surf/include/target/display.h
+++ b/target/msm8660_surf/include/target/display.h
@@ -48,6 +48,10 @@
 #define TSH_MIPI_FB_WIDTH            480
 #define TSH_MIPI_FB_HEIGHT           854
 
+/* NOVATEK MIPI panel */
+#define NOV_MIPI_FB_WIDTH            540
+#define NOV_MIPI_FB_HEIGHT           960
+
 #define MIPI_HSYNC_PULSE_WIDTH       50
 #define MIPI_HSYNC_BACK_PORCH_DCLK   500
 #define MIPI_HSYNC_FRONT_PORCH_DCLK  500
diff --git a/target/msm8660_surf/rules.mk b/target/msm8660_surf/rules.mk
index 16a9413..960d8be 100755
--- a/target/msm8660_surf/rules.mk
+++ b/target/msm8660_surf/rules.mk
@@ -19,6 +19,8 @@
 DEFINES += DISPLAY_SPLASH_SCREEN=1
 DEFINES += DISPLAY_TYPE_LCDC=1
 DEFINES += DISPLAY_TYPE_MIPI=0
+DEFINES += DISPLAY_MIPI_PANEL_NOVATEK_BLUE=0
+DEFINES += DISPLAY_MIPI_PANEL_TOSHIBA=0
 
 MODULES += \
 	dev/keys \