diff --git a/platform/msm_shared/include/qusb2_phy.h b/platform/msm_shared/include/qusb2_phy.h
index fc971c8..d3ed338 100644
--- a/platform/msm_shared/include/qusb2_phy.h
+++ b/platform/msm_shared/include/qusb2_phy.h
@@ -32,6 +32,8 @@
 
 void qusb2_phy_reset(void);
 
+#define QUSB2PHY_PLL_LOCK        0x20
+
 #define QUSB2PHY_PORT_POWERDOWN     (QUSB2_PHY_BASE + 0x000000B4)
 #define QUSB2PHY_PORT_UTMI_CTRL2    (QUSB2_PHY_BASE + 0x000000C4)
 #define QUSB2PHY_PLL_TEST           (QUSB2_PHY_BASE + 0x00000004)
@@ -45,6 +47,7 @@
 #define QUSB2PHY_PORT_TEST2         (QUSB2_PHY_BASE + 0x0000009C)
 #define QUSB2PHY_PLL_PWR_CTL        (QUSB2_PHY_BASE + 0x00000018)
 #define QUSB2PHY_PLL_AUTOPGM_CTL1   (QUSB2_PHY_BASE + 0x0000001C)
+#define QUSB2PHY_PLL_STATUS         (QUSB2_PHY_BASE + 0x00000038)
 
 
 #endif
diff --git a/platform/msm_shared/qusb2_phy.c b/platform/msm_shared/qusb2_phy.c
index 8981df7..edc0ecc 100644
--- a/platform/msm_shared/qusb2_phy.c
+++ b/platform/msm_shared/qusb2_phy.c
@@ -49,6 +49,11 @@
 	/* Default tune value */
 	uint8_t tune2 = 0xB3;
 
+	/* Disable the ref clock before phy reset */
+#if GCC_RX2_USB2_CLKREF_EN
+	writel((readl(GCC_RX2_USB2_CLKREF_EN) & ~0x1), GCC_RX2_USB2_CLKREF_EN);
+	dmb();
+#endif
 	/* Block Reset */
 	val = readl(GCC_QUSB2_PHY_BCR) | BIT(0);
 	writel(val, GCC_QUSB2_PHY_BCR);
@@ -113,4 +118,16 @@
 	/* Enable PHY */
 	/* set CLAMP_N_EN and USB PHY is enabled*/
 	writel(0x22, QUSB2PHY_PORT_POWERDOWN);
+	udelay(150);
+
+	/* Check PLL status */
+	if (!(readl(QUSB2PHY_PLL_STATUS) & QUSB2PHY_PLL_LOCK))
+	{
+		dprintf(CRITICAL, "QUSB2PHY failed to lock: %d", readl(QUSB2PHY_PLL_STATUS));
+	}
+
+#if GCC_RX2_USB2_CLKREF_EN
+	writel((readl(GCC_RX2_USB2_CLKREF_EN) | 0x1), GCC_RX2_USB2_CLKREF_EN);
+	dmb();
+#endif
 }