platform: msm8996: add HDMI related clocks
Add hdmi core, ahb and pixel clocks to support HDMI interface.
Change-Id: I3db7915b25f8b29153a17a38ec5d9728575a19a7
diff --git a/platform/msm8996/msm8996-clock.c b/platform/msm8996/msm8996-clock.c
index 782a624..5856210 100644
--- a/platform/msm8996/msm8996-clock.c
+++ b/platform/msm8996/msm8996-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -46,6 +46,7 @@
#define mmpll1_mm_source_val 2
#define mmpll3_mm_source_val 3
#define gpll0_mm_source_val 5
+#define hdmipll_mm_source_val 3
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -728,6 +729,77 @@
},
};
+static struct branch_clk mdss_hdmi_ahb_clk = {
+ .cbcr_reg = (uint32_t *) MDSS_HDMI_AHB_CBCR,
+ .has_sibling = 1,
+ .c = {
+ .dbg_name = "mdss_hdmi_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_hdmi_clk[] = {
+ F_MM( 19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk hdmi_clk_src = {
+ .cmd_reg = (uint32_t *) HDMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) HDMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_hdmi_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "hdmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_hdmi_clk = {
+ .cbcr_reg = (uint32_t *) MDSS_HDMI_CBCR,
+ .has_sibling = 0,
+ .parent = &hdmi_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_hdmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_extpclk_clk[] = {
+ F_MDSS( 74250000, hdmipll, 1, 0, 0),
+ F_MDSS( 25200000, hdmipll, 1, 0, 0),
+ F_MDSS( 27000000, hdmipll, 1, 0, 0),
+ F_MDSS( 27030000, hdmipll, 1, 0, 0),
+ F_MDSS( 27070000, hdmipll, 1, 0, 0),
+ F_MDSS( 65000000, hdmipll, 1, 0, 0),
+ F_MDSS(108000000, hdmipll, 1, 0, 0),
+ F_MDSS(148500000, hdmipll, 1, 0, 0),
+ F_MDSS(268500000, hdmipll, 1, 0, 0),
+ F_MDSS(297000000, hdmipll, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk extpclk_clk_src = {
+ .cmd_reg = (uint32_t *) EXTPCLK_CMD_RCGR,
+ .cfg_reg = (uint32_t *) EXTPCLK_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_extpclk_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "extpclk_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_extpclk_clk = {
+ .cbcr_reg = (uint32_t *) MDSS_EXTPCLK_CBCR,
+ .has_sibling = 0,
+ .parent = &extpclk_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_extpclk_clk",
+ .ops = &clk_ops_branch,
+ },
+};
/* Clock lookup table */
static struct clk_lookup msm_msm8996_clocks[] =
@@ -772,6 +844,11 @@
gcc_blsp2_qup2_i2c_apps_clk_src.c),
CLK_LOOKUP("gcc_blsp2_qup2_i2c_apps_clk",
gcc_blsp2_qup2_i2c_apps_clk.c),
+
+ /* HDMI clocks*/
+ CLK_LOOKUP("hdmi_ahb_clk", mdss_hdmi_ahb_clk.c),
+ CLK_LOOKUP("hdmi_core_clk", mdss_hdmi_clk.c),
+ CLK_LOOKUP("hdmi_extp_clk", mdss_extpclk_clk.c),
};
void platform_clock_init(void)