pm8x41: Adding support for output pmic gpios
Output configuration for pm8x41 was not implemented.
Change-Id: I71d98b742f0241885f8583122382458fe5ba20e2
diff --git a/dev/pmic/pm8x41/pm8x41.c b/dev/pmic/pm8x41/pm8x41.c
index c547a75..39d4000 100644
--- a/dev/pmic/pm8x41/pm8x41.c
+++ b/dev/pmic/pm8x41/pm8x41.c
@@ -95,9 +95,6 @@
uint8_t val;
uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
- /* Only input configuration is implemented at this time. */
- ASSERT(config->direction == PM_GPIO_DIR_IN);
-
/* Disable the GPIO */
val = REG_READ(gpio_base + GPIO_EN_CTL);
val &= ~BIT(PERPH_EN_BIT);
@@ -115,12 +112,18 @@
val = config->vin_sel;
REG_WRITE(gpio_base + GPIO_DIG_VIN_CTL, val);
+ if (config->direction == PM_GPIO_DIR_OUT) {
+ /* Set the right dig out control */
+ val = config->out_strength | (config->output_buffer << 4);
+ REG_WRITE(gpio_base + GPIO_DIG_OUT_CTL, val);
+ }
+
/* Enable the GPIO */
val = REG_READ(gpio_base + GPIO_EN_CTL);
val |= BIT(PERPH_EN_BIT);
REG_WRITE(gpio_base + GPIO_EN_CTL, val);
- return 1;
+ return 0;
}
/* Reads the status of requested gpio */
@@ -135,7 +138,21 @@
dprintf(SPEW, "GPIO %d status is %d\n", gpio, *status);
- return 1;
+ return 0;
+}
+
+/* Write the output value of the requested gpio */
+int pm8x41_gpio_set(uint8_t gpio, uint8_t value)
+{
+ uint32_t gpio_base = GPIO_N_PERIPHERAL_BASE(gpio);
+ uint8_t val;
+
+ /* Set the output value of the gpio */
+ val = REG_READ(gpio_base + GPIO_MODE_CTL);
+ val = (val & ~PM_GPIO_OUTPUT_MASK) | value;
+ REG_WRITE(gpio_base + GPIO_MODE_CTL, val);
+
+ return 0;
}
/* Prepare PON RESIN S2 reset */