apq8084: Add support for SD card
CRs-Fixed: 573205
Change-Id: I3c278f5781c6fbcc5ceddc7e2a90e048160ba86a
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 4608432..873eeda 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -136,10 +136,14 @@
{
ret = clk_get_set_enable(clk_name, 100000000, 1);
}
- else if(freq == MMC_CLK_200MHZ)
+ else if(freq == MMC_CLK_192MHZ)
{
ret = clk_get_set_enable(clk_name, 192000000, 1);
}
+ else if(freq == MMC_CLK_200MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 200000000, 1);
+ }
else if(freq == MMC_CLK_400MHZ)
{
ret = clk_get_set_enable(clk_name, 384000000, 1);
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index 06d94db..cedafec 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -243,7 +243,7 @@
};
/* SDCC Clocks */
-static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
+static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] =
{
F( 144000, cxo, 16, 3, 25),
F( 400000, cxo, 12, 1, 4),
@@ -256,6 +256,18 @@
F_END
};
+static struct clk_freq_tbl ftbl_gcc_sdcc2_4_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F(100000000, gpll0, 6, 0, 0),
+ F(200000000, gpll0, 3, 0, 0),
+ F_END
+};
+
static struct rcg_clk sdcc1_apps_clk_src =
{
.cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
@@ -265,7 +277,7 @@
.d_reg = (uint32_t *) SDCC1_D,
.set_rate = clock_lib2_rcg_set_rate_mnd,
- .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
.current_freq = &rcg_dummy_freq,
.c = {
@@ -296,6 +308,46 @@
},
};
+static struct rcg_clk sdcc2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC2_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC2_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC2_M,
+ .n_reg = (uint32_t *) SDCC2_N,
+ .d_reg = (uint32_t *) SDCC2_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc2_4_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc2_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_APPS_CBCR,
+ .parent = &sdcc2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc2_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC2_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
/* USB 3.0 Clocks */
static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
{
@@ -557,6 +609,9 @@
CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+ CLK_LOOKUP("sdc2_iface_clk", gcc_sdcc2_ahb_clk.c),
+ CLK_LOOKUP("sdc2_core_clk", gcc_sdcc2_apps_clk.c),
+
CLK_LOOKUP("gcc_sdcc1_cdccal_sleep_clk", gcc_sdcc1_cdccal_sleep_clk.c),
CLK_LOOKUP("gcc_sdcc1_cdccal_ff_clk", gcc_sdcc1_cdccal_ff_clk.c),
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index 78a0f26..b09e214 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -100,7 +100,18 @@
#define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490)
#define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494)
-/* SDCC */
+/* SDCC2 */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508)
+#define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */
+
+/* SDCC1 */
#define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */
#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */
#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8)
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index 17dad46..c5a5ee5 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -206,21 +206,22 @@
set_sdc_power_ctrl();
config.bus_width = DATA_BUS_WIDTH_8BIT;
- config.max_clk_rate = MMC_CLK_200MHZ;
/* Try slot 1*/
config.slot = 1;
- config.sdhc_base = mmc_sdhci_base[config.slot - 1];
- config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
- config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.max_clk_rate = MMC_CLK_192MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
if (!(dev = mmc_init(&config)))
{
/* Try slot 2 */
config.slot = 2;
- config.sdhc_base = mmc_sdhci_base[config.slot - 1];
- config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
- config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
+ config.max_clk_rate = MMC_CLK_200MHZ;
+ config.sdhc_base = mmc_sdhci_base[config.slot - 1];
+ config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
+ config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
if (!(dev = mmc_init(&config)))
{