platform: msm8916: Add support for dual_dsi in 8916/8939
Enable support for DSI 1 interface on 8916/8939. This is to
support the dual dsi on the target. Add support for DSI 1 byte,
pixel and esc clocks along with correct base addresses for
DSI 1 interface. Add register settings for enabling split
display and destination split on 8916/8939.
Change-Id: I85bdc3cce504bce2b6faca06a6d55dd599018536
diff --git a/platform/msm8916/acpuclock.c b/platform/msm8916/acpuclock.c
index 5b08c53..bcc65f0 100644
--- a/platform/msm8916/acpuclock.c
+++ b/platform/msm8916/acpuclock.c
@@ -263,15 +263,20 @@
}
/* Disable all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_disable(void)
+void gcc_dsi_clocks_disable(uint8_t dual_dsi)
{
clk_disable(clk_get("mdss_esc0_clk"));
writel(0x0, DSI_PIXEL0_CBCR);
writel(0x0, DSI_BYTE0_CBCR);
+ if (dual_dsi) {
+ clk_disable(clk_get("mdss_esc1_clk"));
+ writel(0x0, DSI_PIXEL1_CBCR);
+ writel(0x0, DSI_BYTE1_CBCR);
+ }
}
/* Configure all the branch clocks needed by the DSI controller */
-void gcc_dsi_clocks_enable(uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
+void gcc_dsi_clocks_enable(uint8_t dual_dsi, uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
{
int ret;
@@ -296,6 +301,30 @@
dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
ASSERT(0);
}
+
+ if (dual_dsi) {
+ /* Configure Byte clock -autopll- This will not change becasue
+ byte clock does not need any divider*/
+ writel(0x100, DSI_BYTE1_CFG_RCGR);
+ writel(0x1, DSI_BYTE1_CMD_RCGR);
+ writel(0x1, DSI_BYTE1_CBCR);
+
+ /* Configure Pixel clock */
+ writel(0x100, DSI_PIXEL1_CFG_RCGR);
+ writel(0x1, DSI_PIXEL1_CMD_RCGR);
+ writel(0x1, DSI_PIXEL1_CBCR);
+
+ writel(pclk0_m, DSI_PIXEL1_M);
+ writel(pclk0_n, DSI_PIXEL1_N);
+ writel(pclk0_d, DSI_PIXEL1_D);
+
+ /* Configure ESC clock */
+ ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
+ if (ret) {
+ dprintf(CRITICAL, "failed to set esc1_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+ }
}
/* Function to asynchronously reset CE.