platform: uart: disable IRQ while UART sending data
To send some bytes by UART, we program the DM_NO_CHARS_FOR_TX
register to tell UART FSM how many data we have. Then we write
the data to the DM_TF register one by one. Once the number we
write to the DM_TF is equal to DM_NO_CHARS_FOR_TX, TX_RDY signal
will be set. And we send the data successfully.
Consider this scenario, the flow is aborted, by the X IRQ,
in the following position:
...
check TX_RDY signal
...
write DM_NO_CHARS_FOR_TX
... ---------->aborted by X IRQ
write DM_TF
...
And the X IRQ handler also wants to send out some data by UART.
Then the IRQ handler will hang at the TX_RDY checking. Because
the TX_RDY never arrives if the previous flow doesn't finish.
CRs-Fixed: 637800
Change-Id: I6d518a503eb23e02e634f64b06a7f9e22e9d4456
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index f551a7a..c92a34f 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -29,6 +29,7 @@
#include <string.h>
#include <stdlib.h>
#include <debug.h>
+#include <kernel/thread.h>
#include <reg.h>
#include <sys/types.h>
#include <platform/iomap.h>
@@ -339,6 +340,8 @@
}
}
+ //We need to make sure the DM_NO_CHARS_FOR_TX&DM_TF are are programmed atmoically.
+ enter_critical_section();
/* We are here. FIFO is ready to be written. */
/* Write number of characters to be written */
writel(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base));
@@ -366,6 +369,7 @@
tx_char_left = num_of_chars - (i + 1) * 4;
tx_data = tx_data + num_chars_written;
}
+ exit_critical_section();
return MSM_BOOT_UART_DM_E_SUCCESS;
}