msm8960: Enabling splash screen for lk
This enables splash screen support in lk for mipi
toshiba mdt61 panel.
Change-Id: Ieb9fcde096aa8c8e55a3ceb88f2fd7513ca7187e
diff --git a/platform/msm8960/acpuclock.c b/platform/msm8960/acpuclock.c
index b2e63bb..6d65504 100644
--- a/platform/msm8960/acpuclock.c
+++ b/platform/msm8960/acpuclock.c
@@ -33,7 +33,6 @@
#include <uart_dm.h>
#include <gsbi.h>
-
/* Set rate and enable the clock */
void clock_config(uint32_t ns, uint32_t md, uint32_t ns_addr, uint32_t md_addr)
{
@@ -44,7 +43,8 @@
writel(val, ns_addr);
/* Write the MD value into the MD register */
- writel(md, md_addr);
+ if (md_addr != 0x0)
+ writel(md, md_addr);
/* Write the ns value, and active reset for M/N Counter, again */
val = 1 << 7;
@@ -73,6 +73,38 @@
writel(val, ns_addr);
}
+/* Write the M,N,D values and enable the MMSS Clocks */
+void config_mmss_clk( uint32_t ns,
+ uint32_t md,
+ uint32_t cc,
+ uint32_t ns_addr,
+ uint32_t md_addr,
+ uint32_t cc_addr){
+ unsigned int val = 0;
+
+ clock_config(ns, md, ns_addr, md_addr);
+
+ /* Enable MND counter */
+ val = cc | (1 << 5);
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Enable the root of the clock tree */
+ val = 1 << 2;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Enable the Pixel Clock */
+ val = 1 << 0;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+
+ /* Force On */
+ val = 1 << 31;
+ val = val | readl(cc_addr);
+ writel(val, cc_addr);
+}
+
void pll8_enable(void)
{
unsigned int curr_value = 0;
@@ -134,3 +166,54 @@
writel(GSBI_HCLK_CTL_CLK_ENA << GSBI_HCLK_CTL_S, GSBIn_HCLK_CTL(id));
}
+void pll1_enable(void){
+ uint32_t val = 0;
+
+ /* Reset MND divider */
+ val |= (1<<2);
+ writel(val, MM_PLL1_MODE_REG);
+
+ /* Use PLL -- Disable Bypass */
+ val |= (1<<1);
+ writel(val, MM_PLL1_MODE_REG);
+
+ /* Activate PLL out control */
+ val |= 1;
+ writel(val, MM_PLL1_MODE_REG);
+
+ while (!readl(MM_PLL1_STATUS_REG));
+}
+
+void config_mdp_lut_clk(void){
+ /* Force on*/
+ writel(MDP_LUT_VAL, MDP_LUT_CC_REG);
+}
+
+/* Turn on MDP related clocks and pll's for MDP */
+void mdp_clock_init(void)
+{
+ /* Turn on the PLL1, as source for MDP clock */
+ pll1_enable();
+
+ /* Turn on MDP clk */
+ config_mmss_clk(MDP_NS_VAL, MDP_MD_VAL,
+ MDP_CC_VAL, MDP_NS_REG, MDP_MD_REG, MDP_CC_REG);
+
+ /* Seems to lose pixels without this from status 0x051E0048 */
+ config_mdp_lut_clk();
+}
+
+/* Initialize all clocks needed by Display */
+void mmss_clock_init(void){
+ /* Configure Pixel clock */
+ config_mmss_clk(PIXEL_NS_VAL, PIXEL_MD_VAL, PIXEL_CC_VAL, PIXEL_NS_REG, PIXEL_MD_REG, PIXEL_CC_REG);
+
+ /* Configure DSI clock */
+ config_mmss_clk(DSI_NS_VAL, DSI_MD_VAL, DSI_CC_VAL, DSI_NS_REG, DSI_MD_REG, DSI_CC_REG);
+
+ /* Configure Byte clock */
+ config_mmss_clk(BYTE_NS_VAL, 0x0, BYTE_CC_VAL, BYTE_NS_REG, 0x0, BYTE_CC_REG);
+
+ /* Configure ESC clock */
+ config_mmss_clk(ESC_NS_VAL, 0x0, ESC_CC_VAL, ESC_NS_REG, 0x0, ESC_CC_REG);
+}