| commit | e5f72cd9d9624b005f3a3370fe5bd6d04b39bc70 | [log] [tgz] |
|---|---|---|
| author | Parth Dixit <parthd@codeaurora.org> | Wed Feb 08 18:17:23 2017 +0530 |
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | Thu Feb 09 06:07:38 2017 -0800 |
| tree | 1f4a815ffe2fec53ae8302eedbc6a0792a427c55 | |
| parent | d5dd9d2c13a3f65c7e3ad0acca2a8edac5b342d5 [diff] |
platform : msm_shared: set REL_WR_SEC_C register to 0x1 per eMMC5.0 spec Some eMMC vendors violate eMMC 5.0 spec and set REL_WR_SEC_C register to 0x10 to indicate the ability of RPMB throughput improvement thus lead to failure when TZ module write data to RPMB partition. This change will check bit[4] of EXT_CSD[166] and if it is not set then change value of REL_WR_SEC_C to 0x1 directly ignoring value of EXT_CSD[222]. Change-Id: I4f90ac6a1f498e38cc148f38afb8274d13df0856