platform: msm_shared: Fix sdcc driver hang issue
If the higher order bootloaders use sdhc mode & LK uses legacy mode
then LK mmc driver hangs in waiting for ready status from controller.
During init sequence of lk legacy mmc driver we should disable sdhc mode
and reset the controller for a clean start.
CRs-Fixed: 596424
Change-Id: I91729af49ccfe0d4e756c4d36f7de23bc0777f80
diff --git a/platform/msm_shared/include/mmc.h b/platform/msm_shared/include/mmc.h
index 15375e4..222c01b 100644
--- a/platform/msm_shared/include/mmc.h
+++ b/platform/msm_shared/include/mmc.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -610,6 +610,14 @@
#define MMC_CLK_ENABLE 1
#define MMC_CLK_DISABLE 0
+/* SDHC mode & core sw reset related macros */
+#define MMC_BOOT_MCI_HC_MODE MMC_BOOT_MCI_REG(0x078)
+#define SDHCI_HC_START_BIT 0x0
+#define SDHCI_HC_WIDTH 0x1
+
+#define CORE_SW_RST_START 0x7
+#define CORE_SW_RST_WIDTH 0x1
+
unsigned int mmc_boot_main(unsigned char slot, unsigned int base);
unsigned int mmc_write(unsigned long long data_addr,
unsigned int data_len, unsigned int *in);
diff --git a/platform/msm_shared/mmc.c b/platform/msm_shared/mmc.c
index 2c9636a..ec6a88b 100644
--- a/platform/msm_shared/mmc.c
+++ b/platform/msm_shared/mmc.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -1905,6 +1905,18 @@
host->ocr = MMC_BOOT_OCR_27_36 | MMC_BOOT_OCR_SEC_MODE;
host->cmd_retry = MMC_BOOT_MAX_COMMAND_RETRY;
+ /* Disable sdhc mode */
+ RMWREG32(MMC_BOOT_MCI_HC_MODE, SDHCI_HC_START_BIT, SDHCI_HC_WIDTH, 0);
+
+ /* Wait for the MMC_BOOT_MCI_POWER write to go through. */
+ mmc_mclk_reg_wr_delay();
+
+ /* Reset controller */
+ RMWREG32(MMC_BOOT_MCI_POWER, CORE_SW_RST_START, CORE_SW_RST_WIDTH, 1);
+
+ /* Wait for the MMC_BOOT_MCI_POWER write to go through. */
+ mmc_mclk_reg_wr_delay();
+
/* Initialize any clocks needed for SDC controller */
clock_init_mmc(mmc_slot);