platform/target: Initial commit for thulium bringup
Add support for target and platform implementation for
thulium.
Change-Id: I4ca7191697ac5a7518dcfadaf812d793e5ce1d48
diff --git a/platform/thulium/acpuclock.c b/platform/thulium/acpuclock.c
new file mode 100644
index 0000000..3b76b91
--- /dev/null
+++ b/platform/thulium/acpuclock.c
@@ -0,0 +1,271 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <debug.h>
+#include <reg.h>
+#include <mmc.h>
+#include <clock.h>
+#include <platform/timer.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+#include <pm8x41.h>
+
+void clock_init_mmc(uint32_t interface)
+{
+ char clk_name[64];
+ int ret;
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_iface_clk", interface);
+
+ /* enable interface clock */
+ ret = clk_get_set_enable(clk_name, 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_iface_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+}
+
+/* Configure MMC clock */
+void clock_config_mmc(uint32_t interface, uint32_t freq)
+{
+ int ret = 0;
+ char clk_name[64];
+
+ snprintf(clk_name, sizeof(clk_name), "sdc%u_core_clk", interface);
+
+ if(freq == MMC_CLK_400KHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 400000, true);
+ }
+ else if(freq == MMC_CLK_50MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 50000000, true);
+ }
+ else if(freq == MMC_CLK_96MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 100000000, true);
+ }
+ else if(freq == MMC_CLK_192MHZ)
+ {
+ ret = clk_get_set_enable(clk_name, 192000000, true);
+ }
+ else
+ {
+ dprintf(CRITICAL, "sdc frequency (%u) is not supported\n", freq);
+ ASSERT(0);
+ }
+
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set sdc%u_core_clk ret = %d\n", interface, ret);
+ ASSERT(0);
+ }
+}
+
+/* Configure UART clock based on the UART block id*/
+void clock_config_uart_dm(uint8_t id)
+{
+ int ret;
+ char iclk[64];
+ char cclk[64];
+
+ snprintf(iclk, sizeof(iclk), "uart%u_iface_clk", id);
+ snprintf(cclk, sizeof(cclk), "uart%u_core_clk", id);
+
+ ret = clk_get_set_enable(iclk, 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_iface_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable(cclk, 7372800, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set uart%u_core_clk ret = %d\n", id, ret);
+ ASSERT(0);
+ }
+}
+
+/* Function to asynchronously reset CE (Crypto Engine).
+ * Function assumes that all the CE clocks are off.
+ */
+static void ce_async_reset(uint8_t instance)
+{
+}
+
+void clock_ce_enable(uint8_t instance)
+{
+}
+
+void clock_ce_disable(uint8_t instance)
+{
+}
+
+void clock_config_ce(uint8_t instance)
+{
+ /* Need to enable the clock before disabling since the clk_disable()
+ * has a check to default to nop when the clk_enable() is not called
+ * on that particular clock.
+ */
+ clock_ce_enable(instance);
+
+ clock_ce_disable(instance);
+
+ ce_async_reset(instance);
+
+ clock_ce_enable(instance);
+
+}
+
+void clock_usb30_gdsc_enable(void)
+{
+ uint32_t reg = readl(GCC_USB30_GDSCR);
+
+ reg &= ~(0x1);
+
+ writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 clocks */
+void clock_usb30_init(void)
+{
+ int ret;
+
+ ret = clk_get_set_enable("usb30_iface_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ clock_usb30_gdsc_enable();
+
+ ret = clk_get_set_enable("usb30_master_clk", 125000000, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_phy_aux_clk", 1200000, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_phy_aux_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_mock_utmi_clk", 60000000, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_mock_utmi_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb30_sleep_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_sleep_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ ret = clk_get_set_enable("usb_phy_cfg_ahb2phy_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to enable usb_phy_cfg_ahb2phy_clk = %d\n", ret);
+ ASSERT(0);
+ }
+
+ pm8x41_lnbb_clock_ctrl(1);
+}
+
+void clock_bumpup_pipe3_clk()
+{
+ int ret = 0;
+
+ ret = clk_get_set_enable("usb30_pipe_clk", 0, true);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set usb30_pipe_clk. ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ return;
+}
+
+void clock_reset_usb_phy()
+{
+ int ret;
+
+ struct clk *phy_reset_clk = NULL;
+ struct clk *pipe_reset_clk = NULL;
+
+ /* Look if phy com clock is present */
+ phy_reset_clk = clk_get("usb30_phy_reset");
+ ASSERT(phy_reset_clk);
+
+ pipe_reset_clk = clk_get("usb30_pipe_clk");
+ ASSERT(pipe_reset_clk);
+
+ /* ASSERT */
+ ret = clk_reset(phy_reset_clk, CLK_RESET_ASSERT);
+
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_phy_reset clk\n");
+ return;
+ }
+
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_ASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to assert usb30_pipe_clk\n");
+ goto deassert_phy_clk;
+ }
+
+ udelay(100);
+
+ /* DEASSERT */
+ ret = clk_reset(pipe_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb_pipe_clk\n");
+ return;
+ }
+
+deassert_phy_clk:
+
+ ret = clk_reset(phy_reset_clk, CLK_RESET_DEASSERT);
+ if (ret)
+ {
+ dprintf(CRITICAL, "Failed to deassert usb30_phy_com_reset clk\n");
+ return;
+ }
+}
diff --git a/platform/thulium/gpio.c b/platform/thulium/gpio.c
new file mode 100644
index 0000000..281584f
--- /dev/null
+++ b/platform/thulium/gpio.c
@@ -0,0 +1,64 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <platform/gpio.h>
+
+/* Remove the file after the gpio patch to move this to msm_shared gets merged. */
+void gpio_tlmm_config(uint32_t gpio, uint8_t func,
+ uint8_t dir, uint8_t pull,
+ uint8_t drvstr, uint32_t enable)
+{
+ uint32_t val = 0;
+ val |= pull;
+ val |= func << 2;
+ val |= drvstr << 6;
+ val |= enable << 9;
+ writel(val, (unsigned int *)GPIO_CONFIG_ADDR(gpio));
+ return;
+}
+
+void gpio_set(uint32_t gpio, uint32_t dir)
+{
+ writel(dir, (unsigned int *)GPIO_IN_OUT_ADDR(gpio));
+ return;
+}
+
+/* Configure gpio for blsp uart */
+void gpio_config_uart_dm(uint8_t id)
+{
+ /* configure rx gpio */
+ gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+
+ /* configure tx gpio */
+ gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ GPIO_8MA, GPIO_DISABLE);
+}
diff --git a/platform/thulium/include/platform/clock.h b/platform/thulium/include/platform/clock.h
new file mode 100644
index 0000000..0a5836c
--- /dev/null
+++ b/platform/thulium/include/platform/clock.h
@@ -0,0 +1,51 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MSM8996_CLOCK_H
+#define __MSM8996_CLOCK_H
+
+#include <clock.h>
+#include <clock_lib2.h>
+
+#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
+
+
+void platform_clock_init(void);
+
+void clock_init_mmc(uint32_t interface);
+void clock_config_mmc(uint32_t interface, uint32_t freq);
+void clock_config_uart_dm(uint8_t id);
+void hsusb_clock_init(void);
+void clock_config_ce(uint8_t instance);
+void mdp_clock_init(void);
+void clock_ce_enable(uint8_t instance);
+void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
+void clock_reset_usb_phy();
+
+#endif
diff --git a/platform/thulium/include/platform/gpio.h b/platform/thulium/include/platform/gpio.h
new file mode 100644
index 0000000..c00512b
--- /dev/null
+++ b/platform/thulium/include/platform/gpio.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_MSM8996_GPIO_H
+#define __PLATFORM_MSM8996_GPIO_H
+
+#include <gpio.h>
+
+/* GPIO TLMM: Direction */
+#define GPIO_INPUT 0
+#define GPIO_OUTPUT 1
+
+/* GPIO TLMM: Pullup/Pulldown */
+#define GPIO_NO_PULL 0
+#define GPIO_PULL_DOWN 1
+#define GPIO_KEEPER 2
+#define GPIO_PULL_UP 3
+
+/* GPIO TLMM: Drive Strength */
+#define GPIO_2MA 0
+#define GPIO_4MA 1
+#define GPIO_6MA 2
+#define GPIO_8MA 3
+#define GPIO_10MA 4
+#define GPIO_12MA 5
+#define GPIO_14MA 6
+#define GPIO_16MA 7
+
+/* GPIO TLMM: Status */
+#define GPIO_ENABLE 0
+#define GPIO_DISABLE 1
+
+void gpio_config_uart_dm(uint8_t id);
+void gpio_config_blsp_i2c(uint8_t, uint8_t);
+#endif
diff --git a/platform/thulium/include/platform/iomap.h b/platform/thulium/include/platform/iomap.h
new file mode 100644
index 0000000..2c17d12
--- /dev/null
+++ b/platform/thulium/include/platform/iomap.h
@@ -0,0 +1,176 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PLATFORM_THULIUM_IOMAP_H_
+#define _PLATFORM_THULIUM_IOMAP_H_
+
+#define MSM_SHARED_BASE 0x86000000
+
+#define MSM_IOMAP_HMSS_START 0x09800000
+
+#define MSM_IOMAP_BASE 0x00000000
+#define MSM_IOMAP_END 0x10000000
+
+#define MSM_SHARED_IMEM_BASE 0x066BF000
+#define RESTART_REASON_ADDR (MSM_SHARED_IMEM_BASE + 0x65C)
+
+#define MSM_GIC_DIST_BASE (MSM_IOMAP_HMSS_START + 0x003C0000)
+#define MSM_GIC_REDIST_BASE (MSM_IOMAP_HMSS_START + 0x00400000)
+
+#define HMSS_APCS_F0_QTMR_V1_BASE (MSM_IOMAP_HMSS_START + 0x00050000)
+#define QTMR_BASE HMSS_APCS_F0_QTMR_V1_BASE
+
+#define PERIPH_SS_BASE 0x07400000
+
+#define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00064000)
+#define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900)
+#define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000)
+#define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900)
+
+#define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0016F000)
+#define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x00170000)
+#define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x00171000)
+#define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00172000)
+#define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00173000)
+#define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00174000)
+
+#define BLSP2_UART1_BASE (PERIPH_SS_BASE + 0x001B0000)
+
+/* USB3.0 */
+#define MSM_USB30_BASE 0x6A00000
+#define MSM_USB30_QSCRATCH_BASE 0x6AF8800
+/* SS QMP (Qulacomm Multi Protocol) */
+#define QMP_PHY_BASE 0x7410000
+
+/* QUSB2 PHY */
+#define QUSB2_PHY_BASE 0x7411000
+#define QUSB2PHY_PORT_POWERDOWN (QUSB2_PHY_BASE + 0x000000B4)
+#define GCC_QUSB2_PHY_BCR (CLK_CTL_BASE + 0x00012038)
+#define QUSB2PHY_PORT_UTMI_CTRL2 (QUSB2_PHY_BASE + 0x000000C4)
+#define QUSB2PHY_PORT_TUNE1 (QUSB2_PHY_BASE + 0x00000080)
+#define QUSB2PHY_PORT_TUNE2 (QUSB2_PHY_BASE + 0x00000084)
+#define QUSB2PHY_PORT_TUNE3 (QUSB2_PHY_BASE + 0x00000088)
+#define QUSB2PHY_PORT_TUNE4 (QUSB2_PHY_BASE + 0x0000008C)
+
+/* Clocks */
+#define CLK_CTL_BASE 0x300000
+
+/* GPLL */
+#define GPLL0_MODE (CLK_CTL_BASE + 0x0000)
+#define GPLL4_MODE (CLK_CTL_BASE + 0x77000)
+#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x52000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x52004)
+
+/* UART Clocks */
+#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x17004)
+#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x1C004)
+#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x1C00C)
+#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x1C010)
+#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x1C014)
+#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x1C018)
+#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x1C01C)
+
+/* USB3 clocks */
+#define USB_30_BCR (CLK_CTL_BASE + 0xF000)
+#define USB30_MASTER_CBCR (CLK_CTL_BASE + 0xF008)
+#define USB30_MASTER_CMD_RCGR (CLK_CTL_BASE + 0xF014)
+#define USB30_MASTER_CFG_RCGR (CLK_CTL_BASE + 0xF018)
+#define USB30_MASTER_M (CLK_CTL_BASE + 0xF01C)
+#define USB30_MASTER_N (CLK_CTL_BASE + 0xF020)
+#define USB30_MASTER_D (CLK_CTL_BASE + 0xF024)
+#define SYS_NOC_USB3_AXI_CBCR (CLK_CTL_BASE + 0xF03C)
+
+#define USB30_MOCK_UTMI_CMD_RCGR (CLK_CTL_BASE + 0xF014)
+#define USB30_MOCK_UTMI_CFG_RCGR (CLK_CTL_BASE + 0xF018)
+#define USB30_MOCK_UTMI_CBCR (CLK_CTL_BASE + 0xF010)
+#define USB30_SLEEP_CBCR (CLK_CTL_BASE + 0xF00C)
+#define USB30_PHY_AUX_CMD_RCGR (CLK_CTL_BASE + 0x5000C)
+#define USB30_PHY_AUX_CFG_RCGR (CLK_CTL_BASE + 0x50010)
+#define USB30_PHY_AUX_CBCR (CLK_CTL_BASE + 0x50000)
+#define USB30_PHY_PIPE_CBCR (CLK_CTL_BASE + 0x50004)
+#define USB30_PHY_BCR (CLK_CTL_BASE + 0x50020)
+#define USB30PHY_PHY_BCR (CLK_CTL_BASE + 0x50024)
+#define GCC_USB30_GDSCR (CLK_CTL_BASE + 0xF004)
+#define USB_PHY_CFG_AHB2PHY_CBCR (CLK_CTL_BASE + 0x6A004)
+
+/* SDCC */
+#define SDCC1_BCR (CLK_CTL_BASE + 0x13000) /* block reset */
+#define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x13004) /* branch control */
+#define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x13008)
+#define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x13010) /* cmd */
+#define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x13014) /* cfg */
+#define SDCC1_M (CLK_CTL_BASE + 0x13018) /* m */
+#define SDCC1_N (CLK_CTL_BASE + 0x1301C) /* n */
+#define SDCC1_D (CLK_CTL_BASE + 0x13020) /* d */
+
+/* SDCC2 */
+#define SDCC2_BCR (CLK_CTL_BASE + 0x14000) /* block reset */
+#define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x14004) /* branch control */
+#define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x14008)
+#define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x14010) /* cmd */
+#define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x14014) /* cfg */
+#define SDCC2_M (CLK_CTL_BASE + 0x14018) /* m */
+#define SDCC2_N (CLK_CTL_BASE + 0x1401C) /* n */
+#define SDCC2_D (CLK_CTL_BASE + 0x14020) /* d */
+
+#define UFS_BASE 0x624000
+
+#define SPMI_BASE 0x4000000
+#define SPMI_GENI_BASE (SPMI_BASE + 0xA000)
+#define SPMI_PIC_BASE (SPMI_BASE + 0x1800000)
+
+#define MSM_CE_BAM_BASE 0x67A000
+#define MSM_CE_BASE 0x644000
+
+#define TLMM_BASE_ADDR 0x1010000
+#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + (x)*0x1000)
+#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x4 + (x)*0x1000)
+
+#define MPM2_MPM_CTRL_BASE 0x4A1000
+#define MPM2_MPM_PS_HOLD 0x4AB000
+#define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0x4A3000
+
+/* DRV strength for sdcc */
+#define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x0003C000)
+
+/* SDHCI - power control registers */
+#define SDCC_MCI_HC_MODE (0x00000078)
+#define SDCC_HC_PWRCTL_STATUS_REG (0x000000DC)
+#define SDCC_HC_PWRCTL_MASK_REG (0x000000E0)
+#define SDCC_HC_PWRCTL_CLEAR_REG (0x000000E4)
+#define SDCC_HC_PWRCTL_CTL_REG (0x000000E8)
+
+/* Boot config */
+#define SEC_CTRL_CORE_BASE 0x70000
+#define BOOT_CONFIG_OFFSET 0x00006044
+#define BOOT_CONFIG_REG (SEC_CTRL_CORE_BASE + BOOT_CONFIG_OFFSET)
+
+/* Fix This */
+#define PLATFORM_QMP_OFFSET 0x8
+
+#endif
diff --git a/platform/thulium/include/platform/irqs.h b/platform/thulium/include/platform/irqs.h
new file mode 100644
index 0000000..dd0f31a
--- /dev/null
+++ b/platform/thulium/include/platform/irqs.h
@@ -0,0 +1,68 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __IRQS_THULIUM_H
+#define __IRQS_THULIUM_H
+
+/* MSM ACPU Interrupt Numbers */
+
+/* 0-15: STI/SGI (software triggered/generated interrupts)
+ * 16-31: PPI (private peripheral interrupts)
+ * 32+: SPI (shared peripheral interrupts)
+ */
+
+#define GIC_PPI_START 16
+#define GIC_SPI_START 32
+
+#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP (GIC_PPI_START + 3)
+#define INT_QTMR_VIRTUAL_TIMER_EXP (GIC_PPI_START + 4)
+
+#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP (GIC_SPI_START + 31)
+
+#define USB30_EE1_IRQ (GIC_SPI_START + 131)
+
+/* Retrofit universal macro names */
+#define INT_USB_HS USB30_EE1_IRQ
+
+#define SDCC1_PWRCTL_IRQ (GIC_SPI_START + 134)
+#define SDCC2_PWRCTL_IRQ (GIC_SPI_START + 221)
+
+#define UFS_IRQ (GIC_SPI_START + 265)
+
+#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ (GIC_SPI_START + 265)
+
+/* Fix this: where this comes from? */
+#define NR_MSM_IRQS 256
+#define NR_GPIO_IRQS 173
+#define NR_BOARD_IRQS 0
+
+#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + \
+ NR_BOARD_IRQS)
+
+#endif /* __IRQS_THULIUM_H */
diff --git a/platform/thulium/platform.c b/platform/thulium/platform.c
new file mode 100644
index 0000000..1dad8cc
--- /dev/null
+++ b/platform/thulium/platform.c
@@ -0,0 +1,132 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <debug.h>
+#include <reg.h>
+#include <platform/iomap.h>
+#include <qgic.h>
+#include <qtimer.h>
+#include <platform/clock.h>
+#include <mmu.h>
+#include <arch/arm/mmu.h>
+#include <smem.h>
+#include <board.h>
+
+#define MSM_IOMAP_SIZE ((MSM_IOMAP_END - MSM_IOMAP_BASE)/MB)
+#define MSM_SHARED_SIZE 2
+
+/* LK memory - cacheable, write through */
+#define LK_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE)
+
+/* Peripherals - non-shared device */
+#define IOMAP_MEMORY (MMU_MEMORY_TYPE_DEVICE_SHARED | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+/* SCRATCH memory - cacheable, write through */
+#define SCRATCH_MEMORY (MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
+ MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN)
+
+static mmu_section_t mmu_section_table[] = {
+/* Physical addr, Virtual addr, Size (in MB), Flags */
+ { MEMBASE, MEMBASE, (MEMSIZE / MB), LK_MEMORY},
+ { MSM_IOMAP_BASE, MSM_IOMAP_BASE, MSM_IOMAP_SIZE, IOMAP_MEMORY},
+ { KERNEL_ADDR, KERNEL_ADDR, KERNEL_SIZE, SCRATCH_MEMORY},
+ { SCRATCH_ADDR, SCRATCH_ADDR, SCRATCH_SIZE, SCRATCH_MEMORY},
+ { MSM_SHARED_BASE, MSM_SHARED_BASE, MSM_SHARED_SIZE, SCRATCH_MEMORY},
+};
+
+void platform_early_init(void)
+{
+ board_init();
+ platform_clock_init();
+ qgic_init();
+ qtimer_init();
+ scm_init();
+}
+
+void platform_init(void)
+{
+ dprintf(INFO, "platform_init()\n");
+}
+
+void platform_uninit(void)
+{
+#if DISPLAY_SPLASH_SCREEN
+ display_shutdown();
+#endif
+
+ qtimer_uninit();
+}
+
+int platform_use_identity_mmu_mappings(void)
+{
+ /* Use only the mappings specified in this file. */
+ return 0;
+}
+
+/* Setup memory for this platform */
+void platform_init_mmu_mappings(void)
+{
+ uint32_t i;
+ uint32_t sections;
+ uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+
+ /* Configure the MMU page entries for memory read from the
+ mmu_section_table */
+ for (i = 0; i < table_size; i++)
+ {
+ sections = mmu_section_table[i].num_of_sections;
+
+ while (sections--)
+ {
+ arm_mmu_map_section(mmu_section_table[i].paddress +
+ sections * MB,
+ mmu_section_table[i].vaddress +
+ sections * MB,
+ mmu_section_table[i].flags);
+ }
+ }
+}
+
+addr_t platform_get_virt_to_phys_mapping(addr_t virt_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return virt_addr;
+}
+
+addr_t platform_get_phys_to_virt_mapping(addr_t phys_addr)
+{
+ /* Using 1-1 mapping on this platform. */
+ return phys_addr;
+}
+
+uint32_t platform_get_sclk_count(void)
+{
+ return readl(MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL);
+}
diff --git a/platform/thulium/rules.mk b/platform/thulium/rules.mk
new file mode 100644
index 0000000..10afc50
--- /dev/null
+++ b/platform/thulium/rules.mk
@@ -0,0 +1,28 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ARCH := arm
+ARM_CPU := cortex-a8
+CPU := generic
+
+DEFINES += ARM_CPU_CORE_KRAIT
+
+MMC_SLOT := 1
+
+DEFINES += PERIPH_BLK_BLSP=1
+DEFINES += WITH_CPU_EARLY_INIT=0 WITH_CPU_WARM_BOOT=0 \
+ MMC_SLOT=$(MMC_SLOT)
+
+INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared/include
+
+DEVS += fbcon
+MODULES += dev/fbcon
+
+OBJS += \
+ $(LOCAL_DIR)/platform.o \
+ $(LOCAL_DIR)/acpuclock.o \
+ $(LOCAL_DIR)/thulium-clock.o \
+ $(LOCAL_DIR)/gpio.o
+
+LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld
+
+include platform/msm_shared/rules.mk
diff --git a/platform/thulium/thulium-clock.c b/platform/thulium/thulium-clock.c
new file mode 100644
index 0000000..b02bec4
--- /dev/null
+++ b/platform/thulium/thulium-clock.c
@@ -0,0 +1,419 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ * * Neither the name of The Linux Foundation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <assert.h>
+#include <reg.h>
+#include <err.h>
+#include <clock.h>
+#include <clock_pll.h>
+#include <clock_lib2.h>
+#include <platform/clock.h>
+#include <platform/iomap.h>
+
+
+/* Mux source select values */
+#define cxo_source_val 0
+#define gpll0_source_val 1
+#define gpll4_source_val 5
+#define cxo_mm_source_val 0
+#define mmpll0_mm_source_val 1
+#define mmpll1_mm_source_val 2
+#define mmpll3_mm_source_val 3
+#define gpll0_mm_source_val 5
+
+struct clk_freq_tbl rcg_dummy_freq = F_END;
+
+
+/* Clock Operations */
+static struct clk_ops clk_ops_rst =
+{
+ .reset = clock_lib2_reset_clk_reset,
+};
+
+static struct clk_ops clk_ops_branch =
+{
+ .enable = clock_lib2_branch_clk_enable,
+ .disable = clock_lib2_branch_clk_disable,
+ .set_rate = clock_lib2_branch_set_rate,
+ .reset = clock_lib2_branch_clk_reset,
+};
+
+static struct clk_ops clk_ops_rcg_mnd =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_rcg =
+{
+ .enable = clock_lib2_rcg_enable,
+ .set_rate = clock_lib2_rcg_set_rate,
+};
+
+static struct clk_ops clk_ops_cxo =
+{
+ .enable = cxo_clk_enable,
+ .disable = cxo_clk_disable,
+};
+
+static struct clk_ops clk_ops_pll_vote =
+{
+ .enable = pll_vote_clk_enable,
+ .disable = pll_vote_clk_disable,
+ .auto_off = pll_vote_clk_disable,
+ .is_enabled = pll_vote_clk_is_enabled,
+};
+
+static struct clk_ops clk_ops_vote =
+{
+ .enable = clock_lib2_vote_clk_enable,
+ .disable = clock_lib2_vote_clk_disable,
+};
+
+/* Clock Sources */
+static struct fixed_clk cxo_clk_src =
+{
+ .c = {
+ .rate = 19200000,
+ .dbg_name = "cxo_clk_src",
+ .ops = &clk_ops_cxo,
+ },
+};
+
+static struct pll_vote_clk gpll0_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(0),
+ .status_reg = (void *) GPLL0_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 600000000,
+ .dbg_name = "gpll0_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+static struct pll_vote_clk gpll4_clk_src =
+{
+ .en_reg = (void *) APCS_GPLL_ENA_VOTE,
+ .en_mask = BIT(4),
+ .status_reg = (void *) GPLL4_MODE,
+ .status_mask = BIT(30),
+ .parent = &cxo_clk_src.c,
+
+ .c = {
+ .rate = 1600000000,
+ .dbg_name = "gpll4_clk_src",
+ .ops = &clk_ops_pll_vote,
+ },
+};
+
+/* UART Clocks */
+static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] =
+{
+ F( 3686400, gpll0, 1, 96, 15625),
+ F( 7372800, gpll0, 1, 192, 15625),
+ F(14745600, gpll0, 1, 384, 15625),
+ F(16000000, gpll0, 5, 2, 15),
+ F(19200000, cxo, 1, 0, 0),
+ F(24000000, gpll0, 5, 1, 5),
+ F(32000000, gpll0, 1, 4, 75),
+ F(40000000, gpll0, 15, 0, 0),
+ F(46400000, gpll0, 1, 29, 375),
+ F(48000000, gpll0, 12.5, 0, 0),
+ F(51200000, gpll0, 1, 32, 375),
+ F(56000000, gpll0, 1, 7, 75),
+ F(58982400, gpll0, 1, 1536, 15625),
+ F(60000000, gpll0, 10, 0, 0),
+ F(63160000, gpll0, 9.5, 0, 0),
+ F_END
+};
+
+static struct rcg_clk blsp1_uart2_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) BLSP1_UART2_APPS_CMD_RCGR,
+ .cfg_reg = (uint32_t *) BLSP1_UART2_APPS_CFG_RCGR,
+ .m_reg = (uint32_t *) BLSP1_UART2_APPS_M,
+ .n_reg = (uint32_t *) BLSP1_UART2_APPS_N,
+ .d_reg = (uint32_t *) BLSP1_UART2_APPS_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "blsp1_uart2_apps_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_blsp1_uart2_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) BLSP1_UART2_APPS_CBCR,
+ .parent = &blsp1_uart2_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_blsp1_uart2_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+ .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR,
+ .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE,
+ .en_mask = BIT(17),
+
+ .c = {
+ .dbg_name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_ops_vote,
+ },
+};
+
+/* SDCC Clocks */
+static struct clk_freq_tbl ftbl_gcc_sdcc1_4_apps_clk[] =
+{
+ F( 144000, cxo, 16, 3, 25),
+ F( 400000, cxo, 12, 1, 4),
+ F( 20000000, gpll0, 15, 1, 2),
+ F( 25000000, gpll0, 12, 1, 2),
+ F( 50000000, gpll0, 12, 0, 0),
+ F( 96000000, gpll4, 16, 0, 0),
+ F(192000000, gpll4, 8, 0, 0),
+ F(384000000, gpll4, 4, 0, 0),
+ F_END
+};
+
+static struct rcg_clk sdcc1_apps_clk_src =
+{
+ .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR,
+ .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR,
+ .m_reg = (uint32_t *) SDCC1_M,
+ .n_reg = (uint32_t *) SDCC1_N,
+ .d_reg = (uint32_t *) SDCC1_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_sdcc1_4_apps_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "sdc1_clk",
+ .ops = &clk_ops_rcg_mnd,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_apps_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR,
+ .parent = &sdcc1_apps_clk_src.c,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_apps_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sdcc1_ahb_clk =
+{
+ .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk = {
+ .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "sys_noc_usb30_axi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = {
+ F( 125000000, gpll0, 1, 5, 24),
+ F_END
+};
+
+static struct rcg_clk usb30_master_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MASTER_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MASTER_CFG_RCGR,
+ .m_reg = (uint32_t *) USB30_MASTER_M,
+ .n_reg = (uint32_t *) USB30_MASTER_N,
+ .d_reg = (uint32_t *) USB30_MASTER_D,
+
+ .set_rate = clock_lib2_rcg_set_rate_mnd,
+ .freq_tbl = ftbl_gcc_usb30_master_clk,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_master_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_master_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MASTER_CBCR,
+ .bcr_reg = (uint32_t *) USB_30_BCR,
+ .parent = &usb30_master_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_master_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = {
+ F( 60000000, gpll0, 10, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_mock_utmi_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_MOCK_UTMI_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_MOCK_UTMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_mock_utmi_clk = {
+ .cbcr_reg = (uint32_t *) USB30_MOCK_UTMI_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_mock_utmi_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_mock_utmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_sleep_clk = {
+ .cbcr_reg = (uint32_t *) USB30_SLEEP_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_sleep_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_gcc_usb30_phy_aux_clk_src[] = {
+ F( 1200000, cxo, 16, 0, 0),
+ F_END
+};
+
+static struct rcg_clk usb30_phy_aux_clk_src = {
+ .cmd_reg = (uint32_t *) USB30_PHY_AUX_CMD_RCGR,
+ .cfg_reg = (uint32_t *) USB30_PHY_AUX_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_gcc_usb30_phy_aux_clk_src,
+ .current_freq = &rcg_dummy_freq,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk gcc_usb30_phy_aux_clk = {
+ .cbcr_reg = (uint32_t *)USB30_PHY_AUX_CBCR,
+ .has_sibling = 0,
+ .parent = &usb30_phy_aux_clk_src.c,
+
+ .c = {
+ .dbg_name = "usb30_phy_aux_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct branch_clk gcc_usb30_pipe_clk = {
+ .bcr_reg = (uint32_t *) USB30PHY_PHY_BCR,
+ .cbcr_reg = (uint32_t *) USB30_PHY_PIPE_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb30_pipe_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct reset_clk gcc_usb30_phy_reset = {
+ .bcr_reg = (uint32_t )USB30_PHY_BCR,
+
+ .c = {
+ .dbg_name = "usb30_phy_reset",
+ .ops = &clk_ops_rst,
+ },
+};
+
+static struct branch_clk gcc_usb_phy_cfg_ahb2phy_clk = {
+ .cbcr_reg = (uint32_t *)USB_PHY_CFG_AHB2PHY_CBCR,
+ .has_sibling = 1,
+
+ .c = {
+ .dbg_name = "usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+
+/* Clock lookup table */
+static struct clk_lookup msm_thulium_clocks[] =
+{
+ CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c),
+ CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c),
+
+ CLK_LOOKUP("uart2_iface_clk", gcc_blsp1_ahb_clk.c),
+ CLK_LOOKUP("uart2_core_clk", gcc_blsp1_uart2_apps_clk.c),
+
+ /* USB30 clocks */
+ CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
+ CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c),
+ CLK_LOOKUP("usb30_mock_utmi_clk", gcc_usb30_mock_utmi_clk.c),
+ CLK_LOOKUP("usb30_sleep_clk", gcc_usb30_sleep_clk.c),
+ CLK_LOOKUP("usb30_phy_aux_clk", gcc_usb30_phy_aux_clk.c),
+ CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c),
+ CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c),
+
+ CLK_LOOKUP("usb_phy_cfg_ahb2phy_clk", gcc_usb_phy_cfg_ahb2phy_clk.c),
+};
+
+void platform_clock_init(void)
+{
+ clk_init(msm_thulium_clocks, ARRAY_SIZE(msm_thulium_clocks));
+}