msm7627a: splash screen support
Change-Id: Ifa8223a71da1cb28f1b395009e430998d2c145c6
diff --git a/platform/msm7x27a/include/platform/iomap.h b/platform/msm7x27a/include/platform/iomap.h
index ce0da18..6dbe82a 100644
--- a/platform/msm7x27a/include/platform/iomap.h
+++ b/platform/msm7x27a/include/platform/iomap.h
@@ -29,8 +29,8 @@
* SUCH DAMAGE.
*/
-#ifndef _PLATFORM_MSM7K_IOMAP_H_
-#define _PLATFORM_MSM7K_IOMAP_H_
+#ifndef _PLATFORM_MSM7627A_IOMAP_H_
+#define _PLATFORM_MSM7627A_IOMAP_H_
#define MSM_GPIO1_BASE 0xA9200000
#define MSM_GPIO2_BASE 0xA9300000
@@ -62,4 +62,57 @@
#define MSM_SDC1_BASE 0xA0400000
#define MSM_SDC3_BASE 0xA0600000
+#define MIPI_DSI_BASE (0xA1100000)
+#define DSI_PHY_SW_RESET (0xA1100128)
+#define REG_DSI(off) (MIPI_DSI_BASE + (off))
+#define MDP_BASE (0xAA200000)
+#define REG_MDP(off) (MDP_BASE + (off))
+#define DSIPHY_REGULATOR_BASE (0x2CC)
+#define DSIPHY_TIMING_BASE (0x260)
+#define DSIPHY_CTRL_BASE (0x290)
+#define DSIPHY_PLL_BASE (0x200)
+#define DSIPHY_STRENGTH_BASE (0x2A0)
+
+/* Range 0 - 4 */
+#define DSIPHY_REGULATOR_CTRL(x) REG_DSI(DSIPHY_REGULATOR_BASE + (x) * 4)
+/* Range 0 - 11 */
+#define DSIPHY_TIMING_CTRL(x) REG_DSI(DSIPHY_TIMING_BASE + (x) * 4)
+/* Range 0 - 3 */
+#define DSIPHY_CTRL(x) REG_DSI(DSIPHY_CTRL_BASE + (x) * 4)
+/* Range 0 - 2 */
+#define DSIPHY_STRENGTH_CTRL(x) REG_DSI(DSIPHY_STRENGTH_BASE + (x) * 4)
+/* Range 0 - 19 */
+#define DSIPHY_PLL_CTRL(x) REG_DSI(DSIPHY_PLL_BASE + (x) * 4)
+
+#define DSI_CMD_DMA_MEM_START_ADDR_PANEL (0x2E000000)
+#define MDP_DMA_P_CONFIG (0xAA290000)
+#define MDP_DMA_P_OUT_XY (0xAA290010)
+#define MDP_DMA_P_SIZE (0xAA290004)
+#define MDP_DMA_P_BUF_ADDR (0xAA290008)
+#define MDP_DMA_P_BUF_Y_STRIDE (0xAA29000C)
+
+#define MDP_DSI_VIDEO_EN (0xAA2F0000)
+#define MDP_DSI_VIDEO_HSYNC_CTL (0xAA2F0004)
+#define MDP_DSI_VIDEO_VSYNC_PERIOD (0xAA2F0008)
+#define MDP_DSI_VIDEO_VSYNC_PULSE_WIDTH (0xAA2F000C)
+#define MDP_DSI_VIDEO_DISPLAY_HCTL (0xAA2F0010)
+#define MDP_DSI_VIDEO_DISPLAY_V_START (0xAA2F0014)
+#define MDP_DSI_VIDEO_DISPLAY_V_END (0xAA2F0018)
+#define MDP_DSI_VIDEO_BORDER_CLR (0xAA2F0028)
+#define MDP_DSI_VIDEO_HSYNC_SKEW (0xAA2F0030)
+#define MDP_DSI_VIDEO_CTL_POLARITY (0xAA2F0038)
+#define MDP_DSI_VIDEO_TEST_CTL (0xAA2F0034)
+
+#define MDP_DMA_P_START REG_MDP(0x0000C)
+#define MDP_DMA_S_START REG_MDP(0x00010)
+#define MDP_DISP_INTF_SEL REG_MDP(0x00038)
+#define MDP_MAX_RD_PENDING_CMD_CONFIG REG_MDP(0x0004C)
+#define MDP_INTR_ENABLE REG_MDP(0x00020)
+#define MDP_INTR_CLEAR REG_MDP(0x00028)
+#define MDP_DSI_CMD_MODE_ID_MAP REG_MDP(0x000A0)
+#define MDP_DSI_CMD_MODE_TRIGGER_EN REG_MDP(0x000A4)
+#define MDP_OVERLAYPROC0_CFG REG_MDP(0x10004)
+
+#define MDP_TEST_MODE_CLK REG_MDP(0xF0000)
+#define MDP_INTR_STATUS REG_MDP(0x00054)
#endif