Merge "platform: Add function to detect the panel and pick up corresponding DT"
diff --git a/arch/arm/include/arch/arm.h b/arch/arm/include/arch/arm.h
index a14bf9c..e056628 100644
--- a/arch/arm/include/arch/arm.h
+++ b/arch/arm/include/arch/arm.h
@@ -87,6 +87,8 @@
void arm_write_dacr(uint32_t val);
void arm_invalidate_tlb(void);
+void dump_fault_frame(struct arm_fault_frame *frame);
+
#if defined(__cplusplus)
}
#endif
diff --git a/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h b/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h
new file mode 100644
index 0000000..3f9c7b3
--- /dev/null
+++ b/dev/gcdb/display/include/panel_hx8379c_fwvga_video.h
@@ -0,0 +1,253 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are
+* met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above
+* copyright notice, this list of conditions and the following
+* disclaimer in the documentation and/or other materials provided
+* with the distribution.
+* * Neither the name of The Linux Foundation nor the names of its
+* contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _PANEL_HX8379C_FWVGA_VIDEO_H_
+#define _PANEL_HX8379C_FWVGA_VIDEO_H_
+/*---------------------------------------------------------------------------*/
+/* HEADER files */
+/*---------------------------------------------------------------------------*/
+#include "panel.h"
+
+/*---------------------------------------------------------------------------*/
+/* Panel configuration */
+/*---------------------------------------------------------------------------*/
+static struct panel_config hx8379c_fwvga_video_panel_data = {
+ "qcom,mdss_dsi_hx8379c_fwvga_video", "dsi:0:", "qcom,mdss-dsi-panel",
+ 10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel resolution */
+/*---------------------------------------------------------------------------*/
+static struct panel_resolution hx8379c_fwvga_video_panel_res = {
+ 480, 854, 60, 60, 60, 0, 6, 6, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel color information */
+/*---------------------------------------------------------------------------*/
+static struct color_info hx8379c_fwvga_video_color = {
+ 24, 0, 0xff, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel on/off command information */
+/*---------------------------------------------------------------------------*/
+static char hx8379c_fwvga_video_on_cmd0[] = {
+ 0x04, 0x00, 0x39, 0xC0,
+ 0xB9, 0xFF, 0x83, 0x79,
+};
+
+static char hx8379c_fwvga_video_on_cmd1[] = {
+ 0x15, 0x00, 0x39, 0xC0,
+ 0xB1, 0x44, 0x1C, 0x1C,
+ 0x31, 0x31, 0x50, 0xD0,
+ 0xEE, 0x54, 0x80, 0x38,
+ 0x38, 0xF8, 0x32, 0x22,
+ 0x22, 0x00, 0x80, 0x30,
+ 0x00, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd2[] = {
+ 0x0A, 0x00, 0x39, 0xC0,
+ 0xB2, 0x80, 0xFE, 0x0B,
+ 0x04, 0x00, 0x50, 0x11,
+ 0x42, 0x1D, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd3[] = {
+ 0x0B, 0x00, 0x39, 0xC0,
+ 0xB4, 0x69, 0x6A, 0x69,
+ 0x6A, 0x69, 0x6A, 0x22,
+ 0x70, 0x23, 0x70, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd4[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xCC, 0x02, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd5[] = {
+ 0x02, 0x00, 0x39, 0xC0,
+ 0xD2, 0x77, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd6[] = {
+ 0x1E, 0x00, 0x39, 0xC0,
+ 0xD3, 0x00, 0x07, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x32, 0x10, 0x03, 0x00,
+ 0x03, 0x03, 0x60, 0x03,
+ 0x60, 0x00, 0x08, 0x00,
+ 0x08, 0x45, 0x44, 0x08,
+ 0x08, 0x37, 0x08, 0x08,
+ 0x37, 0x09, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd7[] = {
+ 0x21, 0x00, 0x39, 0xC0,
+ 0xD5, 0x18, 0x18, 0x19,
+ 0x19, 0x18, 0x18, 0x20,
+ 0x21, 0x24, 0x25, 0x18,
+ 0x18, 0x18, 0x18, 0x00,
+ 0x01, 0x04, 0x05, 0x02,
+ 0x03, 0x06, 0x07, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd8[] = {
+ 0x21, 0x00, 0x39, 0xC0,
+ 0xD6, 0x18, 0x18, 0x18,
+ 0x18, 0x19, 0x19, 0x25,
+ 0x24, 0x21, 0x20, 0x18,
+ 0x18, 0x18, 0x18, 0x05,
+ 0x04, 0x01, 0x00, 0x03,
+ 0x02, 0x07, 0x06, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0x18, 0x18, 0x18,
+ 0x18, 0xFF, 0xFF, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd9[] = {
+ 0x2B, 0x00, 0x39, 0xC0,
+ 0xE0, 0x00, 0x10, 0x16,
+ 0x35, 0x39, 0x3F, 0x27,
+ 0x47, 0x07, 0x0B, 0x0C,
+ 0x17, 0x0E, 0x13, 0x16,
+ 0x14, 0x15, 0x07, 0x11,
+ 0x13, 0x18, 0x00, 0x10,
+ 0x17, 0x35, 0x3A, 0x3F,
+ 0x26, 0x47, 0x06, 0x0B,
+ 0x0C, 0x17, 0x0F, 0x14,
+ 0x16, 0x14, 0x15, 0x07,
+ 0x11, 0x13, 0x16, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd10[] = {
+ 0x03, 0x00, 0x39, 0xC0,
+ 0xB6, 0x4B, 0x4B, 0xFF,
+};
+
+static char hx8379c_fwvga_video_on_cmd11[] = {
+ 0x11, 0x00, 0x05, 0x80
+};
+
+static char hx8379c_fwvga_video_on_cmd12[] = {
+ 0x29, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379c_fwvga_video_on_command[] = {
+ {0x8, hx8379c_fwvga_video_on_cmd0, 0x00},
+ {0x1c, hx8379c_fwvga_video_on_cmd1, 0x00},
+ {0x10, hx8379c_fwvga_video_on_cmd2, 0x00},
+ {0x10, hx8379c_fwvga_video_on_cmd3, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd4, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd5, 0x00},
+ {0x24, hx8379c_fwvga_video_on_cmd6, 0x00},
+ {0x28, hx8379c_fwvga_video_on_cmd7, 0x00},
+ {0x28, hx8379c_fwvga_video_on_cmd8, 0x00},
+ {0x30, hx8379c_fwvga_video_on_cmd9, 0x00},
+ {0x8, hx8379c_fwvga_video_on_cmd10, 0x00},
+ {0x4, hx8379c_fwvga_video_on_cmd11, 0x96},
+ {0x4, hx8379c_fwvga_video_on_cmd12, 0x78}
+};
+
+#define HX8379C_FWVGA_VIDEO_ON_COMMAND 13
+
+
+static char hx8379c_fwvga_videooff_cmd0[] = {
+ 0x28, 0x00, 0x05, 0x80
+};
+
+static char hx8379c_fwvga_videooff_cmd1[] = {
+ 0x10, 0x00, 0x05, 0x80
+};
+
+static struct mipi_dsi_cmd hx8379c_fwvga_video_off_command[] = {
+ {0x4, hx8379c_fwvga_videooff_cmd0, 0x32},
+ {0x4, hx8379c_fwvga_videooff_cmd1, 0x78}
+};
+
+#define HX8379C_FWVGA_VIDEO_OFF_COMMAND 2
+
+
+static struct command_state hx8379c_fwvga_video_state = {
+ 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Command mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct commandpanel_info hx8379c_fwvga_video_command_panel = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Video mode panel information */
+/*---------------------------------------------------------------------------*/
+static struct videopanel_info hx8379c_fwvga_video_video_panel = {
+ 1, 0, 0, 0, 1, 1, 2, 0, 0x9
+};
+
+/*---------------------------------------------------------------------------*/
+/* Lane configuration */
+/*---------------------------------------------------------------------------*/
+static struct lane_configuration hx8379c_fwvga_video_lane_config = {
+ 2, 0, 1, 1, 0, 0
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel timing */
+/*---------------------------------------------------------------------------*/
+static const uint32_t hx8379c_fwvga_video_timings[] = {
+ 0x73, 0x21, 0x1A, 0x00, 0x31, 0x2D, 0x1E, 0x23, 0x2B, 0x03, 0x04, 0x00
+};
+
+static struct panel_timing hx8379c_fwvga_video_timing_info = {
+ 0, 4, 0x20, 0x2c
+};
+
+/*---------------------------------------------------------------------------*/
+/* Panel reset sequence */
+/*---------------------------------------------------------------------------*/
+static struct panel_reset_sequence hx8379c_fwvga_video_reset_seq = {
+ {1, 0, 1, }, {20, 20, 20, }, 2
+};
+
+/*---------------------------------------------------------------------------*/
+/* Backlight setting */
+/*---------------------------------------------------------------------------*/
+static struct backlight hx8379c_fwvga_video_backlight = {
+ 1, 1, 4095, 100, 1, "PMIC_8941"
+};
+
+#define HX8379C_FWVGA_VIDEO_SIGNATURE 0xFFFF
+
+#endif /*_PANEL_HX8379A_FWVGA_SKUA_VIDEO_H_*/
diff --git a/dev/gcdb/display/panel_display.c b/dev/gcdb/display/panel_display.c
index 9ecd88a..9ae9bf6 100755
--- a/dev/gcdb/display/panel_display.c
+++ b/dev/gcdb/display/panel_display.c
@@ -47,12 +47,41 @@
#include "include/panel.h"
#include "target/display.h"
+static int dsi_panel_ctl_base_setup(struct msm_panel_info *pinfo,
+ char *panel_destination)
+{
+ if (!strcmp(panel_destination, "DISPLAY_1")) {
+ pinfo->dest = DISPLAY_1;
+ pinfo->mipi.ctl_base = MIPI_DSI0_BASE;
+ pinfo->mipi.phy_base = DSI0_PHY_BASE;
+ pinfo->mipi.sctl_base = MIPI_DSI1_BASE;
+ pinfo->mipi.sphy_base = DSI1_PHY_BASE;
+ } else if (!strcmp(panel_destination, "DISPLAY_2")) {
+ pinfo->dest = DISPLAY_2;
+ pinfo->mipi.ctl_base = MIPI_DSI1_BASE;
+ pinfo->mipi.phy_base = DSI1_PHY_BASE;
+ pinfo->mipi.sctl_base = MIPI_DSI0_BASE;
+ pinfo->mipi.sphy_base = DSI0_PHY_BASE;
+ } else {
+ pinfo->dest = DISPLAY_UNKNOWN;
+ dprintf(CRITICAL, "%s: Unkown panel destination: %d\n",
+ __func__, pinfo->dest);
+ return ERROR;
+ }
+
+ dprintf(SPEW, "%s: panel dest=%s, ctl_base=0x%08x, phy_base=0x%08x\n",
+ __func__, panel_destination, pinfo->mipi.ctl_base,
+ pinfo->mipi.phy_base);
+ return NO_ERROR;
+}
+
/*---------------------------------------------------------------------------*/
/* Panel Init */
/*---------------------------------------------------------------------------*/
int dsi_panel_init(struct msm_panel_info *pinfo,
struct panel_struct *pstruct)
{
+ int ret = NO_ERROR;
/* Resolution setting*/
pinfo->xres = pstruct->panelres->panel_width;
pinfo->yres = pstruct->panelres->panel_height;
@@ -128,6 +157,10 @@
pinfo->mipi.bitclock = pstruct->paneldata->panel_bitclock_freq;
pinfo->mipi.use_enable_gpio =
pstruct->paneldata->panel_with_enable_gpio;
+ ret = dsi_panel_ctl_base_setup(pinfo,
+ pstruct->paneldata->panel_destination);
+ if (ret)
+ return ret;
/* Video Panel configuration */
pinfo->mipi.pulse_mode_hsa_he = pstruct->videopanel->hsync_pulse;
@@ -289,7 +322,7 @@
pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
- MIPI_DSI0_BASE);
+ pinfo->mipi.ctl_base);
if (pinfo->mipi.dual_dsi)
ret = mdss_dsi_video_mode_config(final_width, final_height,
@@ -303,7 +336,7 @@
pinfo->mipi.hsa_power_stop,
pinfo->mipi.eof_bllp_power,
pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ pinfo->mipi.sctl_base);
return ret;
}
@@ -347,7 +380,7 @@
pinfo->mipi.dst_format,
ystride, lane_en,
pinfo->mipi.interleave_mode,
- MIPI_DSI0_BASE);
+ pinfo->mipi.ctl_base);
if (pinfo->mipi.dual_dsi)
ret = mdss_dsi_cmd_mode_config(final_width, final_height,
@@ -355,7 +388,7 @@
pinfo->mipi.dst_format,
ystride, lane_en,
pinfo->mipi.interleave_mode,
- MIPI_DSI1_BASE);
+ pinfo->mipi.sctl_base);
return ret;
}
diff --git a/platform/msm8994/acpuclock.c b/platform/msm8994/acpuclock.c
index e170046..6b77ea0 100644
--- a/platform/msm8994/acpuclock.c
+++ b/platform/msm8994/acpuclock.c
@@ -448,41 +448,39 @@
clk_disable(clk_get("mmss_mmssnoc_axi_clk"));
}
-void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t dual_dsi,
+void mmss_dsi_clock_enable(uint32_t dsi_pixel0_cfg_rcgr, uint32_t flags,
uint8_t pclk0_m, uint8_t pclk0_n, uint8_t pclk0_d)
{
int ret;
- /* Configure Byte clock -autopll- This will not change because
- byte clock does not need any divider*/
- writel(0x100, DSI_BYTE0_CFG_RCGR);
- writel(0x1, DSI_BYTE0_CMD_RCGR);
- writel(0x1, DSI_BYTE0_CBCR);
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+ /* Enable DSI0 branch clocks */
+ writel(0x100, DSI_BYTE0_CFG_RCGR);
+ writel(0x1, DSI_BYTE0_CMD_RCGR);
+ writel(0x1, DSI_BYTE0_CBCR);
- /* Configure Pixel clock */
- writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
- writel(0x1, DSI_PIXEL0_CMD_RCGR);
- writel(0x1, DSI_PIXEL0_CBCR);
+ writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL0_CFG_RCGR);
+ writel(0x1, DSI_PIXEL0_CMD_RCGR);
+ writel(0x1, DSI_PIXEL0_CBCR);
- writel(pclk0_m, DSI_PIXEL0_M);
- writel(pclk0_n, DSI_PIXEL0_N);
- writel(pclk0_d, DSI_PIXEL0_D);
+ writel(pclk0_m, DSI_PIXEL0_M);
+ writel(pclk0_n, DSI_PIXEL0_N);
+ writel(pclk0_d, DSI_PIXEL0_D);
- /* Configure ESC clock */
- ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
- if(ret)
- {
- dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
- ASSERT(0);
+ ret = clk_get_set_enable("mdss_esc0_clk", 0, 1);
+ if(ret)
+ {
+ dprintf(CRITICAL, "failed to set esc0_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
}
- if (dual_dsi) {
- /* Configure Byte 1 clock */
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
+ /* Enable DSI1 branch clocks */
writel(0x100, DSI_BYTE1_CFG_RCGR);
writel(0x1, DSI_BYTE1_CMD_RCGR);
writel(0x1, DSI_BYTE1_CBCR);
- /* Configure Pixel clock */
writel(dsi_pixel0_cfg_rcgr, DSI_PIXEL1_CFG_RCGR);
writel(0x1, DSI_PIXEL1_CMD_RCGR);
writel(0x1, DSI_PIXEL1_CBCR);
@@ -491,7 +489,6 @@
writel(pclk0_n, DSI_PIXEL1_N);
writel(pclk0_d, DSI_PIXEL1_D);
- /* Configure ESC clock */
ret = clk_get_set_enable("mdss_esc1_clk", 0, 1);
if(ret)
{
@@ -501,15 +498,15 @@
}
}
-void mmss_dsi_clock_disable(uint32_t dual_dsi)
+void mmss_dsi_clock_disable(uint32_t flags)
{
- /* Disable ESC clock */
- clk_disable(clk_get("mdss_esc0_clk"));
- writel(0x0, DSI_BYTE0_CBCR);
- writel(0x0, DSI_PIXEL0_CBCR);
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI0) {
+ clk_disable(clk_get("mdss_esc0_clk"));
+ writel(0x0, DSI_BYTE0_CBCR);
+ writel(0x0, DSI_PIXEL0_CBCR);
+ }
- if (dual_dsi) {
- /* Disable ESC clock */
+ if (flags & MMSS_DSI_CLKS_FLAG_DSI1) {
clk_disable(clk_get("mdss_esc1_clk"));
writel(0x0, DSI_BYTE1_CBCR);
writel(0x0, DSI_PIXEL1_CBCR);
diff --git a/platform/msm8994/include/platform/clock.h b/platform/msm8994/include/platform/clock.h
index c50fef7..578e56e 100644
--- a/platform/msm8994/include/platform/clock.h
+++ b/platform/msm8994/include/platform/clock.h
@@ -100,6 +100,9 @@
#define EDPAUX_CFG_RCGR REG_MM(0x20E4)
#define EDPAUX_CMD_RCGR REG_MM(0x20E0)
+#define MMSS_DSI_CLKS_FLAG_DSI0 BIT(0)
+#define MMSS_DSI_CLKS_FLAG_DSI1 BIT(1)
+
void platform_clock_init(void);
void clock_init_mmc(uint32_t interface);
diff --git a/platform/msm_shared/board.c b/platform/msm_shared/board.c
index 89fb195..39072aa 100644
--- a/platform/msm_shared/board.c
+++ b/platform/msm_shared/board.c
@@ -42,6 +42,7 @@
LINUX_MACHTYPE_UNKNOWN,
BASEBAND_MSM,
{{PMIC_IS_INVALID, 0}, {PMIC_IS_INVALID, 0}, {PMIC_IS_INVALID, 0}},
+ 0,
};
static void platform_detect()
diff --git a/platform/msm_shared/boot_stats.c b/platform/msm_shared/boot_stats.c
index 551000e..20635f2 100644
--- a/platform/msm_shared/boot_stats.c
+++ b/platform/msm_shared/boot_stats.c
@@ -30,6 +30,7 @@
#include <debug.h>
#include <reg.h>
#include <platform/iomap.h>
+#include <platform.h>
static uint32_t kernel_load_start;
void bs_set_timestamp(enum bs_entry bs_id)
diff --git a/platform/msm_shared/clock_lib2.c b/platform/msm_shared/clock_lib2.c
index f5e321a..cc87c92 100644
--- a/platform/msm_shared/clock_lib2.c
+++ b/platform/msm_shared/clock_lib2.c
@@ -270,5 +270,5 @@
if (!bclk)
return 0;
- return __clock_lib2_branch_clk_reset(bclk->bcr_reg, action);
+ return __clock_lib2_branch_clk_reset((uint32_t)bclk->bcr_reg, action);
}
diff --git a/platform/msm_shared/crypto_hash.c b/platform/msm_shared/crypto_hash.c
index 0d3cce8..9a2cdc9 100644
--- a/platform/msm_shared/crypto_hash.c
+++ b/platform/msm_shared/crypto_hash.c
@@ -27,6 +27,7 @@
*/
#include <string.h>
+#include <sha.h>
#include <debug.h>
#include <sys/types.h>
#include "crypto_hash.h"
diff --git a/platform/msm_shared/dev_tree.c b/platform/msm_shared/dev_tree.c
index 36b2a3a..32071b5 100644
--- a/platform/msm_shared/dev_tree.c
+++ b/platform/msm_shared/dev_tree.c
@@ -37,6 +37,7 @@
#include <board.h>
#include <list.h>
#include <kernel/thread.h>
+#include <target.h>
struct dt_entry_v1
{
@@ -455,7 +456,7 @@
break;
dtb_size = fdt_totalsize(&dtb_hdr);
- if (check_aboot_addr_range_overlap(tags, dtb_size)) {
+ if (check_aboot_addr_range_overlap((uint32_t)tags, dtb_size)) {
dprintf(CRITICAL, "Tags addresses overlap with aboot addresses.\n");
return NULL;
}
diff --git a/platform/msm_shared/display.c b/platform/msm_shared/display.c
index f0b6020..6c59ecf 100644
--- a/platform/msm_shared/display.c
+++ b/platform/msm_shared/display.c
@@ -186,7 +186,7 @@
if (ret)
goto msm_display_on_out;
- ret = mipi_dsi_on();
+ ret = mipi_dsi_on(pinfo);
if (ret)
goto msm_display_on_out;
break;
@@ -348,7 +348,7 @@
break;
case MIPI_VIDEO_PANEL:
dprintf(INFO, "Turn off MIPI_VIDEO_PANEL.\n");
- ret = mdp_dsi_video_off();
+ ret = mdp_dsi_video_off(pinfo);
if (ret)
goto msm_display_off_out;
ret = mipi_dsi_off(pinfo);
diff --git a/platform/msm_shared/hsusb.c b/platform/msm_shared/hsusb.c
index 49da56c..839f301 100644
--- a/platform/msm_shared/hsusb.c
+++ b/platform/msm_shared/hsusb.c
@@ -41,6 +41,7 @@
#include <kernel/thread.h>
#include <reg.h>
#include <dev/udc.h>
+#include <target.h>
#include "hsusb.h"
#define MAX_TD_XFER_SIZE (16 * 1024)
@@ -307,21 +308,19 @@
item = memalign(CACHE_LINE,
ROUNDUP(sizeof(struct ept_queue_item), CACHE_LINE));
if (!item) {
- dprintf(ALWAYS, "allocate USB item fail ept%d"
- "%s queue\n",
- "td count = %d\n",
+ dprintf(ALWAYS, "allocate USB item fail ept%d\n %s queue\ntd count = %d\n",
ept->num,
ept->in ? "in" : "out",
count);
return -1;
} else {
count ++;
- curr_item->next = PA(item);
+ curr_item->next = PA((addr_t)item);
item->next = TERMINATE;
}
} else
/* Since next TD in chain already exists */
- item = VA(curr_item->next);
+ item = (struct ept_queue_item *)VA(curr_item->next);
/* Update TD with transfer information */
item->info = INFO_BYTES(xfer) | INFO_ACTIVE;
@@ -340,7 +339,7 @@
curr_item->next = TERMINATE;
curr_item->info |= INFO_IOC;
enter_critical_section();
- ept->head->next = PA(req->item);
+ ept->head->next = PA((addr_t)req->item);
ept->head->info = 0;
ept->req = req;
arch_clean_invalidate_cache_range((addr_t) ept,
@@ -349,7 +348,7 @@
sizeof(struct ept_queue_head));
arch_clean_invalidate_cache_range((addr_t) ept->req,
sizeof(struct usb_request));
- arch_clean_invalidate_cache_range((addr_t) VA(req->req.buf),
+ arch_clean_invalidate_cache_range((addr_t) VA((addr_t)req->req.buf),
req->req.length);
item = req->item;
@@ -359,7 +358,7 @@
if (curr_item->next == TERMINATE)
item = NULL;
else
- item = curr_item->next;
+ item = (struct ept_queue_item *)curr_item->next;
arch_clean_invalidate_cache_range((addr_t) curr_item,
sizeof(struct ept_queue_item));
}
@@ -374,9 +373,8 @@
{
struct ept_queue_item *item;
unsigned actual, total_len;
- int status, len;
+ int status;
struct usb_request *req=NULL;
- void *buf;
DBG("ept%d %s complete req=%p\n",
ept->num, ept->in ? "in" : "out", ept->req);
@@ -386,13 +384,13 @@
if(ept->req)
{
- req = VA(ept->req);
+ req = (struct usb_request *)VA((addr_t)ept->req);
arch_invalidate_cache_range((addr_t) ept->req,
sizeof(struct usb_request));
}
if (req) {
- item = VA(req->item);
+ item = (struct ept_queue_item *)VA((addr_t)req->item);
/* total transfer length for transacation */
total_len = req->req.length;
ept->req = 0;
@@ -426,7 +424,7 @@
/*
* Record the data transferred for the last TD
*/
- actual += total_len - (item->info >> 16)
+ actual += (total_len - (item->info >> 16))
& 0x7FFF;
total_len = 0;
break;
@@ -437,10 +435,10 @@
* TD woulb the max possible TD transfer size
* (16K)
*/
- actual += MAX_TD_XFER_SIZE - (item->info >> 16) & 0x7FFF;
- total_len -= MAX_TD_XFER_SIZE - (item->info >> 16) & 0x7FFF;
+ actual += (MAX_TD_XFER_SIZE - (item->info >> 16)) & 0x7FFF;
+ total_len -= (MAX_TD_XFER_SIZE - (item->info >> 16)) & 0x7FFF;
/*Move to next item in chain*/
- item = VA(item->next);
+ item = (struct ept_queue_item *)VA(item->next);
}
}
status = 0;
@@ -526,7 +524,7 @@
{
DBG("setup_tx %p %d\n", buf, len);
memcpy(ep0req->buf, buf, len);
- ep0req->buf = PA((addr_t)ep0req->buf);
+ ep0req->buf = (void *)PA((addr_t)ep0req->buf);
ep0req->complete = ep0in_complete;
ep0req->length = len;
udc_request_queue(ep0in, ep0req);
diff --git a/platform/msm_shared/i2c_qup.c b/platform/msm_shared/i2c_qup.c
index 916d865..dc8481d 100644
--- a/platform/msm_shared/i2c_qup.c
+++ b/platform/msm_shared/i2c_qup.c
@@ -702,6 +702,7 @@
mask_interrupt(dev->qup_irq);
}
+#if DEFINE_GSBI_I2C
struct qup_i2c_dev *qup_i2c_init(uint8_t gsbi_id, unsigned clk_freq,
unsigned src_clk_freq)
{
@@ -739,6 +740,7 @@
return dev;
}
+#endif
struct qup_i2c_dev *qup_blsp_i2c_init(uint8_t blsp_id, uint8_t qup_id,
uint32_t clk_freq, uint32_t src_clk_freq)
diff --git a/platform/msm_shared/image_verify.c b/platform/msm_shared/image_verify.c
index bc2017d..1f68b9d 100644
--- a/platform/msm_shared/image_verify.c
+++ b/platform/msm_shared/image_verify.c
@@ -25,11 +25,14 @@
* SUCH DAMAGE.
*/
#include <x509.h>
+#include <err.h>
#include <certificate.h>
#include <crypto_hash.h>
+#include <string.h>
#include "image_verify.h"
#include "scm.h"
+
/*
* Returns -1 if decryption failed otherwise size of plain_text in bytes
*/
@@ -62,7 +65,7 @@
*/
int ret = -1;
X509 *x509_certificate = NULL;
- unsigned char *cert_ptr = certBuffer;
+ const unsigned char *cert_ptr = (const unsigned char *)certBuffer;
unsigned int cert_size = sizeof(certBuffer);
EVP_PKEY *pub_key = NULL;
RSA *rsa_key = NULL;
@@ -133,7 +136,7 @@
int auth = 0;
unsigned char *plain_text = NULL;
unsigned int digest[8];
- unsigned int hash_size;
+ int hash_size;
plain_text = (unsigned char *)calloc(sizeof(char), SIGNATURE_SIZE);
if (plain_text == NULL) {
diff --git a/platform/msm_shared/include/crypto4_eng.h b/platform/msm_shared/include/crypto4_eng.h
index dde7794..4a8b037 100644
--- a/platform/msm_shared/include/crypto4_eng.h
+++ b/platform/msm_shared/include/crypto4_eng.h
@@ -73,4 +73,5 @@
#define GOPROC_GO 1
+void crypto_eng_cleanup(void);
#endif
diff --git a/platform/msm_shared/include/crypto5_wrapper.h b/platform/msm_shared/include/crypto5_wrapper.h
index 9c9af9b..0ae4ff0 100644
--- a/platform/msm_shared/include/crypto5_wrapper.h
+++ b/platform/msm_shared/include/crypto5_wrapper.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012,2014 The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -33,5 +33,6 @@
void crypto_init_params(struct crypto_init_params * params);
uint32_t crypto_get_max_auth_blk_size();
+void crypto_eng_cleanup(void);
#endif
diff --git a/platform/msm_shared/include/crypto_hash.h b/platform/msm_shared/include/crypto_hash.h
index bdcf7e0..44e227a 100644
--- a/platform/msm_shared/include/crypto_hash.h
+++ b/platform/msm_shared/include/crypto_hash.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -132,4 +132,9 @@
unsigned char *digest_ptr);
bool crypto_initialized(void);
+void
+hash_find(unsigned char *addr, unsigned int size, unsigned char *digest,
+ unsigned char auth_alg);
+
+crypto_engine_type board_ce_type(void);
#endif
diff --git a/platform/msm_shared/include/image_verify.h b/platform/msm_shared/include/image_verify.h
index 0819421..fe20c9f 100644
--- a/platform/msm_shared/include/image_verify.h
+++ b/platform/msm_shared/include/image_verify.h
@@ -47,4 +47,5 @@
/* Find hash of image */
void image_find_digest(unsigned char *image_ptr, unsigned int image_size,
unsigned hash_type, unsigned char *digest);
+void save_kernel_hash_cmd(void *digest);
#endif
diff --git a/platform/msm_shared/include/mipi_dsi.h b/platform/msm_shared/include/mipi_dsi.h
index 2a244ca..7f27de8 100644
--- a/platform/msm_shared/include/mipi_dsi.h
+++ b/platform/msm_shared/include/mipi_dsi.h
@@ -214,9 +214,9 @@
**********************************************************/
int mipi_config(struct msm_fb_panel_data *panel);
int mdss_dsi_config(struct msm_fb_panel_data *panel);
-int mdss_dsi_phy_init(struct mipi_dsi_panel_config *,
+int mdss_dsi_phy_init(struct mipi_panel_info *mipi,
uint32_t ctl_base, uint32_t phy_base);
-void mdss_dsi_phy_contention_detection(struct mipi_dsi_panel_config *,
+void mdss_dsi_phy_contention_detection(struct mipi_panel_info *mipi,
uint32_t phy_base);
int mdss_dsi_video_mode_config(uint16_t disp_width,
@@ -237,9 +237,11 @@
uint8_t interleav,
uint32_t ctl_base);
-int mipi_dsi_on();
+int mipi_dsi_on(struct msm_panel_info *pinfo);
int mipi_dsi_off(struct msm_panel_info *pinfo);
-int mdss_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count, char dual_dsi);
-int mdss_dsi_cmds_rx(uint32_t **rp, int rp_len, int rdbk_len);
+int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi,
+ struct mipi_dsi_cmd *cmds, int count, char dual_dsi);
+int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len,
+ int rdbk_len);
#endif
diff --git a/platform/msm_shared/include/mmc_sdhci.h b/platform/msm_shared/include/mmc_sdhci.h
index d54cc45..1612e61 100644
--- a/platform/msm_shared/include/mmc_sdhci.h
+++ b/platform/msm_shared/include/mmc_sdhci.h
@@ -204,7 +204,7 @@
({ \
uint32_t indx = (start) / (size_of); \
uint32_t offset = (start) % (size_of); \
- uint32_t mask = (((len)<(size_of))? 1<<(len):0) - 1; \
+ uint32_t mask = (((len)<(size_of))? 1ULL<<(len):0) - 1; \
uint32_t unpck = array[indx] >> offset; \
uint32_t indx2 = ((start) + (len) - 1) / (size_of); \
if(indx2 > indx) \
diff --git a/platform/msm_shared/include/msm_panel.h b/platform/msm_shared/include/msm_panel.h
index cbf04ac..6c55f0e 100755
--- a/platform/msm_shared/include/msm_panel.h
+++ b/platform/msm_shared/include/msm_panel.h
@@ -52,6 +52,10 @@
#define EDP_PANEL 12 /* EDP */
#define QPIC_PANEL 13 /* QPIC */
+#define DISPLAY_UNKNOWN 0
+#define DISPLAY_1 1
+#define DISPLAY_2 2
+
enum mdss_mdp_pipe_type {
MDSS_MDP_PIPE_TYPE_VIG,
MDSS_MDP_PIPE_TYPE_RGB,
@@ -218,6 +222,10 @@
uint8_t mode_gpio_state;
uint32_t signature;
uint32_t use_enable_gpio;
+ uint32_t ctl_base;
+ uint32_t phy_base;
+ uint32_t sctl_base;
+ uint32_t sphy_base;
};
struct edp_panel_info {
@@ -256,6 +264,7 @@
uint32_t wait_cycle;
uint32_t clk_rate;
uint32_t orientation;
+ uint32_t dest;
/* Select pipe type for handoff */
uint32_t pipe_type;
char lowpowerstop;
diff --git a/platform/msm_shared/include/qgic.h b/platform/msm_shared/include/qgic.h
index cb4c573..9bc66ff 100644
--- a/platform/msm_shared/include/qgic.h
+++ b/platform/msm_shared/include/qgic.h
@@ -31,6 +31,9 @@
#define __PLATFORM_MSM_SHARED_QGIC_H
#include "qgic_common.h"
+#include <platform/iomap.h>
+#include <platform/interrupts.h>
+#include <arch/arm.h>
#define GIC_CPU_REG(off) (MSM_GIC_CPU_BASE + (off))
@@ -50,4 +53,9 @@
uint32_t qgic_read_iar(void);
void qgic_write_eoi(uint32_t);
+enum handler_return gic_platform_irq(struct arm_iframe *frame);
+void gic_platform_fiq(struct arm_iframe *frame);
+status_t gic_mask_interrupt(unsigned int vector);
+status_t gic_unmask_interrupt(unsigned int vector);
+void gic_register_int_handler(unsigned int vector, int_handler func, void *arg);
#endif
diff --git a/platform/msm_shared/include/qtimer.h b/platform/msm_shared/include/qtimer.h
index fd680a0..d914a88 100644
--- a/platform/msm_shared/include/qtimer.h
+++ b/platform/msm_shared/include/qtimer.h
@@ -44,3 +44,5 @@
void qtimer_uninit();
void qtimer_init();
uint32_t qtimer_tick_rate();
+void udelay(unsigned usecs);
+void mdelay(unsigned msecs);
diff --git a/platform/msm_shared/include/scm.h b/platform/msm_shared/include/scm.h
index de046a4..2c5e14b 100644
--- a/platform/msm_shared/include/scm.h
+++ b/platform/msm_shared/include/scm.h
@@ -308,6 +308,7 @@
int scm_halt_pmic_arbiter();
int scm_call_atomic2(uint32_t svc, uint32_t cmd, uint32_t arg1, uint32_t arg2);
+int restore_secure_cfg(uint32_t id);
void scm_elexec_call(paddr_t kernel_entry, paddr_t dtb_offset);
void *get_canary();
diff --git a/platform/msm_shared/include/sdhci_msm.h b/platform/msm_shared/include/sdhci_msm.h
index fe68140..0cdfe2f 100644
--- a/platform/msm_shared/include/sdhci_msm.h
+++ b/platform/msm_shared/include/sdhci_msm.h
@@ -30,6 +30,7 @@
#define __SDHCI_MSM_H__
#include <kernel/event.h>
+#include <mmc_sdhci.h>
#define SDHCI_HC_START_BIT 0x0
#define SDHCI_HC_WIDTH 0x1
@@ -140,4 +141,5 @@
void sdhci_mode_disable(struct sdhci_host *host);
/* API: Toggle the bit for clock-data recovery */
void sdhci_msm_toggle_cdr(struct sdhci_host *host, bool enable);
+void sdhci_msm_set_mci_clk(struct sdhci_host *host);
#endif
diff --git a/platform/msm_shared/interrupts.c b/platform/msm_shared/interrupts.c
index 9d84bb2..2fdaf35 100644
--- a/platform/msm_shared/interrupts.c
+++ b/platform/msm_shared/interrupts.c
@@ -31,6 +31,7 @@
#include <platform/irqs.h>
#include <platform/interrupts.h>
#include <debug.h>
+#include <qgic.h>
extern int target_supports_qgic();
diff --git a/platform/msm_shared/mdp5.c b/platform/msm_shared/mdp5.c
index 63b824d..6c84522 100755
--- a/platform/msm_shared/mdp5.c
+++ b/platform/msm_shared/mdp5.c
@@ -138,12 +138,22 @@
/* For targets from MDP v1.5, MDP INTF registers are double buffered */
if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_108)) {
+ if (pinfo->dest == DISPLAY_2) {
+ *ctl0_reg_val |= BIT(31);
+ *ctl1_reg_val |= BIT(30);
+ } else {
*ctl0_reg_val |= BIT(30);
*ctl1_reg_val |= BIT(31);
+ }
} else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) ||
(mdss_mdp_rev == MDSS_MDP_HW_REV_109)) {
+ if (pinfo->dest == DISPLAY_2) {
+ *ctl0_reg_val |= BIT(29);
+ *ctl1_reg_val |= BIT(30);
+ } else {
*ctl0_reg_val |= BIT(30);
*ctl1_reg_val |= BIT(29);
+ }
}
}
@@ -386,12 +396,11 @@
free_smp_offset);
}
-void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
+static void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base)
{
uint32_t hsync_period, vsync_period;
uint32_t hsync_start_x, hsync_end_x;
uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
- uint32_t mdss_mdp_intf_off;
uint32_t adjust_xres = 0;
struct lcdc_panel_info *lcdc = NULL;
@@ -437,9 +446,6 @@
itp.underflow_clr = pinfo->lcdc.underflow_clr;
itp.hsync_skew = pinfo->lcdc.hsync_skew;
-
- mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
-
hsync_period = itp.hsync_pulse_width + itp.h_back_porch +
itp.width + itp.h_front_porch;
@@ -466,39 +472,38 @@
hsync_ctl = (hsync_period << 16) | itp.hsync_pulse_width;
display_hctl = (hsync_end_x << 16) | hsync_start_x;
- writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off);
+ writel(hsync_ctl, MDP_HSYNC_CTL + intf_base);
writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_VSYNC_PERIOD_F1 + intf_base);
writel(itp.vsync_pulse_width*hsync_period,
MDP_VSYNC_PULSE_WIDTH_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off);
- writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + intf_base);
+ writel(display_hctl, MDP_DISPLAY_HCTL + intf_base);
writel(display_vstart, MDP_DISPLAY_V_START_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_DISPLAY_V_START_F1 + intf_base);
writel(display_vend, MDP_DISPLAY_V_END_F0 +
- mdss_mdp_intf_off);
- writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off);
- writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off);
- writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off);
+ intf_base);
+ writel(0x00, MDP_DISPLAY_V_END_F1 + intf_base);
+ writel(0x00, MDP_ACTIVE_HCTL + intf_base);
+ writel(0x00, MDP_ACTIVE_V_START_F0 + intf_base);
+ writel(0x00, MDP_ACTIVE_V_START_F1 + intf_base);
+ writel(0x00, MDP_ACTIVE_V_END_F0 + intf_base);
+ writel(0x00, MDP_ACTIVE_V_END_F1 + intf_base);
+ writel(0xFF, MDP_UNDERFFLOW_COLOR + intf_base);
- if (intf_base == MDP_INTF_0_BASE) /* eDP */
- writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ if (intf_base == (MDP_INTF_0_BASE + mdss_mdp_intf_offset())) /* eDP */
+ writel(0x212A, MDP_PANEL_FORMAT + intf_base);
else
- writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x213F, MDP_PANEL_FORMAT + intf_base);
}
-void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
+static void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo,
uint32_t intf_base)
{
uint32_t mdp_hw_rev = readl(MDP_HW_REV);
- uint32_t mdss_mdp_intf_off;
uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines;
uint32_t adjust_xres = 0;
@@ -520,8 +525,6 @@
lcdc->v_back_porch >= MDP_MIN_FETCH)
return;
- mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset();
-
adjust_xres = pinfo->xres;
if (pinfo->lcdc.split_display)
adjust_xres /= 2;
@@ -547,8 +550,8 @@
fetch_start = (v_total - fetch_lines) * h_total + 1;
- writel(fetch_start, MDP_PROG_FETCH_START + mdss_mdp_intf_off);
- writel(BIT(31), MDP_INTF_CONFIG + mdss_mdp_intf_off);
+ writel(fetch_start, MDP_PROG_FETCH_START + intf_base);
+ writel(BIT(31), MDP_INTF_CONFIG + intf_base);
}
void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info
@@ -749,17 +752,41 @@
static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo,
int is_main_ctl)
{
- if (pinfo->lcdc.pipe_swap) {
- if (is_main_ctl)
- return BIT(4) | BIT(5); /* Interface 2 */
- else
- return BIT(5); /* Interface 1 */
+ uint32_t mctl_intf_sel;
+ uint32_t sctl_intf_sel;
+
+ if ((pinfo->dest == DISPLAY_2) ||
+ ((pinfo->dest = DISPLAY_1) && (pinfo->lcdc.pipe_swap))) {
+ mctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */
+ sctl_intf_sel = BIT(5); /* Interface 1 */
} else {
- if (is_main_ctl)
- return BIT(5); /* Interface 1 */
- else
- return BIT(4) | BIT(5); /* Interface 2 */
+ mctl_intf_sel = BIT(5); /* Interface 1 */
+ sctl_intf_sel = BIT(4) | BIT(5); /* Interface 2 */
}
+ dprintf(SPEW, "%s: main ctl dest=%s sec ctl dest=%s\n", __func__,
+ (mctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1",
+ (sctl_intf_sel & BIT(4)) ? "Intf2" : "Intf1");
+ return is_main_ctl ? mctl_intf_sel : sctl_intf_sel;
+}
+
+static void mdp_set_intf_base(struct msm_panel_info *pinfo,
+ uint32_t *intf_sel, uint32_t *sintf_sel,
+ uint32_t *intf_base, uint32_t *sintf_base)
+{
+ if (pinfo->dest == DISPLAY_2) {
+ *intf_sel = BIT(16);
+ *sintf_sel = BIT(8);
+ *intf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
+ *sintf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
+ } else {
+ *intf_sel = BIT(8);
+ *sintf_sel = BIT(16);
+ *intf_base = MDP_INTF_1_BASE + mdss_mdp_intf_offset();
+ *sintf_base = MDP_INTF_2_BASE + mdss_mdp_intf_offset();
+ }
+ dprintf(SPEW, "%s: main intf=%s, sec intf=%s\n", __func__,
+ (pinfo->dest == DISPLAY_2) ? "Intf2" : "Intf1",
+ (pinfo->dest == DISPLAY_2) ? "Intf1" : "Intf2");
}
int mdp_dsi_video_config(struct msm_panel_info *pinfo,
@@ -767,16 +794,19 @@
{
int ret = NO_ERROR;
struct lcdc_panel_info *lcdc = NULL;
- uint32_t intf_sel = 0x100;
+ uint32_t intf_sel, sintf_sel;
+ uint32_t intf_base, sintf_base;
uint32_t left_pipe, right_pipe;
uint32_t reg;
- mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE);
- mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE);
+ mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);
+
+ mdss_intf_tg_setup(pinfo, intf_base);
+ mdss_intf_fetch_start_config(pinfo, intf_base);
if (pinfo->mipi.dual_dsi) {
- mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE);
- mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE);
+ mdss_intf_tg_setup(pinfo, sintf_base);
+ mdss_intf_fetch_start_config(pinfo, sintf_base);
}
mdp_clk_gating_ctrl();
@@ -815,7 +845,7 @@
reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0);
writel(reg, MDP_CTL_1_BASE + CTL_TOP);
}
- intf_sel |= BIT(16); /* INTF 2 enable */
+ intf_sel |= sintf_sel; /* INTF 2 enable */
}
writel(intf_sel, MDP_DISP_INTF_SEL);
@@ -901,13 +931,13 @@
int mdp_dsi_cmd_config(struct msm_panel_info *pinfo,
struct fbcon_config *fb)
{
- uint32_t intf_sel = BIT(8);
+ uint32_t intf_sel, sintf_sel;
+ uint32_t intf_base, sintf_base;
uint32_t reg;
int ret = NO_ERROR;
uint32_t left_pipe, right_pipe;
struct lcdc_panel_info *lcdc = NULL;
- uint32_t mdss_mdp_intf_off = 0;
if (pinfo == NULL)
return ERR_INVALID_ARGS;
@@ -916,6 +946,8 @@
if (lcdc == NULL)
return ERR_INVALID_ARGS;
+ mdp_set_intf_base(pinfo, &intf_sel, &sintf_sel, &intf_base, &sintf_base);
+
if (pinfo->lcdc.split_display) {
reg = BIT(1); /* Command mode */
if (pinfo->lcdc.pipe_swap)
@@ -932,12 +964,10 @@
writel(BIT(5), MDP_REG_PPB0_CNTL);
}
- mdss_mdp_intf_off = mdss_mdp_intf_offset();
-
mdp_clk_gating_ctrl();
if (pinfo->mipi.dual_dsi)
- intf_sel |= BIT(16); /* INTF 2 enable */
+ intf_sel |= sintf_sel; /* INTF 2 enable */
writel(intf_sel, MDP_DISP_INTF_SEL);
@@ -954,7 +984,7 @@
mdss_layer_mixer_setup(fb, pinfo);
- writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x213F, MDP_PANEL_FORMAT + intf_base);
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1);
writel(reg, MDP_CTL_0_BASE + CTL_TOP);
@@ -962,7 +992,7 @@
mdss_fbc_cfg(pinfo);
if (pinfo->mipi.dual_dsi) {
- writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off);
+ writel(0x213F, sintf_base + MDP_PANEL_FORMAT);
if (!pinfo->lcdc.dst_split) {
reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0);
writel(reg, MDP_CTL_1_BASE + CTL_TOP);
@@ -975,20 +1005,33 @@
int mdp_dsi_video_on(struct msm_panel_info *pinfo)
{
uint32_t ctl0_reg_val, ctl1_reg_val;
+ uint32_t timing_engine_en;
+
mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val);
writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH);
writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH);
- writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset());
+
+ if (pinfo->dest == DISPLAY_1)
+ timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
+ else
+ timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
+ writel(0x01, timing_engine_en + mdss_mdp_intf_offset());
return NO_ERROR;
}
-int mdp_dsi_video_off()
+int mdp_dsi_video_off(struct msm_panel_info *pinfo)
{
+ uint32_t timing_engine_en;
+
+ if (pinfo->dest == DISPLAY_1)
+ timing_engine_en = MDP_INTF_1_TIMING_ENGINE_EN;
+ else
+ timing_engine_en = MDP_INTF_2_TIMING_ENGINE_EN;
+
if(!target_cont_splash_screen())
{
- writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN +
- mdss_mdp_intf_offset());
+ writel(0x00000000, timing_engine_en + mdss_mdp_intf_offset());
mdelay(60);
/* Ping-Pong done Tear Check Read/Write */
/* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */
diff --git a/platform/msm_shared/mipi_dsi.c b/platform/msm_shared/mipi_dsi.c
index 08b675f..0bb3274 100644
--- a/platform/msm_shared/mipi_dsi.c
+++ b/platform/msm_shared/mipi_dsi.c
@@ -69,20 +69,21 @@
static uint32_t response_value = 0;
-uint32_t mdss_dsi_read_panel_signature(uint32_t panel_signature)
+static uint32_t mdss_dsi_read_panel_signature(struct mipi_panel_info *mipi)
{
uint32_t rec_buf[1];
uint32_t *lp = rec_buf, data;
int ret = response_value;
+ uint32_t panel_signature = mipi->signature;
#if (DISPLAY_TYPE_MDSS == 1)
if (ret && ret != panel_signature)
goto exit_read_signature;
- ret = mdss_dsi_cmds_tx(&read_ddb_start_cmd, 1, 0);
+ ret = mdss_dsi_cmds_tx(mipi, &read_ddb_start_cmd, 1, 0);
if (ret)
goto exit_read_signature;
- if (!mdss_dsi_cmds_rx(&lp, 1, 1))
+ if (!mdss_dsi_cmds_rx(mipi, &lp, 1, 1))
goto exit_read_signature;
data = ntohl(*lp);
@@ -99,27 +100,28 @@
return ret;
}
-static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi)
+static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi,
+ uint32_t ctl_base, uint32_t sctl_base)
{
uint32_t ReadValue;
uint32_t count = 0;
int status = 0;
- uint32_t ctl_base = dual_dsi ? MIPI_DSI1_BASE : MIPI_DSI0_BASE;
+ uint32_t base = dual_dsi ? sctl_base : ctl_base;
#if (DISPLAY_TYPE_MDSS == 1)
- writel(0x03030303, MIPI_DSI0_BASE + INT_CTRL);
- writel(0x1, MIPI_DSI0_BASE + CMD_MODE_DMA_SW_TRIGGER);
+ writel(0x03030303, ctl_base + INT_CTRL);
+ writel(0x1, ctl_base + CMD_MODE_DMA_SW_TRIGGER);
dsb();
if (dual_dsi) {
- writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL);
- writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER);
+ writel(0x03030303, sctl_base + INT_CTRL);
+ writel(0x1, sctl_base + CMD_MODE_DMA_SW_TRIGGER);
dsb();
}
- ReadValue = readl(ctl_base + INT_CTRL) & 0x00000001;
+ ReadValue = readl(base + INT_CTRL) & 0x00000001;
while (ReadValue != 0x00000001) {
- ReadValue = readl(ctl_base + INT_CTRL) & 0x00000001;
+ ReadValue = readl(base + INT_CTRL) & 0x00000001;
count++;
if (count > 0xffff) {
status = FAIL;
@@ -129,30 +131,29 @@
}
}
- writel((readl(ctl_base + INT_CTRL) | 0x01000001),
- ctl_base + INT_CTRL);
+ writel((readl(base + INT_CTRL) | 0x01000001), base + INT_CTRL);
dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
#endif
return status;
}
-static int mdss_dsi_wait4_video_done()
+static int mdss_dsi_wait4_video_done(uint32_t ctl_base)
{
unsigned long read;
unsigned long count = 0;
int status = 0;
/* If video mode is not enabled, return here */
- if ((readl(MIPI_DSI0_BASE + CTRL) & BIT(1)) == 0)
+ if ((readl(ctl_base + CTRL) & BIT(1)) == 0)
return 0;
- read = readl(MIPI_DSI0_BASE + INT_CTRL);
+ read = readl(ctl_base + INT_CTRL);
/* Enable VIDEO MODE DONE MASK and clear the interrupt */
read = read | DSI_VIDEO_MODE_DONE_MASK | DSI_VIDEO_MODE_DONE_AK;
- writel(read, MIPI_DSI0_BASE + INT_CTRL);
+ writel(read, ctl_base + INT_CTRL);
dsb();
do {
- read = readl(MIPI_DSI0_BASE + INT_CTRL) &
+ read = readl(ctl_base + INT_CTRL) &
DSI_VIDEO_MODE_DONE_STAT;
count++;
if (count > 0xffff) {
@@ -163,8 +164,7 @@
}
} while (!read);
- writel((readl(MIPI_DSI0_BASE + INT_CTRL) | 0x01000001),
- MIPI_DSI0_BASE + INT_CTRL);
+ writel((readl(ctl_base + INT_CTRL) | 0x01000001), ctl_base + INT_CTRL);
dprintf(SPEW, "Panel wait_4_video_done: Recieved video mode done ack\n");
/* Skip BLLP 4ms */
@@ -173,7 +173,8 @@
return status;
}
-int mdss_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count, char dual_dsi)
+int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi,
+ struct mipi_dsi_cmd *cmds, int count, char dual_dsi)
{
int ret = 0;
#if (DISPLAY_TYPE_MDSS == 1)
@@ -182,6 +183,16 @@
uint8_t pload[256];
uint32_t off;
uint32_t size;
+ uint32_t ctl_base, sctl_base;
+
+ /* if dest controller is not specified, default to DSI0 */
+ if (!mipi) {
+ ctl_base = MIPI_DSI0_BASE;
+ sctl_base = MIPI_DSI1_BASE;
+ } else {
+ ctl_base = mipi->ctl_base;
+ sctl_base = mipi->sctl_base;
+ }
/* Align pload at 8 byte boundary */
off = (uint32_t) pload;
@@ -193,7 +204,7 @@
cm = cmds;
for (i = 0; i < count; i++) {
/* Wait for VIDEO_MODE_DONE */
- ret = mdss_dsi_wait4_video_done();
+ ret = mdss_dsi_wait4_video_done(ctl_base);
if (ret)
goto wait4video_error;
@@ -204,15 +215,15 @@
size = 4 - size;
size += cm->size;
memcpy((uint8_t *)off, (cm->payload), size);
- writel(off, MIPI_DSI0_BASE + DMA_CMD_OFFSET);
-
- writel(size, MIPI_DSI0_BASE + DMA_CMD_LENGTH);
+ writel(off, ctl_base + DMA_CMD_OFFSET);
+ writel(size, ctl_base + DMA_CMD_LENGTH);
if (dual_dsi) {
- writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET);
- writel(size, MIPI_DSI1_BASE + DMA_CMD_LENGTH);
+ writel(off, sctl_base + DMA_CMD_OFFSET);
+ writel(size, sctl_base + DMA_CMD_LENGTH);
}
dsb();
- ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi);
+ ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi, ctl_base,
+ sctl_base);
if (cm->wait)
mdelay(cm->wait);
else
@@ -224,12 +235,20 @@
return ret;
}
-int mdss_dsi_cmds_rx(uint32_t **rp, int rp_len, int rdbk_len)
+int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len,
+ int rdbk_len)
{
uint32_t *lp, data;
char *dp;
int i, off;
int rlen, res;
+ uint32_t ctl_base;
+
+ /* if dest controller is not specified, default to DSI0 */
+ if (!mipi)
+ ctl_base = MIPI_DSI0_BASE;
+ else
+ ctl_base = mipi->ctl_base;
if (rdbk_len > rp_len) {
return 0;
@@ -259,7 +278,7 @@
off += ((rlen - 1) * 4);
for (i = 0; i < rlen; i++) {
- data = readl(MIPI_DSI_BASE + off);
+ data = readl(ctl_base + off);
*lp = ntohl(data); /* to network byte order */
lp++;
@@ -276,15 +295,15 @@
return rdbk_len;
}
-static int mdss_dsi_cmd_bta_sw_trigger(void)
+static int mdss_dsi_cmd_bta_sw_trigger(uint32_t ctl_base)
{
uint32_t data;
int cnt = 0;
int err = 0;
- writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */
+ writel(0x01, ctl_base + 0x094); /* trigger */
while (cnt < 10000) {
- data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */
+ data = readl(ctl_base + 0x0004); /*DSI_STATUS */
if ((data & 0x0010) == 0)
break;
cnt++;
@@ -294,13 +313,13 @@
return err;
}
-int mdss_dsi_host_init(struct mipi_dsi_panel_config *pinfo, uint32_t
+int mdss_dsi_host_init(struct mipi_panel_info *mipi, uint32_t
dual_dsi, uint32_t broadcast)
{
uint8_t DMA_STREAM1 = 0; // for mdp display processor path
uint8_t EMBED_MODE1 = 1; // from frame buffer
uint8_t POWER_MODE2 = 1; // from frame buffer
- uint8_t PACK_TYPE1; // long packet
+ uint8_t PACK_TYPE1 = 0; // long packet
uint8_t VC1 = 0;
uint8_t DT1 = 0; // non embedded mode
uint8_t WC1 = 0; // for non embedded mode only
@@ -311,7 +330,7 @@
uint32_t ctrl_mode = 0x105; //Default is command mode to send cmds.
#if (DISPLAY_TYPE_MDSS == 1)
- switch (pinfo->num_of_lanes) {
+ switch (mipi->num_of_lanes) {
default:
case 1:
DLNx_EN = 1; // 1 lane
@@ -327,11 +346,10 @@
break;
}
- PACK_TYPE1 = pinfo->pack;
- lane_swap = pinfo->lane_swap;
- timing_ctl = ((pinfo->t_clk_post << 8) | pinfo->t_clk_pre);
+ lane_swap = mipi->lane_swap;
+ timing_ctl = ((mipi->t_clk_post << 8) | mipi->t_clk_pre);
- if (pinfo->cmds_post_tg) {
+ if (mipi->cmds_post_tg) {
/*
* Need to send pixel data before sending the ON commands
* so need to configure controller to VIDEO MODE.
@@ -340,42 +358,41 @@
}
if (dual_dsi) {
- writel(0x0001, MIPI_DSI1_BASE + SOFT_RESET);
- writel(0x0000, MIPI_DSI1_BASE + SOFT_RESET);
+ writel(0x0001, mipi->sctl_base + SOFT_RESET);
+ writel(0x0000, mipi->sctl_base + SOFT_RESET);
- writel((0 << 16) | 0x3f, MIPI_DSI1_BASE + CLK_CTRL); /* Turn on all DSI Clks */
- writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI1_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw
- // trigger 0x4; dma stream1
+ /* Turn on all DSI Clks */
+ writel((0 << 16) | 0x3f, mipi->sctl_base + CLK_CTRL);
+ writel(DMA_STREAM1 << 8 | 0x04, mipi->sctl_base + TRIG_CTRL);
- writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, MIPI_DSI1_BASE + CTRL); // reg 0x00 for this
- // build
+ writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->sctl_base + CTRL);
writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
| PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
- MIPI_DSI1_BASE + COMMAND_MODE_DMA_CTRL);
+ mipi->sctl_base + COMMAND_MODE_DMA_CTRL);
- if (readl(MIPI_DSI_BASE) == DSI_HW_REV_103_1) /*for 8939 hw dsi1 has Lane_map as 3210*/
+ /* for 8939 hw dsi1 has Lane_map as 3210 */
+ if (readl(MIPI_DSI_BASE) == DSI_HW_REV_103_1)
lane_swap_dsi1 = 0x7;
else
lane_swap_dsi1 = lane_swap;
- writel(lane_swap_dsi1, MIPI_DSI1_BASE + LANE_SWAP_CTL);
- writel(timing_ctl, MIPI_DSI1_BASE + TIMING_CTL);
+ writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL);
+ writel(timing_ctl, mipi->sctl_base + TIMING_CTL);
}
- writel(0x0001, MIPI_DSI0_BASE + SOFT_RESET);
- writel(0x0000, MIPI_DSI0_BASE + SOFT_RESET);
+ writel(0x0001, mipi->ctl_base + SOFT_RESET);
+ writel(0x0000, mipi->ctl_base + SOFT_RESET);
- writel((0 << 16) | 0x3f, MIPI_DSI0_BASE + CLK_CTRL); /* Turn on all DSI Clks */
- writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI0_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw
- // trigger 0x4; dma stream1
+ /* Turn on all DSI Clks */
+ writel((0 << 16) | 0x3f, mipi->ctl_base + CLK_CTRL);
+ writel(DMA_STREAM1 << 8 | 0x04, mipi->ctl_base + TRIG_CTRL);
- writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, MIPI_DSI0_BASE + CTRL); // reg 0x00 for this
- // build
+ writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->ctl_base + CTRL);
writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26
| PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
- MIPI_DSI0_BASE + COMMAND_MODE_DMA_CTRL);
+ mipi->ctl_base + COMMAND_MODE_DMA_CTRL);
- writel(lane_swap, MIPI_DSI0_BASE + LANE_SWAP_CTL);
- writel(timing_ctl, MIPI_DSI0_BASE + TIMING_CTL);
+ writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL);
+ writel(timing_ctl, mipi->ctl_base + TIMING_CTL);
#endif
return 0;
@@ -385,69 +402,72 @@
{
#if (DISPLAY_TYPE_MDSS == 1)
unsigned long read_val = 0;
+ uint32_t ctl_base = pinfo->mipi.ctl_base;
+ uint32_t sctl_base = pinfo->mipi.sctl_base;
+
if (pinfo->mipi.panel_off_cmds) {
/*
* Once MDP TG is disabled, reset of DSI controller is
* needed before we send panel OFF commands.
*/
if (pinfo->type == MIPI_VIDEO_PANEL) {
- read_val = readl(MIPI_DSI0_BASE + CTRL);
- writel((read_val & ~BIT(0)), MIPI_DSI0_BASE + CTRL);
- writel(0x0001, MIPI_DSI0_BASE + SOFT_RESET);
+ read_val = readl(ctl_base + CTRL);
+ writel((read_val & ~BIT(0)), ctl_base + CTRL);
+ writel(0x0001, ctl_base + SOFT_RESET);
dsb();
- writel(0x0000, MIPI_DSI0_BASE + SOFT_RESET);
+ writel(0x0000, ctl_base + SOFT_RESET);
dsb();
/* Enable cmd mode only */
writel(((read_val & ~BIT(1)) | BIT(2)),
- MIPI_DSI0_BASE + CTRL);
+ ctl_base + CTRL);
}
if (pinfo->mipi.broadcast) {
if (pinfo->type == MIPI_VIDEO_PANEL) {
- read_val = readl(MIPI_DSI1_BASE + CTRL);
+ read_val = readl(sctl_base + CTRL);
writel((read_val & ~BIT(0)),
- MIPI_DSI1_BASE + CTRL);
+ sctl_base + CTRL);
- writel(0x0001, MIPI_DSI1_BASE + SOFT_RESET);
+ writel(0x0001, sctl_base + SOFT_RESET);
dsb();
- writel(0x0000, MIPI_DSI1_BASE + SOFT_RESET);
+ writel(0x0000, sctl_base + SOFT_RESET);
dsb();
writel(((read_val & ~BIT(1)) | BIT(2)),
- MIPI_DSI1_BASE + CTRL);
+ sctl_base + CTRL);
}
}
- mdss_dsi_cmds_tx(pinfo->mipi.panel_off_cmds,
+ mdss_dsi_cmds_tx(&pinfo->mipi, pinfo->mipi.panel_off_cmds,
pinfo->mipi.num_of_panel_off_cmds,
pinfo->mipi.broadcast);
}
#endif
}
-int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t
+int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, uint32_t
broadcast)
{
int status = 0;
uint32_t ctrl_mode = 0;
#if (DISPLAY_TYPE_MDSS == 1)
- if (!pinfo->panel_on_cmds)
+ if (!mipi->panel_on_cmds)
goto end;
- ctrl_mode = readl(MIPI_DSI0_BASE + CTRL);
+ ctrl_mode = readl(mipi->ctl_base + CTRL);
/* Enable command mode before sending the commands. */
- writel(ctrl_mode | 0x04, MIPI_DSI0_BASE + CTRL);
+ writel(ctrl_mode | 0x04, mipi->ctl_base + CTRL);
if (broadcast)
- writel(ctrl_mode | 0x04, MIPI_DSI1_BASE + CTRL);
- status = mdss_dsi_cmds_tx(pinfo->panel_on_cmds,
- pinfo->num_of_panel_on_cmds, broadcast);
- writel(ctrl_mode, MIPI_DSI0_BASE + CTRL);
+ writel(ctrl_mode | 0x04, mipi->sctl_base + CTRL);
+ status = mdss_dsi_cmds_tx(mipi, mipi->panel_on_cmds,
+ mipi->num_of_panel_on_cmds, broadcast);
+ writel(ctrl_mode, mipi->ctl_base + CTRL);
if (broadcast)
- writel(ctrl_mode, MIPI_DSI1_BASE + CTRL);
+ writel(ctrl_mode, mipi->sctl_base + CTRL);
if (!broadcast && !status && target_panel_auto_detect_enabled())
- status = mdss_dsi_read_panel_signature(pinfo->signature);
+ status = mdss_dsi_read_panel_signature(mipi);
end:
#endif
@@ -561,37 +581,32 @@
{
int ret = NO_ERROR;
struct msm_panel_info *pinfo;
- struct mipi_dsi_panel_config mipi_pinfo;
+ struct mipi_panel_info *mipi;
#if (DISPLAY_TYPE_MDSS == 1)
if (!panel)
return ERR_INVALID_ARGS;
pinfo = &(panel->panel_info);
- mipi_pinfo.mode = pinfo->mipi.mode;
- mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
- mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db;
- mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds;
- mipi_pinfo.num_of_panel_on_cmds = pinfo->mipi.num_of_panel_on_cmds;
- mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
- mipi_pinfo.pack = 0;
- mipi_pinfo.t_clk_pre = pinfo->mipi.t_clk_pre;
- mipi_pinfo.t_clk_post = pinfo->mipi.t_clk_post;
- mipi_pinfo.signature = pinfo->mipi.signature;
- mipi_pinfo.cmds_post_tg = pinfo->mipi.cmds_post_tg;
+ mipi = &(pinfo->mipi);
- mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE, DSI0_PHY_BASE);
- if (pinfo->mipi.dual_dsi)
- mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE, DSI1_PHY_BASE);
+ dprintf(SPEW, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base,
+ mipi->phy_base);
- ret = mdss_dsi_host_init(&mipi_pinfo, pinfo->mipi.dual_dsi,
- pinfo->mipi.broadcast);
+ mdss_dsi_phy_init(mipi, mipi->ctl_base, mipi->phy_base);
+ if (mipi->dual_dsi)
+ mdss_dsi_phy_init(mipi, mipi->sctl_base, mipi->sphy_base);
+
+ ret = mdss_dsi_host_init(mipi, mipi->dual_dsi,
+ mipi->broadcast);
if (ret) {
dprintf(CRITICAL, "dsi host init error\n");
goto error;
}
- mdss_dsi_phy_contention_detection(&mipi_pinfo, DSI0_PHY_BASE);
+ mdss_dsi_phy_contention_detection(mipi, mipi->phy_base);
+ if (mipi->dual_dsi)
+ mdss_dsi_phy_contention_detection(mipi, mipi->sphy_base);
if (panel->pre_init_func) {
ret = panel->pre_init_func();
@@ -601,8 +616,8 @@
}
}
- if (!mipi_pinfo.cmds_post_tg) {
- ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
+ if (!mipi->cmds_post_tg) {
+ ret = mdss_dsi_panel_initialize(mipi, mipi->broadcast);
if (ret) {
dprintf(CRITICAL, "dsi panel init error\n");
goto error;
@@ -621,15 +636,9 @@
{
int ret = 0;
struct msm_panel_info *pinfo = &(panel->panel_info);
- struct mipi_dsi_panel_config mipi_pinfo;
if (pinfo->mipi.cmds_post_tg) {
- mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds;
- mipi_pinfo.num_of_panel_on_cmds =
- pinfo->mipi.num_of_panel_on_cmds;
- mipi_pinfo.signature = pinfo->mipi.signature;
-
- ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast);
+ ret = mdss_dsi_panel_initialize(&pinfo->mipi, pinfo->mipi.broadcast);
if (ret) {
dprintf(CRITICAL, "dsi panel init error\n");
}
@@ -701,18 +710,18 @@
return 0;
}
-int mipi_dsi_on()
+int mipi_dsi_on(struct msm_panel_info *pinfo)
{
int ret = NO_ERROR;
unsigned long ReadValue;
unsigned long count = 0;
- ReadValue = readl(MIPI_DSI0_BASE + INT_CTRL) & 0x00010000;
+ ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000;
mdelay(10);
while (ReadValue != 0x00010000) {
- ReadValue = readl(MIPI_DSI0_BASE + INT_CTRL) & 0x00010000;
+ ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000;
count++;
if (count > 0xffff) {
dprintf(CRITICAL, "Video lane test failed\n");
@@ -729,13 +738,13 @@
if(!target_cont_splash_screen())
{
mdss_dsi_panel_shutdown(pinfo);
- writel(0, MIPI_DSI0_BASE + CLK_CTRL);
- writel(0x1F1, MIPI_DSI0_BASE + CTRL);
+ writel(0, pinfo->mipi.ctl_base + CLK_CTRL);
+ writel(0x1F1, pinfo->mipi.ctl_base + CTRL);
}
- writel(0x1115501, MIPI_DSI0_BASE + INT_CTRL);
+ writel(0x1115501, pinfo->mipi.ctl_base + INT_CTRL);
if (pinfo->mipi.broadcast)
- writel(0x1115501, MIPI_DSI1_BASE + INT_CTRL);
+ writel(0x1115501, pinfo->mipi.sctl_base + INT_CTRL);
return NO_ERROR;
}
diff --git a/platform/msm_shared/mipi_dsi_autopll_20nm.c b/platform/msm_shared/mipi_dsi_autopll_20nm.c
index 0f7052a..baa520b 100644
--- a/platform/msm_shared/mipi_dsi_autopll_20nm.c
+++ b/platform/msm_shared/mipi_dsi_autopll_20nm.c
@@ -154,29 +154,33 @@
return status;
}
-uint32_t mdss_dsi_pll_20nm_sw_reset_st_machine(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_common_block(uint32_t pll_base)
{
- writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG1);
- writel(0x64, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_START_SEG2);
- writel(0x15, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_CONTROL);
-
- writel(0x20, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL);
- writel(0x07, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL2);
+ writel(0x82, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x2a, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
+ writel(0x2b, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
- writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
-}
-
-static void pll_20nm_phy_kvco_config(uint32_t pll_base)
-{
-
+ writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL);
+ writel(0x0e, pll_base + MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL);
+ writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN);
+ writel(0x4a, pll_base + MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND);
writel(0x00, pll_base + MMSS_DSI_PHY_PLL_DIV_REF1);
writel(0x01, pll_base + MMSS_DSI_PHY_PLL_DIV_REF2);
+ writel(0x07, pll_base + MMSS_DSI_PHY_PLL_PLL_CNTRL);
+ writel(0x1f, pll_base + MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL);
writel(0x8a, pll_base + MMSS_DSI_PHY_PLL_KVCO_COUNT1);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CAL_CNTRL);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_KVCO_CODE);
+ writel(0x10, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG3);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SSC_EN_CENTER);
+ writel(0x0c, pll_base + MMSS_DSI_PHY_PLL_FAUX_EN);
+ writel(0x0a, pll_base + MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN);
+ writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL);
+ writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
}
-static void pll_20nm_phy_loop_bw_config(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_loop_bw(uint32_t pll_base)
{
writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_IP_SETI);
writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_PLL_CP_SETI);
@@ -185,74 +189,16 @@
writel(0x77, pll_base + MMSS_DSI_PHY_PLL_PLL_CRCTRL);
}
-static void pll_20nm_phy_config(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_phy_config(uint32_t pll_base)
{
- writel(0x40, pll_base + MMSS_DSI_PHY_PLL_SYS_CLK_CTRL);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CMN_MODE);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IE_TRIM);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_IP_TRIM);
- writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_CONTROL);
- writel(0x0e, pll_base + MMSS_DSI_PHY_PLL_IPTAT_TRIM_VCCA_TX_SEL);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_PHSEL_DC);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_CORE_CLK_IN_SYNC_SEL);
- writel(0x08, pll_base + MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN);
- writel(0x3f, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL1);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_ATB_SEL2);
- writel(0x4b, pll_base + MMSS_DSI_PHY_PLL_SYSCLK_EN_SEL_TXBAND);
- udelay(1000);
-
- pll_20nm_phy_kvco_config(pll_base);
-
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG1);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG2);
- writel(0x10, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG3);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_VREF_CFG4);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_BGTC);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_TEST_UPDN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_VCO_TUNE);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_PLL_AMP_OS);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_SSC_EN_CENTER);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_UP);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_DN);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_CODE_CAL_CSR);
- writel(0x00, pll_base + MMSS_DSI_PHY_PLL_RES_TRIM_EN_VCOCALDONE);
- writel(0x0c, pll_base + MMSS_DSI_PHY_PLL_FAUX_EN);
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_PLL_RXTXEPCLK_EN);
-
- writel(0x0f, pll_base + MMSS_DSI_PHY_PLL_LOW_POWER_RO_CONTROL);
- udelay(1000);
-
- pll_20nm_phy_loop_bw_config(pll_base);
+ mdss_dsi_pll_20nm_config_common_block(pll_base);
+ mdss_dsi_pll_20nm_config_loop_bw(pll_base);
}
-static void mdss_dsi_pll_20nm_disable(uint32_t pll_base)
+static void mdss_dsi_pll_20nm_config_vco_rate(uint32_t pll_base, struct mdss_dsi_pll_config *pd)
{
- dprintf(SPEW, "Disabling DSI PHY PLL \n");
- writel(0x042, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
- writel(0x002, pll_base + MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN);
- writel(0x002, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
- dmb();
-}
-int32_t mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
- struct mdss_dsi_pll_config *pd)
-{
uint32_t data;
-
- mdss_dsi_phy_sw_reset(ctl_base);
- pll_20nm_phy_config(pll_base);
-
- /*
- * For 20nm PHY, DSI PLL 1 drains some current in its reset state.
- * Need to turn off the DSI1 PLL explicitly.
- */
- if (ctl_base == MIPI_DSI0_BASE) {
- dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
- mdss_dsi_pll_20nm_disable(DSI1_PLL_BASE);
- }
-
/* set up divider */
data = readl(pll_base + MMSS_DSI_PHY_PLL_POST_DIVIDER_CONTROL);
data |= 0x080; /* bit 7 */
@@ -285,6 +231,21 @@
writel(((pd->lock_comp >> 16) & 0xff),
pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3);
+ writel(0x01, pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN);
+
+
+ dprintf(SPEW, "div frac1=0x%x, div frac2 = 0x%x, div frac3=0x%x\n",
+ readl(pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START1),
+ readl(pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START2),
+ readl(pll_base + MMSS_DSI_PHY_PLL_DIV_FRAC_START3));
+ dprintf(SPEW, "dec start1=0x%x, dec start2 = 0x%x\n",
+ readl(pll_base + MMSS_DSI_PHY_PLL_DEC_START1),
+ readl(pll_base + MMSS_DSI_PHY_PLL_DEC_START2));
+ dprintf(SPEW, "plllock cmp1=0x%x,plllock cmp2= 0x%x, plllock cmp3=0x%x\n",
+ readl(pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP1),
+ readl(pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP2),
+ readl(pll_base + MMSS_DSI_PHY_PLL_PLLLOCK_CMP3));
+
/*
* Make sure that PLL vco configuration is complete
* before controlling the state machine.
@@ -292,3 +253,47 @@
udelay(1000);
dmb();
}
+
+static void mdss_dsi_pll_20nm_config_resetsm(uint32_t pll_base)
+{
+ writel(0x24, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL);
+ writel(0x07, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL2);
+}
+
+static void mdss_dsi_pll_20nm_config_vco_start(uint32_t pll_base)
+{
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x02, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ udelay(10);
+ writel(0x03, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+}
+
+static void mdss_dsi_pll_20nm_disable(uint32_t pll_base)
+{
+ dprintf(SPEW, "Disabling DSI PHY PLL \n");
+ writel(0x02, pll_base + MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN);
+ writel(0x06, pll_base + MMSS_DSI_PHY_PLL_RESETSM_CNTRL3);
+ dmb();
+}
+
+void mdss_dsi_auto_pll_20nm_config(uint32_t pll_base, uint32_t ctl_base,
+ struct mdss_dsi_pll_config *pd)
+{
+
+ mdss_dsi_pll_20nm_phy_config(pll_base);
+
+ /*
+ * For 20nm PHY, DSI PLL 1 drains some current in its reset state.
+ * Need to turn off the DSI1 PLL explicitly.
+ */
+ if (ctl_base == MIPI_DSI0_BASE) {
+ dprintf(SPEW, "Calling disable function for PHY PLL 1 \n");
+ mdss_dsi_pll_20nm_disable(DSI1_PLL_BASE);
+ }
+
+ mdss_dsi_pll_20nm_config_vco_rate(pll_base, pd);
+
+ mdss_dsi_pll_20nm_config_resetsm(pll_base);
+ mdss_dsi_pll_20nm_config_vco_start(pll_base);
+ udelay(1000);
+}
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index ffcb407..d3d534b 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -53,33 +53,33 @@
#define TOTAL_LANE_COUNT 5
#define CONFIG_REG_FOR_EACH_LANE 9
-static void mipi_dsi_calibration(void)
+static void mipi_dsi_calibration(uint32_t ctl_base)
{
uint32_t i = 0;
uint32_t term_cnt = 5000;
- int32_t cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ int32_t cal_busy = readl(ctl_base + 0x550);
/* DSI1_DSIPHY_REGULATOR_CAL_PWR_CFG */
- writel(0x01, MIPI_DSI_BASE + 0x0518);
+ writel(0x01, ctl_base + 0x0518);
/* DSI1_DSIPHY_CAL_SW_CFG2 */
- writel(0x0, MIPI_DSI_BASE + 0x0534);
+ writel(0x0, ctl_base + 0x0534);
/* DSI1_DSIPHY_CAL_HW_CFG1 */
- writel(0x5a, MIPI_DSI_BASE + 0x053c);
+ writel(0x5a, ctl_base + 0x053c);
/* DSI1_DSIPHY_CAL_HW_CFG3 */
- writel(0x10, MIPI_DSI_BASE + 0x0544);
+ writel(0x10, ctl_base + 0x0544);
/* DSI1_DSIPHY_CAL_HW_CFG4 */
- writel(0x01, MIPI_DSI_BASE + 0x0548);
+ writel(0x01, ctl_base + 0x0548);
/* DSI1_DSIPHY_CAL_HW_CFG0 */
- writel(0x01, MIPI_DSI_BASE + 0x0538);
+ writel(0x01, ctl_base + 0x0538);
/* DSI1_DSIPHY_CAL_HW_TRIGGER */
- writel(0x01, MIPI_DSI_BASE + 0x0528);
+ writel(0x01, ctl_base + 0x0528);
/* DSI1_DSIPHY_CAL_HW_TRIGGER */
- writel(0x00, MIPI_DSI_BASE + 0x0528);
+ writel(0x00, ctl_base + 0x0528);
- cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ cal_busy = readl(ctl_base + 0x550);
while (cal_busy & 0x10) {
i++;
if (i > term_cnt) {
@@ -87,7 +87,7 @@
"exceeded polling TIMEOUT!\n");
break;
}
- cal_busy = readl(MIPI_DSI_BASE + 0x550);
+ cal_busy = readl(ctl_base + 0x550);
}
}
@@ -177,7 +177,7 @@
writel(pd->regulator[i], MIPI_DSI_BASE + off);
off += 4;
}
- mipi_dsi_calibration();
+ mipi_dsi_calibration(MIPI_DSI_BASE);
off = 0x0204; /* pll ctrl 1 - 19, skip 0 */
for (i = 1; i < 20; i++) {
@@ -216,10 +216,37 @@
udelay(100);
}
-int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t phy_base)
+static int mdss_dsi_20nm_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd, uint32_t phy_base)
{
/* DSI0 and DSI1 have a common regulator */
+ uint32_t off = 0x0280; /* phy regulator ctrl settings */
+ if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) {
+ /* LDO ctrl */
+ writel(0x1d, DSI0_PHY_BASE + MMSS_DSI_PHY_LDO_CTRL);
+ } else {
+ /* Regulator ctrl 1 */
+ writel(pd->regulator[1], DSI0_PHY_BASE + off + (4 * 1));
+ /* Regulator ctrl 2 */
+ writel(pd->regulator[2], DSI0_PHY_BASE + off + (4 * 2));
+ /* Regulator ctrl 3 */
+ writel(pd->regulator[3], DSI0_PHY_BASE + off + (4 * 3));
+ /* Regulator ctrl 4 */
+ writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4));
+ /* Regulator ctrl - CAL_PWR_CFG */
+ writel(pd->regulator[6], DSI0_PHY_BASE + off + (4 * 6));
+ /* LDO ctrl */
+ writel(0x00, phy_base + 0x01dc);
+ /* Regulator ctrl 0 */
+ writel(pd->regulator[0], DSI0_PHY_BASE + off + (4 * 0));
+ dmb();
+ }
+}
+
+static int mdss_dsi_phy_regulator_init(struct mdss_dsi_phy_ctrl *pd,
+ uint32_t phy_base)
+{
+ /* DSI0 and DSI1 have a common regulator */
uint32_t off = 0x0280; /* phy regulator ctrl settings */
if (pd->regulator_mode == DSI_PHY_REGULATOR_LDO_MODE) {
@@ -270,12 +297,12 @@
}
}
-int mdss_dsi_v2_phy_init(struct mipi_dsi_panel_config *pinfo, uint32_t ctl_base)
+int mdss_dsi_v2_phy_init(struct mipi_panel_info *mipi, uint32_t ctl_base)
{
struct mdss_dsi_phy_ctrl *pd;
uint32_t i, ln, off = 0, offset;
- pd = pinfo->mdss_dsi_phy_config;
+ pd = mipi->mdss_dsi_phy_db;
/* DSI PHY configuration */
off = 0x480;
writel(pd->strength[0], ctl_base + off + (4 * 0));
@@ -291,7 +318,7 @@
for (i = 0; i < 5; i++)
writel(pd->regulator[i], ctl_base + off + (4 * i));
- mipi_dsi_calibration();
+ mipi_dsi_calibration(ctl_base);
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
@@ -309,12 +336,12 @@
for (i = 0; i < 12; i++)
writel(pd->timing[i], ctl_base + off + (4 * i));
- if (1 == pinfo->num_of_lanes)
+ if (1 == mipi->num_of_lanes)
writel(0x8, ctl_base + 0x200 + (4 * 11));
- if (pinfo->lane_swap)
- writel(pinfo->lane_swap, ctl_base + 0x0ac);
+ if (mipi->lane_swap)
+ writel(mipi->lane_swap, ctl_base + 0x0ac);
/* T_CLK_POST, T_CLK_PRE for CLK lane P/N HS 200 mV timing
length should > data lane HS timing length */
@@ -322,16 +349,16 @@
return 0;
}
-static int mdss_dsi_phy_28nm_init(struct mipi_dsi_panel_config *pinfo,
+static int mdss_dsi_phy_28nm_init(struct mipi_panel_info *mipi,
uint32_t ctl_base, uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
uint32_t i, off = 0, ln, offset;
if (mdp_get_revision() == MDP_REV_304)
- return mdss_dsi_v2_phy_init(pinfo, ctl_base);
+ return mdss_dsi_v2_phy_init(mipi, ctl_base);
- pd = (pinfo->mdss_dsi_phy_config);
+ pd = (mipi->mdss_dsi_phy_db);
/* Strength ctrl 0 */
writel(pd->strength[0], phy_base + 0x0184);
@@ -389,7 +416,7 @@
}
void mdss_dsi_phy_contention_detection(
- struct mipi_dsi_panel_config *pinfo,
+ struct mipi_panel_info *mipi,
uint32_t phy_base)
{
struct mdss_dsi_phy_ctrl *pd;
@@ -397,48 +424,23 @@
if (mdp_get_revision() == MDP_REV_304)
return;
- pd = (pinfo->mdss_dsi_phy_config);
- writel(pd->strength[1], phy_base + 0x0188);
+ pd = (mipi->mdss_dsi_phy_db);
+ writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
dmb();
}
-static int mdss_dsi_phy_20nm_init(struct mipi_dsi_panel_config *pinfo,
+static int mdss_dsi_phy_20nm_init(struct mipi_panel_info *mipi,
uint32_t ctl_base, uint32_t phy_base)
{
- struct mdss_dsi_phy_ctrl *pd = pinfo->mdss_dsi_phy_config;
+ struct mdss_dsi_phy_ctrl *pd = mipi->mdss_dsi_phy_db;
uint32_t i, off = 0, ln, offset;
+ mdss_dsi_20nm_phy_regulator_init(pd, phy_base);
+
/* Strength ctrl 0 */
writel(pd->strength[0], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_0);
- mdss_dsi_phy_regulator_init(pd, phy_base);
-
- off = MMSS_DSI_PHY_TIMING_CTRL_0;
- for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) {
- writel(pd->timing[i], phy_base + off);
- dmb();
- }
-
- /* Currently the Phy settings for the DSI 0 is done in clk prepare*/
- if (phy_base == DSI1_PHY_BASE) {
- writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1);
- writel(0x05, phy_base + MMSS_DSI_PHY_CTRL_0);
- dmb();
-
- writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
- dmb();
-
- /* BITCLK_HS_SEL should be set to 0 for left */
- writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL);
-
- writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_2);
- writel(0x02, phy_base + MMSS_DSI_PHY_CTRL_2);
- writel(0x03, phy_base + MMSS_DSI_PHY_CTRL_2);
- dmb();
- }
-
- writel(pd->strength[1], phy_base + MMSS_DSI_PHY_STRENGTH_CTRL_1);
- dmb();
+ writel(0x00, phy_base + MMSS_DSI_PHY_GLBL_TEST_CTRL);
for (ln = 0; ln < TOTAL_LANE_COUNT; ln++) {
off = (ln * 0x40);
@@ -449,27 +451,27 @@
}
}
- dmb();
-
- off = MMSS_DSI_PHY_BIST_CTRL_0;
- for (i = 0; i < TOTAL_BIST_CTRL_CONFIG; i++, off +=4) {
- writel(pd->bistCtrl[i], phy_base + off);
+ off = MMSS_DSI_PHY_TIMING_CTRL_0;
+ for (i = 0; i < TOTAL_TIMING_CTRL_CONFIG; i++, off += 4) {
+ writel(pd->timing[i], phy_base + off);
+ dmb();
}
- dmb();
- writel(0x41b, ctl_base + MMSS_DSI_CLKOUT_TIMING_CTRL);
+ writel(0x00, phy_base + MMSS_DSI_PHY_CTRL_1);
+ dmb();
+ writel(0x7f, phy_base + MMSS_DSI_PHY_CTRL_0);
dmb();
}
-int mdss_dsi_phy_init (struct mipi_dsi_panel_config *pinfo,
+int mdss_dsi_phy_init (struct mipi_panel_info *mipi,
uint32_t ctl_base, uint32_t phy_base)
{
int ret;
- if (pinfo->mdss_dsi_phy_config->is_pll_20nm)
- ret = mdss_dsi_phy_20nm_init(pinfo, ctl_base, phy_base);
+ if (mipi->mdss_dsi_phy_db->is_pll_20nm)
+ ret = mdss_dsi_phy_20nm_init(mipi, ctl_base, phy_base);
else
- ret = mdss_dsi_phy_28nm_init(pinfo, ctl_base, phy_base);
+ ret = mdss_dsi_phy_28nm_init(mipi, ctl_base, phy_base);
return ret;
}
diff --git a/platform/msm_shared/mmc_sdhci.c b/platform/msm_shared/mmc_sdhci.c
index 5788bb7..2632961 100644
--- a/platform/msm_shared/mmc_sdhci.c
+++ b/platform/msm_shared/mmc_sdhci.c
@@ -36,6 +36,7 @@
#include <partition_parser.h>
#include <platform/iomap.h>
#include <platform/timer.h>
+#include <platform.h>
extern void clock_init_mmc(uint32_t);
extern void clock_config_mmc(uint32_t, uint32_t);
@@ -1136,7 +1137,6 @@
static uint32_t mmc_identify_card(struct sdhci_host *host, struct mmc_card *card)
{
uint32_t mmc_return = 0;
- uint32_t raw_csd[4];
/* Ask card to send its unique card identification (CID) number (CMD2) */
mmc_return = mmc_all_send_cid(host, card);
@@ -1228,7 +1228,6 @@
uint32_t mmc_sd_card_init(struct sdhci_host *host, struct mmc_card *card)
{
uint8_t i;
- uint32_t mmc_ret;
struct mmc_command cmd;
memset((struct mmc_command *)&cmd, 0, sizeof(struct mmc_command));
@@ -1473,7 +1472,6 @@
static uint32_t mmc_card_init(struct mmc_device *dev)
{
uint32_t mmc_return = 0;
- uint32_t status;
uint8_t bus_width = 0;
struct sdhci_host *host;
@@ -2108,7 +2106,6 @@
uint32_t blk_end;
uint32_t num_erase_grps;
uint64_t erase_timeout = 0;
- uint32_t *out;
struct mmc_card *card;
diff --git a/platform/msm_shared/mmc_wrapper.c b/platform/msm_shared/mmc_wrapper.c
index 0a7d5b4..bcec0ad 100755
--- a/platform/msm_shared/mmc_wrapper.c
+++ b/platform/msm_shared/mmc_wrapper.c
@@ -35,6 +35,7 @@
#include <target.h>
#include <string.h>
#include <partition_parser.h>
+#include <boot_device.h>
#include <dme.h>
/*
* Weak function for UFS.
@@ -134,7 +135,7 @@
val = mmc_sdhci_write((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (write_size / block_size));
if (val)
{
- dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Writing block @ %x\n",(unsigned int)(data_addr / block_size));
return val;
}
sptr += write_size;
@@ -146,7 +147,7 @@
val = mmc_sdhci_write((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (data_len / block_size));
if (val)
- dprintf(CRITICAL, "Failed Writing block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Writing block @ %x\n",(unsigned int)(data_addr / block_size));
}
else
{
@@ -196,7 +197,7 @@
ret = mmc_sdhci_read((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (read_size / block_size));
if (ret)
{
- dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Reading block @ %x\n",(unsigned int) (data_addr / block_size));
return ret;
}
sptr += read_size;
@@ -208,7 +209,7 @@
ret = mmc_sdhci_read((struct mmc_device *)dev, (void *)sptr, (data_addr / block_size), (data_len / block_size));
if (ret)
- dprintf(CRITICAL, "Failed Reading block @ %x\n", (data_addr / block_size));
+ dprintf(CRITICAL, "Failed Reading block @ %x\n",(unsigned int) (data_addr / block_size));
}
else
{
@@ -289,7 +290,7 @@
}
else
{
- dprintf(CRITICAL, "Erase Fail: Erase size: %u is bigger than scratch region:%u\n", scratch_size);
+ dprintf(CRITICAL, "Erase Fail: Erase size: %u is bigger than scratch region\n", scratch_size);
return 1;
}
@@ -372,7 +373,7 @@
unaligned_blks = blk_count % erase_unit_sz;
blks_to_erase = blk_count - unaligned_blks;
- dprintf(SPEW, "Performing SDHCI erase: 0x%x:0x%x\n", blk_addr, blks_to_erase);
+ dprintf(SPEW, "Performing SDHCI erase: 0x%x:0x%x\n", blk_addr,(unsigned int)blks_to_erase);
if (mmc_sdhci_erase((struct mmc_device *)dev, blk_addr, blks_to_erase * block_size))
{
dprintf(CRITICAL, "MMC erase failed\n");
diff --git a/platform/msm_shared/partition_parser.c b/platform/msm_shared/partition_parser.c
index d40fb8a..38b2a80 100644
--- a/platform/msm_shared/partition_parser.c
+++ b/platform/msm_shared/partition_parser.c
@@ -605,12 +605,12 @@
array_size, (long long)(card_size_sec - 34));
/* Updating CRC of the Partition entry array in both headers */
- partition_entry_array_start = primary_gpt_header + block_size;
- crc_value = calculate_crc32(partition_entry_array_start,
+ partition_entry_array_start = (unsigned int)primary_gpt_header + block_size;
+ crc_value = calculate_crc32((unsigned char *)partition_entry_array_start,
max_part_count * part_entry_size);
PUT_LONG(primary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
- crc_value = calculate_crc32(partition_entry_array_start + array_size,
+ crc_value = calculate_crc32((unsigned char *)partition_entry_array_start + array_size,
max_part_count * part_entry_size);
PUT_LONG(secondary_gpt_header + PARTITION_CRC_OFFSET, crc_value);
@@ -715,7 +715,7 @@
}
/* Writing the partition entries array for the primary header */
- partition_entry_array_start = primary_gpt_header + block_size;
+ partition_entry_array_start = (unsigned int)primary_gpt_header + block_size;
ret = write_gpt_partition_array(primary_gpt_header,
partition_entry_array_start,
partition_entry_array_size, block_size);
@@ -726,7 +726,7 @@
}
/*Writing the partition entries array for the backup header */
- partition_entry_array_start = primary_gpt_header + block_size +
+ partition_entry_array_start = (unsigned int)primary_gpt_header + block_size +
partition_entry_array_size;
ret = write_gpt_partition_array(secondary_gpt_header,
partition_entry_array_start,
diff --git a/platform/msm_shared/qpic_nand.c b/platform/msm_shared/qpic_nand.c
index b972cce..efe4188 100644
--- a/platform/msm_shared/qpic_nand.c
+++ b/platform/msm_shared/qpic_nand.c
@@ -903,10 +903,9 @@
struct cmd_element *cmd_list_read_ptr = ce_read_array;
struct cmd_element *cmd_list_ptr_start = ce_array;
struct cmd_element *cmd_list_read_ptr_start = ce_read_array;
- uint32_t status;
+ uint32_t status, nand_ret;
int num_desc = 0;
uint32_t blk_addr = page / flash.num_pages_per_blk;
- int nand_ret;
/* Erase only if the block is not bad */
if (qpic_nand_block_isbad(page))
@@ -1277,7 +1276,6 @@
qpic_nand_init(struct qpic_nand_init_config *config)
{
uint32_t i;
- int nand_ret;
nand_base = config->nand_base;
@@ -1383,7 +1381,6 @@
uint8_t flags = 0;
uint32_t *cmd_list_temp = NULL;
- uint32_t temp_status = 0;
/* UD bytes in last CW is 512 - cws_per_page *4.
* Since each of the CW read earlier reads 4 spare bytes.
*/
@@ -1498,7 +1495,7 @@
bam_add_cmd_element(cmd_list_ptr, NAND_FLASH_STATUS, (uint32_t)PA((addr_t)&(flash_sts[i])), CE_READ_TYPE);
- cmd_list_temp = cmd_list_ptr;
+ cmd_list_temp = (uint32_t *)cmd_list_ptr;
cmd_list_ptr++;
diff --git a/platform/msm_shared/scm.c b/platform/msm_shared/scm.c
index c7ff1b8..6dc8a00 100644
--- a/platform/msm_shared/scm.c
+++ b/platform/msm_shared/scm.c
@@ -32,6 +32,8 @@
#include <asm.h>
#include <bits.h>
#include <arch/ops.h>
+#include <rand.h>
+#include <image_verify.h>
#include "scm.h"
#pragma GCC optimize ("O0")
@@ -170,7 +172,7 @@
{
uint32_t context_id;
register uint32_t r0 __asm__("r0") = SCM_ATOMIC(svc, cmd, 1);
- register uint32_t r1 __asm__("r1") = &context_id;
+ register uint32_t r1 __asm__("r1") = (uint32_t)&context_id;
register uint32_t r2 __asm__("r2") = arg1;
__asm__ volatile(
@@ -199,7 +201,7 @@
{
int context_id;
register uint32_t r0 __asm__("r0") = SCM_ATOMIC(svc, cmd, 2);
- register uint32_t r1 __asm__("r1") = &context_id;
+ register uint32_t r1 __asm__("r1") = (uint32_t)&context_id;
register uint32_t r2 __asm__("r2") = arg1;
register uint32_t r3 __asm__("r3") = arg2;
@@ -906,7 +908,7 @@
void * get_canary()
{
void * canary;
- if(scm_random(&canary, sizeof(canary))) {
+ if(scm_random((uint32_t *)&canary, sizeof(canary))) {
dprintf(CRITICAL,"scm_call for random failed !!!");
/*
* fall back to use lib rand API if scm call failed.
diff --git a/platform/msm_shared/sdhci_msm.c b/platform/msm_shared/sdhci_msm.c
index d721110..ba63845 100644
--- a/platform/msm_shared/sdhci_msm.c
+++ b/platform/msm_shared/sdhci_msm.c
@@ -191,7 +191,7 @@
/*
* Register the interrupt handler for pwr irq
*/
- register_int_handler(config->pwr_irq, sdhci_int_handler, (void *)config);
+ register_int_handler(config->pwr_irq, (int_handler)sdhci_int_handler, (void *)config);
unmask_interrupt(config->pwr_irq);
@@ -418,7 +418,7 @@
uint32_t total_phases)
{
int sub_phases[MAX_PHASES][MAX_PHASES]={{0}};
- int phases_per_row[MAX_PHASES] = {0};
+ uint32_t phases_per_row[MAX_PHASES] = {0};
uint32_t i,j;
int selected_phase = 0;
uint32_t row_index = 0;
@@ -660,14 +660,14 @@
{
uint32_t *tuning_block;
uint32_t *tuning_data;
- uint32_t tuned_phases[MAX_PHASES] = {{0}};
+ uint32_t tuned_phases[MAX_PHASES] = {0};
uint32_t size;
uint32_t phase = 0;
uint32_t tuned_phase_cnt = 0;
uint8_t drv_type = 0;
bool drv_type_changed = false;
int ret = 0;
- int i;
+ uint32_t i;
struct sdhci_msm_data *msm_host;
msm_host = host->msm_host;
@@ -686,12 +686,12 @@
if (bus_width == DATA_BUS_WIDTH_8BIT)
{
- tuning_block = tuning_block_128;
+ tuning_block = (uint32_t *)tuning_block_128;
size = sizeof(tuning_block_128);
}
else
{
- tuning_block = tuning_block_64;
+ tuning_block = (uint32_t *)tuning_block_64;
size = sizeof(tuning_block_64);
}
diff --git a/platform/msm_shared/shutdown_detect.c b/platform/msm_shared/shutdown_detect.c
index a51c9ae..633dbac 100644
--- a/platform/msm_shared/shutdown_detect.c
+++ b/platform/msm_shared/shutdown_detect.c
@@ -34,6 +34,8 @@
#include <kernel/timer.h>
#include <platform/timer.h>
#include <shutdown_detect.h>
+#include <platform.h>
+#include <target.h>
/* sleep clock is 32.768 khz, 0x8000 count per second */
#define MPM_SLEEP_TIMETICK_COUNT 0x8000
@@ -102,7 +104,7 @@
* for software to be safely detect if there is a key release action.
*/
timer_set_oneshot(p_timer, PWRKEY_DETECT_FREQUENCY,
- long_press_pwrkey_timer_func, NULL);
+ (timer_callback)long_press_pwrkey_timer_func, NULL);
} else {
shutdown_device();
}
@@ -146,7 +148,7 @@
*/
if (is_pwrkey_pon_reason() && is_pwrkey_time_expired()) {
timer_initialize(&pon_timer);
- timer_set_oneshot(&pon_timer, 0, long_press_pwrkey_timer_func, NULL);
+ timer_set_oneshot(&pon_timer, 0,(timer_callback)long_press_pwrkey_timer_func, NULL);
/*
* Wait until long press power key timeout
diff --git a/platform/msm_shared/smem.c b/platform/msm_shared/smem.c
index 25628d3..0dc3c24 100644
--- a/platform/msm_shared/smem.c
+++ b/platform/msm_shared/smem.c
@@ -104,7 +104,7 @@
uint32_t smem_addr = 0;
uint32_t base_ext = 0;
uint32_t offset = 0;
- void *ret = 0;
+ void *ret = NULL;
#if DYNAMIC_SMEM
smem_addr = smem_get_base_addr();
@@ -114,11 +114,11 @@
smem = (struct smem *)smem_addr;
if (type < SMEM_FIRST_VALID_TYPE || type > SMEM_LAST_VALID_TYPE)
- return 1;
+ return ret;
ainfo = &smem->alloc_info[type];
if (readl(&ainfo->allocated) == 0)
- return 1;
+ return ret;
*size = readl(&ainfo->size);
base_ext = readl(&ainfo->base_ext);
@@ -126,7 +126,7 @@
if(base_ext)
{
- ret = base_ext + offset;
+ ret = (void*)base_ext + offset;
}
else
{
diff --git a/platform/msm_shared/smem.h b/platform/msm_shared/smem.h
index b9cb855..9c9cf61 100644
--- a/platform/msm_shared/smem.h
+++ b/platform/msm_shared/smem.h
@@ -32,6 +32,7 @@
#define __PLATFORM_MSM_SHARED_SMEM_H
#include <sys/types.h>
+#include <platform.h>
#define SMEM_V7_SMEM_MAX_PMIC_DEVICES 1
#define SMEM_V8_SMEM_MAX_PMIC_DEVICES 3
diff --git a/platform/msm_shared/smem_ptable.c b/platform/msm_shared/smem_ptable.c
index 6ec563a..fd27e10 100644
--- a/platform/msm_shared/smem_ptable.c
+++ b/platform/msm_shared/smem_ptable.c
@@ -61,7 +61,7 @@
{
unsigned i;
unsigned ret;
- unsigned len;
+ unsigned len = 0;
/* Read only the header portion of ptable */
ret = smem_read_alloc_entry_offset(SMEM_AARM_PARTITION_TABLE,
@@ -220,7 +220,7 @@
uint32_t i;
uint32_t ret;
uint32_t version;
- uint32_t smem_ram_ptable_size;
+ uint32_t smem_ram_ptable_size = 0;
struct smem_ram_ptable_hdr *ram_ptable_hdr;
/* Check smem ram partition table version and decide on length of ram_ptable */
diff --git a/platform/msm_shared/spmi.c b/platform/msm_shared/spmi.c
index 6d486b7..d82fbb9 100644
--- a/platform/msm_shared/spmi.c
+++ b/platform/msm_shared/spmi.c
@@ -33,6 +33,7 @@
#include <platform/iomap.h>
#include <platform/irqs.h>
#include <platform/interrupts.h>
+#include <malloc.h>
#define PMIC_ARB_V2 0x20010000
#define CHNL_IDX(sid, pid) ((sid << 8) | pid)
@@ -47,8 +48,8 @@
static void spmi_lookup_chnl_number()
{
int i;
- uint8_t slave_id;
- uint8_t ppid_address;
+ uint8_t slave_id = 0;
+ uint8_t ppid_address = 0;
/* We need a max of sid (4 bits) + pid (8bits) of uint8_t's */
uint32_t chnl_tbl_sz = BIT(12) * sizeof(uint8_t);
@@ -95,7 +96,6 @@
{
uint32_t shift_value[] = {0, 8, 16, 24};
int i;
- int j;
uint32_t val = 0;
/* Write to WDATA */
@@ -154,12 +154,12 @@
*/
/* Write first 4 bytes to WDATA0 */
- write_wdata_from_array(param->buffer, 0, param->size, &bytes_written);
+ write_wdata_from_array(param->buffer, 0, param->size,(uint8_t *)&bytes_written);
if (bytes_written < param->size)
{
/* Write next 4 bytes to WDATA1 */
- write_wdata_from_array(param->buffer, 1, param->size, &bytes_written);
+ write_wdata_from_array(param->buffer, 1, param->size, (uint8_t *)&bytes_written);
}
/* Fill in the byte count for the command
@@ -241,7 +241,6 @@
{
uint32_t val = 0;
uint32_t error;
- uint32_t addr;
uint8_t bytes_read = 0;
/* Look up for pmic channel only for V2 hardware
@@ -382,7 +381,7 @@
{
pmic_irq_perph_id = periph_id;
- register_int_handler(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ , spmi_irq, 0);
+ register_int_handler(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ ,(int_handler)spmi_irq, 0);
unmask_interrupt(EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ);
}
diff --git a/platform/msm_shared/uart_dm.c b/platform/msm_shared/uart_dm.c
index 0a2eca0..2d74aa6 100644
--- a/platform/msm_shared/uart_dm.c
+++ b/platform/msm_shared/uart_dm.c
@@ -119,11 +119,11 @@
*/
static unsigned int
msm_boot_uart_calculate_num_chars_to_write(char *data_in,
- uint32_t *num_of_chars)
+ uint32_t *num_of_chars)
{
- int i = 0, j = 0;
+ uint32_t i = 0, j = 0;
- if ((data_in == NULL) || (*num_of_chars < 0)) {
+ if ((data_in == NULL)) {
return MSM_BOOT_UART_DM_E_INVAL;
}
@@ -357,7 +357,7 @@
for (i = 0; i < (int)tx_word_count; i++) {
tx_char = (tx_char_left < 4) ? tx_char_left : 4;
- num_chars_written = pack_chars_into_words(tx_data, tx_char, &tx_word);
+ num_chars_written = pack_chars_into_words((uint8_t *)tx_data, tx_char, &tx_word);
/* Wait till TX FIFO has space */
while (!(readl(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXRDY)) {
diff --git a/target/msm8909/init.c b/target/msm8909/init.c
index 32e4813..56c25c2 100644
--- a/target/msm8909/init.c
+++ b/target/msm8909/init.c
@@ -480,6 +480,10 @@
board->baseband = BASEBAND_MDM;
break;
+ case APQ8009:
+ board->baseband = BASEBAND_APQ;
+ break;
+
default:
dprintf(CRITICAL, "Platform type: %u is not supported\n", platform);
ASSERT(0);
diff --git a/target/msm8909/oem_panel.c b/target/msm8909/oem_panel.c
index 014a012..440f08c 100644
--- a/target/msm8909/oem_panel.c
+++ b/target/msm8909/oem_panel.c
@@ -41,6 +41,7 @@
#include "include/panel_hx8379a_fwvga_skua_video.h"
#include "include/panel_sharp_qhd_video.h"
#include "include/panel_ili9806e_fwvga_video.h"
+#include "include/panel_hx8379c_fwvga_video.h"
#define DISPLAY_MAX_PANEL_DETECTION 0
@@ -60,6 +61,7 @@
HX8379A_FWVGA_SKUA_VIDEO_PANEL,
SHARP_QHD_VIDEO_PANEL,
ILI9806E_FWVGA_VIDEO_PANEL,
+ HX8379C_FWVGA_VIDEO_PANEL,
UNKNOWN_PANEL
};
@@ -72,6 +74,7 @@
{"hx8379a_fwvga_skua_video", HX8379A_FWVGA_SKUA_VIDEO_PANEL},
{"sharp_qhd_video", SHARP_QHD_VIDEO_PANEL},
{"ili9806e_fwvga_video",ILI9806E_FWVGA_VIDEO_PANEL},
+ {"hx8379c_fwvga_video",HX8379C_FWVGA_VIDEO_PANEL},
};
static uint32_t panel_id;
@@ -204,6 +207,31 @@
ili9806e_fwvga_video_timings, TIMING_SIZE);
pinfo->mipi.signature = ILI9806E_FWVGA_VIDEO_SIGNATURE;
break;
+ case HX8379C_FWVGA_VIDEO_PANEL:
+ panelstruct->paneldata = &hx8379c_fwvga_video_panel_data;
+ panelstruct->panelres = &hx8379c_fwvga_video_panel_res;
+ panelstruct->color = &hx8379c_fwvga_video_color;
+ panelstruct->videopanel = &hx8379c_fwvga_video_video_panel;
+ panelstruct->commandpanel = &hx8379c_fwvga_video_command_panel;
+ panelstruct->state = &hx8379c_fwvga_video_state;
+ panelstruct->laneconfig = &hx8379c_fwvga_video_lane_config;
+ panelstruct->paneltiminginfo
+ = &hx8379c_fwvga_video_timing_info;
+ panelstruct->panelresetseq
+ = &hx8379c_fwvga_video_reset_seq;
+ panelstruct->backlightinfo = &hx8379c_fwvga_video_backlight;
+ pinfo->mipi.panel_on_cmds
+ = hx8379c_fwvga_video_on_command;
+ pinfo->mipi.num_of_panel_on_cmds
+ = HX8379C_FWVGA_VIDEO_ON_COMMAND;
+ pinfo->mipi.panel_off_cmds
+ = hx8379c_fwvga_video_off_command;
+ pinfo->mipi.num_of_panel_off_cmds
+ = HX8379C_FWVGA_VIDEO_OFF_COMMAND;
+ memcpy(phy_db->timing,
+ hx8379c_fwvga_video_timings, TIMING_SIZE);
+ pinfo->mipi.signature = HX8379C_FWVGA_VIDEO_SIGNATURE;
+ break;
case UNKNOWN_PANEL:
default:
memset(panelstruct, 0, sizeof(struct panel_struct));
@@ -264,6 +292,8 @@
panel_id = ILI9806E_FWVGA_VIDEO_PANEL;
break;
case QRD_SKUE:
+ panel_id = HX8379C_FWVGA_VIDEO_PANEL;
+ break;
default:
dprintf(CRITICAL, "QRD Display not enabled for %d type\n",
platform_subtype);
diff --git a/target/msm8994/include/target/display.h b/target/msm8994/include/target/display.h
index 35643a0..0bbc751 100644
--- a/target/msm8994/include/target/display.h
+++ b/target/msm8994/include/target/display.h
@@ -49,7 +49,7 @@
};
static const uint32_t panel_regulator_settings[] = {
- 0x03, 0x05, 0x03, 0x00, 0x20, 0x07, 0x01
+ 0x03, 0x02, 0x03, 0x00, 0x10, 0x07, 0x01
};
static const char panel_lane_config[] = {
diff --git a/target/msm8994/target_display.c b/target/msm8994/target_display.c
index 08c8b12..1ac0895 100644
--- a/target/msm8994/target_display.c
+++ b/target/msm8994/target_display.c
@@ -77,51 +77,20 @@
"pmi8994_gpios", 2, 3, 1, 0, 1
};
-static void dsi_pll_20nm_phy_init( uint32_t pll_base, int off)
-{
- mdss_dsi_pll_20nm_sw_reset_st_machine(pll_base);
-
- dmb();
-
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
- writel(0x80, pll_base + off + 0x0174);
-
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
- writel(0x00, pll_base + off + 0x0174);
- udelay(5000);
- /* Strength ctrl 0 */
- writel(0x77, pll_base + off + 0x0184);
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
- writel(0x7f, pll_base + off + 0x0170);
-
- /* DSI_0_PHY_DSIPHY_GLBL_TEST_CTRL */
- writel(0x00, pll_base + off + 0x01d4);
-
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_2 */
- writel(0x00, pll_base + off + 0x0178);
-}
-
static uint32_t dsi_pll_20nm_enable_seq(uint32_t pll_base)
{
uint32_t pll_locked;
-
- /*
- * PLL power up sequence.
- * Add necessary delays recommeded by hardware.
- */
- writel(0x01, pll_base + 0x9c); /* MMSS_DSI_PHY_PLL_PLLLOCK_CMP_EN */
- writel(0x07, pll_base + 0x14); /* MMSS_DSI_PHY_PLL_PLL_CNTRL */
- writel(0x00, pll_base + 0x2c); /* MMSS_DSI_PHY_PLL_PLL_BKG_KVCO_CAL_EN */
- udelay(500);
-
- dsi_pll_20nm_phy_init(pll_base, 0x200); /* Ctrl 0 */
+ /* MDSS_DSI_0_PHY_DSIPHY_CTRL_1 */
+ writel(0x00, pll_base + 0x374);
dmb();
-
- pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
- if (!pll_locked)
- dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
- else
- dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
+ /* MDSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+ writel(0x7f, pll_base + 0x370);
+ dmb();
+ pll_locked = mdss_dsi_pll_20nm_lock_status(pll_base);
+ if (!pll_locked)
+ dprintf(INFO, "%s: DSI PLL lock failed\n", __func__);
+ else
+ dprintf(INFO, "%s: DSI PLL lock Success\n", __func__);
return pll_locked;
}
@@ -286,7 +255,17 @@
{
uint32_t ret;
struct mdss_dsi_pll_config *pll_data;
- uint32_t dual_dsi = pinfo->mipi.dual_dsi;
+ uint32_t flags;
+
+ if (pinfo->dest == DISPLAY_2) {
+ flags = MMSS_DSI_CLKS_FLAG_DSI1;
+ if (pinfo->mipi.dual_dsi)
+ flags |= MMSS_DSI_CLKS_FLAG_DSI0;
+ } else {
+ flags = MMSS_DSI_CLKS_FLAG_DSI0;
+ if (pinfo->mipi.dual_dsi)
+ flags |= MMSS_DSI_CLKS_FLAG_DSI1;
+ }
pll_data = pinfo->mipi.dsi_pll_config;
if (enable) {
@@ -306,13 +285,13 @@
mdss_dsi_auto_pll_20nm_config(DSI0_PLL_BASE,
MIPI_DSI0_BASE, pll_data);
dsi_pll_20nm_enable_seq(DSI0_PLL_BASE);
- mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi,
+ mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, flags,
pll_data->pclk_m,
pll_data->pclk_n,
pll_data->pclk_d);
} else if(!target_cont_splash_screen()) {
/* Disable clocks if continuous splash off */
- mmss_dsi_clock_disable(dual_dsi);
+ mmss_dsi_clock_disable(flags);
mdp_clock_disable();
mmss_bus_clock_disable();
mdp_gdsc_ctrl(enable);