diff --git a/include/target.h b/include/target.h
index c973a61..bb3a6f7 100644
--- a/include/target.h
+++ b/include/target.h
@@ -53,6 +53,10 @@
 bool target_display_panel_node(char *pbuf, uint16_t buf_size);
 uint32_t target_get_boot_device();
 
+const char * target_usb_controller();
+void target_usb_phy_reset(void);
+void target_usb_phy_mux_configure(void);
+
 /* Boot device */
 enum boot_device
 {
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 8c3f841..b785aa1 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -206,3 +206,36 @@
 	clock_ce_enable(instance);
 
 }
+
+void clock_usb30_gdsc_enable(void)
+{
+	uint32_t reg = readl(GCC_USB30_GDSCR);
+
+	reg &= ~(0x1);
+
+	writel(reg, GCC_USB30_GDSCR);
+}
+
+/* enables usb30 interface and master clocks */
+void clock_usb30_init(void)
+{
+	int ret;
+
+	/* interface clock */
+	ret = clk_get_set_enable("usb30_iface_clk", 0, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb30_iface_clk. ret = %d\n", ret);
+		ASSERT(0);
+	}
+
+	clock_usb30_gdsc_enable();
+
+	/* master clock */
+	ret = clk_get_set_enable("usb30_master_clk", 125000000, 1);
+	if(ret)
+	{
+		dprintf(CRITICAL, "failed to set usb30_master_clk. ret = %d\n", ret);
+		ASSERT(0);
+	}
+}
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index c939bad..a353a15 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -281,6 +281,54 @@
 	},
 };
 
+/* USB 3.0 Clocks */
+static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] =
+{
+	F(125000000, gpll0, 1, 5, 24),
+	F_END
+};
+
+static struct rcg_clk usb30_master_clk_src =
+{
+	.cmd_reg      = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR,
+	.m_reg        = (uint32_t *) GCC_USB30_MASTER_M,
+	.n_reg        = (uint32_t *) GCC_USB30_MASTER_N,
+	.d_reg        = (uint32_t *) GCC_USB30_MASTER_D,
+
+	.set_rate     = clock_lib2_rcg_set_rate_mnd,
+	.freq_tbl     = ftbl_gcc_usb30_master_clk,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "usb30_master_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+
+static struct branch_clk gcc_usb30_master_clk =
+{
+	.cbcr_reg     = (uint32_t *) GCC_USB30_MASTER_CBCR,
+	.parent       = &usb30_master_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_usb30_master_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
+static struct branch_clk gcc_sys_noc_usb30_axi_clk =
+{
+	.cbcr_reg     = (uint32_t *) SYS_NOC_USB3_AXI_CBCR,
+	.has_sibling  = 1,
+
+	.c = {
+		.dbg_name = "gcc_sys_noc_usb3_axi_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 /* Clock lookup table */
 static struct clk_lookup msm_clocks_8084[] =
 {
@@ -292,6 +340,10 @@
 
 	CLK_LOOKUP("usb_iface_clk",  gcc_usb_hs_ahb_clk.c),
 	CLK_LOOKUP("usb_core_clk",   gcc_usb_hs_system_clk.c),
+
+	/* USB 3.0 */
+	CLK_LOOKUP("usb30_iface_clk",  gcc_sys_noc_usb30_axi_clk.c),
+	CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c),
 };
 
 void platform_clock_init(void)
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
index bf63755..b620dd0 100644
--- a/platform/apq8084/include/platform/clock.h
+++ b/platform/apq8084/include/platform/clock.h
@@ -45,5 +45,6 @@
 void mdp_clock_init(void);
 void clock_ce_enable(uint8_t instance);
 void clock_ce_disable(uint8_t instance);
+void clock_usb30_init(void);
 
 #endif
diff --git a/platform/apq8084/include/platform/iomap.h b/platform/apq8084/include/platform/iomap.h
index d1ca7a9..7f47659 100644
--- a/platform/apq8084/include/platform/iomap.h
+++ b/platform/apq8084/include/platform/iomap.h
@@ -108,13 +108,36 @@
 #define SDCC1_D                     (CLK_CTL_BASE + 0x4E0) /* d */
 #define SDCC1_CDCCAL_SLEEP_CBCR     (CLK_CTL_BASE + 0x4E4)
 
+/* USB 3.0 clocks */
+#define SYS_NOC_USB3_AXI_CBCR       (CLK_CTL_BASE + 0x0108)
+
+#define GCC_USB_30_BCR              (CLK_CTL_BASE + 0x03C0)
+#define GCC_USB_30_MISC             (CLK_CTL_BASE + 0x03C4)
+
+#define GCC_USB30_MASTER_CBCR       (CLK_CTL_BASE + 0x03C8)
+#define GCC_USB30_SLEEP_CBCR        (CLK_CTL_BASE + 0x03CC)
+#define GCC_USB30_MOCK_UTMI_CBCR    (CLK_CTL_BASE + 0x03D0)
+
+#define GCC_USB30_MASTER_CMD_RCGR   (CLK_CTL_BASE + 0x03D4)
+#define GCC_USB30_MASTER_CFG_RCGR   (CLK_CTL_BASE + 0x03D8)
+#define GCC_USB30_MASTER_M          (CLK_CTL_BASE + 0x03DC)
+#define GCC_USB30_MASTER_N          (CLK_CTL_BASE + 0x03E0)
+#define GCC_USB30_MASTER_D          (CLK_CTL_BASE + 0x03E4)
+
+#define GCC_USB3_PHY_BCR            (CLK_CTL_BASE + 0x03FC)
+#define GCC_USB30_GDSCR             (CLK_CTL_BASE + 0x1E84)
+
+/* USB30 base */
+#define MSM_USB30_BASE               0xF9200000
+#define MSM_USB30_QSCRATCH_BASE      0xF92F8800
+
+
 /* Addresses below this point needs to be verified.
  * Included only for compilation purposes.
  */
 #define MSM_USB_BASE                (PERIPH_SS_BASE + 0x00255000)
 
 #define CLK_CTL_BASE                0xFC400000
-
 #define GCC_WDOG_DEBUG              (CLK_CTL_BASE +  0x00001780)
 
 #define USB_HS_BCR                  (CLK_CTL_BASE + 0x480)
@@ -128,6 +151,7 @@
 #define MSM_CE2_BAM_BASE            0xFD444000
 #define MSM_CE2_BASE                0xFD45A000
 #define USB2_PHY_SEL                0xFD4AB000
+#define COPSS_USB_CONTROL_WITH_JDR  0xFD4AB204
 
 #define TLMM_BASE_ADDR              0xFD510000
 #define GPIO_CONFIG_ADDR(x)         (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
diff --git a/platform/apq8084/include/platform/irqs.h b/platform/apq8084/include/platform/irqs.h
index 33e1a12..5a614d3 100644
--- a/platform/apq8084/include/platform/irqs.h
+++ b/platform/apq8084/include/platform/irqs.h
@@ -47,6 +47,7 @@
 
 #define UFS_IRQ                                (GIC_SPI_START + 28)
 
+#define USB30_EE1_IRQ                          (GIC_SPI_START + 131)
 #define USB1_HS_BAM_IRQ                        (GIC_SPI_START + 135)
 #define USB1_HS_IRQ                            (GIC_SPI_START + 134)
 #define USB2_IRQ                               (GIC_SPI_START + 141)
diff --git a/platform/fsm9900/platform.c b/platform/fsm9900/platform.c
index 7a1791e..c30f60b 100644
--- a/platform/fsm9900/platform.c
+++ b/platform/fsm9900/platform.c
@@ -62,8 +62,6 @@
 	{SYSTEM_IMEM_BASE, SYSTEM_IMEM_BASE, 1,              IMEM_MEMORY},
 };
 
-static struct smem_ram_ptable ram_ptable;
-
 /* Boot timestamps */
 #define BS_INFO_OFFSET     (0x6B0)
 #define BS_INFO_ADDR_V1    (RPM_MSG_RAM_BASE     + BS_INFO_OFFSET)
@@ -127,40 +125,47 @@
 {
 	uint32_t i;
 	uint32_t sections;
+	ram_partition ptn_entry;
 	uint32_t table_size = ARRAY_SIZE(mmu_section_table);
+	uint32_t len = 0;
 
-	ASSERT(smem_ram_ptable_init(&ram_ptable));
+	ASSERT(smem_ram_ptable_init_v1());
+
+	len = smem_get_ram_ptable_len();
 
 	/* Configure the MMU page entries for SDRAM and IMEM memory read
-	   from the smem ram table*/
-	for(i = 0; i < ram_ptable.len; i++)
+	   from the smem ram table */
+	for (i = 0; i < len; i++)
 	{
-		if(ram_ptable.parts[i].type == SYS_MEMORY)
+		smem_get_ram_ptable_entry(&ptn_entry, i);
+		if ((ptn_entry.type == SYS_MEMORY) &&
+		    ((ptn_entry.category == SDRAM) ||
+		     (ptn_entry.category == IMEM)))
 		{
-			if((ram_ptable.parts[i].category == SDRAM) ||
-			   (ram_ptable.parts[i].category == IMEM))
-			{
-				/* Check to ensure that start address is 1MB aligned */
-				ASSERT((ram_ptable.parts[i].start & 0xFFFFF) == 0);
+			/* Check to ensure that start address is 1MB aligned */
+			ASSERT((ptn_entry.start & (MB-1)) == 0);
 
-				sections = (ram_ptable.parts[i].size) / MB;
-				while(sections--) {
-					arm_mmu_map_section(ram_ptable.parts[i].start +
-								sections * MB,
-								ram_ptable.parts[i].start +
-								sections * MB,
-								(MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH | \
-								MMU_MEMORY_AP_READ_WRITE | MMU_MEMORY_XN));
-				}
+			sections = ptn_entry.size / MB;
+			while(sections--)
+			{
+				arm_mmu_map_section(
+					(ptn_entry.start + sections * MB),
+					(ptn_entry.start + sections * MB),
+					(MMU_MEMORY_TYPE_NORMAL_WRITE_THROUGH |
+					 MMU_MEMORY_AP_READ_WRITE |
+					 MMU_MEMORY_XN));
 			}
 		}
 	}
+
 	/* Configure the MMU page entries for memory read from the
 	   mmu_section_table */
-	for (i = 0; i < table_size; i++) {
+	for (i = 0; i < table_size; i++)
+	{
 		sections = mmu_section_table[i].num_of_sections;
 
-		while (sections--) {
+		while (sections--)
+		{
 			arm_mmu_map_section(mmu_section_table[i].paddress +
 					    sections * MB,
 					    mmu_section_table[i].vaddress +
diff --git a/platform/msm8974/platform.c b/platform/msm8974/platform.c
index 9ff92c3..5a7e1d4 100644
--- a/platform/msm8974/platform.c
+++ b/platform/msm8974/platform.c
@@ -128,6 +128,39 @@
 	return ret;
 }
 
+/* Check for 8974 PRO chip */
+int platform_is_8974Pro()
+{
+	uint32_t platform = board_platform_id();
+	int ret = 0;
+
+	switch(platform)
+	{
+		case APQ8074AA:
+		case APQ8074AB:
+		case APQ8074AC:
+
+		case MSM8274AA:
+		case MSM8274AB:
+		case MSM8274AC:
+
+		case MSM8674AA:
+		case MSM8674AB:
+		case MSM8674AC:
+
+		case MSM8974AA:
+		case MSM8974AB:
+		case MSM8974AC:
+
+			ret = 1;
+			break;
+		default:
+			ret = 0;
+	};
+
+	return ret;
+}
+
 addr_t get_bs_info_addr()
 {
 	uint32_t soc_ver = board_soc_version();
diff --git a/platform/msm_shared/usb30_dwc_hw.c b/platform/msm_shared/usb30_dwc_hw.c
index fd18f1a..86a10a9 100644
--- a/platform/msm_shared/usb30_dwc_hw.c
+++ b/platform/msm_shared/usb30_dwc_hw.c
@@ -39,6 +39,8 @@
 #include <usb30_dwc_hwio.h>
 #include <usb30_dwc.h>
 #include <usb30_dwc_hw.h>
+#include <smem.h>
+#include <board.h>
 
 extern char* ss_link_state_lookup[20];
 extern char* hs_link_state_lookup[20];
@@ -59,6 +61,11 @@
 
 #define ERR(...) dprintf(ALWAYS, __VA_ARGS__)
 
+__WEAK int platform_is_8974()
+{
+	return 0;
+}
+
 /* This file provides interface to interact with DWC hardware. This code
  * does not maintain any soft states. It programs the h/w as requested by the
  * APIs.
@@ -532,7 +539,11 @@
 void dwc_ss_phy_workaround_12(dwc_dev_t *dev)
 {
 	/* 12. */
-	REG_WRITEI(dev, GUSB3PIPECTL, 0, 0x30C0003);
+	if ( platform_is_8974() &&
+		 (board_soc_version() < BOARD_SOC_VERSION2))
+	{
+		REG_WRITEI(dev, GUSB3PIPECTL, 0, 0x30C0003);
+	}
 }
 
 /*  AXI master config */
@@ -540,11 +551,16 @@
 {
 	uint32_t reg = 0;
 
-	reg = (DWC_GSBUSCFG0_INCR4BRSTENA_BMSK |
-		   DWC_GSBUSCFG0_INCR8BRSTENA_BMSK |
-		   DWC_GSBUSCFG0_INCR16BRSTENA_BMSK);
+	/* 17. */
+	if ( platform_is_8974() &&
+		 (board_soc_version() < BOARD_SOC_VERSION2))
+	{
+		reg = (DWC_GSBUSCFG0_INCR4BRSTENA_BMSK |
+			   DWC_GSBUSCFG0_INCR8BRSTENA_BMSK |
+			   DWC_GSBUSCFG0_INCR16BRSTENA_BMSK);
 
-	REG_WRITE(dev, GSBUSCFG0, reg);
+		REG_WRITE(dev, GSBUSCFG0, reg);
+	}
 }
 
 /* read the controller id and version information */
diff --git a/platform/msm_shared/usb30_udc.c b/platform/msm_shared/usb30_udc.c
index 01c3d1d..ec95b93 100644
--- a/platform/msm_shared/usb30_udc.c
+++ b/platform/msm_shared/usb30_udc.c
@@ -43,6 +43,9 @@
 #include <usb30_dwc.h>
 #include <usb30_wrapper.h>
 #include <usb30_udc.h>
+#include <smem.h>
+#include <board.h>
+#include <platform/timer.h>
 
 //#define DEBUG_USB
 
@@ -100,24 +103,64 @@
 static udc_t *udc_dev = NULL;
 
 
-/* TODO: need to find right place for the tcsr functions. */
-
-/* UTMI MUX configuration to connect PHY to SNPS controller:
- * Configure primary HS phy mux to use UTMI interface
- * (connected to usb30 controller).
- */
-void tcsr_hs_phy_mux_configure(void)
+__WEAK int platform_is_8974()
 {
-	uint32_t reg;
-
-	reg = readl(USB2_PHY_SEL);
-
-	writel(reg | 0x1, USB2_PHY_SEL);
+	return 0;
 }
 
-void tcsr_hs_phy_mux_de_configure(void)
+__WEAK int platform_is_8974Pro()
 {
-	writel(0x0, USB2_PHY_SEL);
+	return 0;
+}
+
+static void phy_mux_configure(void)
+{
+	/* configuring of hs phy mux is different for some platforms. */
+	target_usb_phy_mux_configure();
+}
+
+static void phy_reset(usb_wrapper_dev_t *wrapper)
+{
+	/* phy reset is different for some platforms. */
+	if (platform_is_8974() || platform_is_8974Pro())
+	{
+		/* SS PHY */
+		usb_wrapper_ss_phy_reset(wrapper);
+
+		/* For 8974: hs phy is reset as part of soft reset.
+		 * No need for explicit reset.
+		 */
+	}
+	else if (board_platform_id() == APQ8084)
+	{
+		target_usb_phy_reset();
+	}
+}
+
+/* Initialize HS phy */
+void hs_phy_init(udc_t *dev)
+{
+	/* only for 8974 */
+	if (platform_is_8974() || platform_is_8974Pro())
+	{
+		/* 5.a, 5.b */
+		usb_wrapper_hs_phy_init(dev->wrapper_dev);
+
+		/* 5.d */
+		dwc_usb2_phy_soft_reset(dev->dwc);
+	}
+}
+
+/* vbus override */
+void vbus_override(udc_t *dev)
+{
+	/* when vbus signal is not available directly to the controller,
+	 * simulate vbus presense.
+	 */
+	if (board_platform_id() == APQ8084)
+	{
+		usb_wrapper_vbus_override(dev->wrapper_dev);
+	}
 }
 
 
@@ -175,17 +218,15 @@
 	/* section 4.4.2: Initialization and configuration sequences */
 
 	/* 1. UTMI Mux configuration */
-	tcsr_hs_phy_mux_configure();
+	phy_mux_configure();
 
 	/* 2. Put controller in reset */
 	dwc_reset(dwc, 1);
 
-	/* PHY reset (steps 3 - 7) must be done while dwc is in reset condition */
+	/* Steps 3 - 7 must be done while dwc is in reset condition */
 
-	/* 3. Reset SS PHY */
-	usb_wrapper_ss_phy_reset(wrapper);
-
-	/* HS PHY is reset as part of soft reset. No need for explicit reset. */
+	/* 3. Reset PHY */
+	phy_reset(wrapper);
 
 	/* 4. SS phy config */
 	usb_wrapper_ss_phy_configure(wrapper);
@@ -193,9 +234,6 @@
 	/* 5. HS phy init */
 	usb_wrapper_hs_phy_init(wrapper);
 
-	/* 5.d */
-	dwc_usb2_phy_soft_reset(dwc);
-
 	/* 6. hs phy config */
 	usb_wrapper_hs_phy_configure(wrapper);
 
@@ -222,6 +260,11 @@
 
 	/* 14. needed only for host mode. ignored. */
 
+	/* If the target does not support vbus detection in controller,
+	 * simulate vbus presence.
+	 */
+	vbus_override(udc_dev);
+
 	/* 15 - 20 */
 	dwc_device_init(dwc);
 }
diff --git a/platform/msm_shared/usb30_wrapper.c b/platform/msm_shared/usb30_wrapper.c
index f0f271b..4075a02 100644
--- a/platform/msm_shared/usb30_wrapper.c
+++ b/platform/msm_shared/usb30_wrapper.c
@@ -128,7 +128,6 @@
 	if ( (board_platform_id() == MSM8974) &&
 		 (board_soc_version() < BOARD_SOC_VERSION2))
 	{
-		/* TODO: confirm if V1 in HPG only applies to 8974 */
 		REG_WRITE(dev, GENERAL_CFG, 0x78);
 	}
 }
@@ -152,6 +151,23 @@
 	REG_WRITE_FIELD(dev, SS_PHY_PARAM_CTRL_1, LOS_BIAS, 0x5);
 }
 
+void usb_wrapper_vbus_override(usb_wrapper_dev_t *dev)
+{
+	/* set extenal vbus valid select */
+	REG_WRITE_FIELD(dev, HS_PHY_CTRL_COMMON, VBUSVLDEXTSEL0, 0x1);
+
+	/* enable D+ pullup */
+	REG_WRITE_FIELD(dev, HS_PHY_CTRL, VBUSVLDEXT0, 0x1);
+
+	/* set otg vbus valid from hs phy to controller */
+	REG_WRITE_FIELD(dev, HS_PHY_CTRL, UTMI_OTG_VBUS_VALID, 0x1);
+
+	/* Indicate value is driven by UTMI_OTG_VBUS_VALID bit */
+	REG_WRITE_FIELD(dev, HS_PHY_CTRL, SW_SESSVLD_SEL, 0x1);
+
+	/* Indicate power present to SS phy */
+	REG_WRITE_FIELD(dev, SS_PHY_CTRL, LANE0_PWR_PRESENT, 0x1);
+}
 
 /* API to read SS PHY registers */
 uint16_t usb_wrapper_ss_phy_read(usb_wrapper_dev_t *dev, uint16_t addr)
diff --git a/platform/msm_shared/usb30_wrapper.h b/platform/msm_shared/usb30_wrapper.h
index d274e51..a8904a0 100644
--- a/platform/msm_shared/usb30_wrapper.h
+++ b/platform/msm_shared/usb30_wrapper.h
@@ -59,6 +59,8 @@
 void usb_wrapper_hs_phy_init(usb_wrapper_dev_t *dev);
 void usb_wrapper_hs_phy_configure(usb_wrapper_dev_t *dev);
 
+void usb_wrapper_vbus_override(usb_wrapper_dev_t *dev);
+
 void usb_wrapper_workaround_10(usb_wrapper_dev_t *dev);
 void usb_wrapper_workaround_11(usb_wrapper_dev_t *dev);
 void usb_wrapper_workaround_13(usb_wrapper_dev_t *dev);
diff --git a/platform/msm_shared/usb30_wrapper_hwio.h b/platform/msm_shared/usb30_wrapper_hwio.h
index addfed8..1b5c9f7 100644
--- a/platform/msm_shared/usb30_wrapper_hwio.h
+++ b/platform/msm_shared/usb30_wrapper_hwio.h
@@ -139,6 +139,39 @@
 #define HWIO_RAM1_REG_RAM11_EN_BMSK                                              0x1
 #define HWIO_RAM1_REG_RAM11_EN_SHFT                                              0x0
 
+/* Note: HS_PHYCTRL_COMMON register is added only from 8084 and onwards. */
+#define HWIO_HS_PHY_CTRL_COMMON_ADDR(x)                                     ((x) + 0x000000ec)
+#define HWIO_HS_PHY_CTRL_COMMON_RMSK                                            0x7fff
+#define HWIO_HS_PHY_CTRL_COMMON_IN(x)      \
+        in_dword_masked(HWIO_HS_PHY_CTRL_COMMON_ADDR(x), HWIO_HS_PHY_CTRL_COMMON_RMSK)
+#define HWIO_HS_PHY_CTRL_COMMON_INM(x, m)      \
+        in_dword_masked(HWIO_HS_PHY_CTRL_COMMON_ADDR(x), m)
+#define HWIO_HS_PHY_CTRL_COMMON_OUT(x, v)      \
+        out_dword(HWIO_HS_PHY_CTRL_COMMON_ADDR(x),v)
+#define HWIO_HS_PHY_CTRL_COMMON_OUTM(x,m,v) \
+        out_dword_masked_ns(HWIO_HS_PHY_CTRL_COMMON_ADDR(x),m,v,HWIO_HS_PHY_CTRL_COMMON_IN(x))
+#define HWIO_HS_PHY_CTRL_COMMON_USE_CLKCORE_BMSK                                0x4000
+#define HWIO_HS_PHY_CTRL_COMMON_USE_CLKCORE_SHFT                                   0xe
+#define HWIO_HS_PHY_CTRL_COMMON_ACAENB0_BMSK                                    0x2000
+#define HWIO_HS_PHY_CTRL_COMMON_ACAENB0_SHFT                                       0xd
+#define HWIO_HS_PHY_CTRL_COMMON_VBUSVLDEXTSEL0_BMSK                             0x1000
+#define HWIO_HS_PHY_CTRL_COMMON_VBUSVLDEXTSEL0_SHFT                                0xc
+#define HWIO_HS_PHY_CTRL_COMMON_OTGDISABLE0_BMSK                                 0x800
+#define HWIO_HS_PHY_CTRL_COMMON_OTGDISABLE0_SHFT                                   0xb
+#define HWIO_HS_PHY_CTRL_COMMON_OTGTUNE0_BMSK                                    0x700
+#define HWIO_HS_PHY_CTRL_COMMON_OTGTUNE0_SHFT                                      0x8
+#define HWIO_HS_PHY_CTRL_COMMON_COMMONONN_BMSK                                    0x80
+#define HWIO_HS_PHY_CTRL_COMMON_COMMONONN_SHFT                                     0x7
+#define HWIO_HS_PHY_CTRL_COMMON_FSEL_BMSK                                         0x70
+#define HWIO_HS_PHY_CTRL_COMMON_FSEL_SHFT                                          0x4
+#define HWIO_HS_PHY_CTRL_COMMON_RETENABLEN_BMSK                                    0x8
+#define HWIO_HS_PHY_CTRL_COMMON_RETENABLEN_SHFT                                    0x3
+#define HWIO_HS_PHY_CTRL_COMMON_SIDDQ_BMSK                                         0x4
+#define HWIO_HS_PHY_CTRL_COMMON_SIDDQ_SHFT                                         0x2
+#define HWIO_HS_PHY_CTRL_COMMON_VATESTENB_BMSK                                     0x3
+#define HWIO_HS_PHY_CTRL_COMMON_VATESTENB_SHFT                                     0x0
+
+
 #define HWIO_HS_PHY_CTRL_ADDR(x)                                          ((x) + 0x00000010)
 #define HWIO_HS_PHY_CTRL_RMSK                                              0x7ffffff
 #define HWIO_HS_PHY_CTRL_POR                                              0x072203b2
@@ -150,6 +183,11 @@
         out_dword(HWIO_HS_PHY_CTRL_ADDR(x),v)
 #define HWIO_HS_PHY_CTRL_OUTM(x,m,v) \
         out_dword_masked_ns(HWIO_HS_PHY_CTRL_ADDR(x),m,v,HWIO_HS_PHY_CTRL_IN(x))
+
+/* Note: This field is introduced only in 8084 and onwards. */
+#define HWIO_HS_PHY_CTRL_SW_SESSVLD_SEL_BMSK                             0x10000000
+#define HWIO_HS_PHY_CTRL_SW_SESSVLD_SEL_SHFT                                   0x1c
+
 #define HWIO_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_BMSK                     0x4000000
 #define HWIO_HS_PHY_CTRL_CLAMP_MPM_DPSE_DMSE_EN_N_SHFT                          0x1a
 #define HWIO_HS_PHY_CTRL_FREECLK_SEL_BMSK                                  0x2000000
diff --git a/project/apq8084.mk b/project/apq8084.mk
index 4e67a84..dd582ce 100644
--- a/project/apq8084.mk
+++ b/project/apq8084.mk
@@ -10,6 +10,7 @@
 EMMC_BOOT := 1
 ENABLE_SDHCI_SUPPORT := 1
 ENABLE_UFS_SUPPORT   := 1
+ENABLE_USB30_SUPPORT := 1
 
 #DEFINES += WITH_DEBUG_DCC=1
 DEFINES += WITH_DEBUG_UART=1
@@ -30,3 +31,7 @@
 ifeq ($(ENABLE_UFS_SUPPORT),1)
 DEFINES += UFS_SUPPORT=1
 endif
+
+ifeq ($(ENABLE_USB30_SUPPORT),1)
+DEFINES += USB30_SUPPORT=1
+endif
diff --git a/target/apq8084/init.c b/target/apq8084/init.c
index dc552f1..dc9bdd6 100644
--- a/target/apq8084/init.c
+++ b/target/apq8084/init.c
@@ -459,3 +459,49 @@
 
 	dprintf(CRITICAL, "Rebooting failed\n");
 }
+
+/* identify the usb controller to be used for the target */
+const char * target_usb_controller()
+{
+	return "dwc";
+}
+
+/* mux hs phy to route to dwc controller */
+static void phy_mux_configure_with_jdr()
+{
+	uint32_t val;
+
+	val = readl(COPSS_USB_CONTROL_WITH_JDR);
+
+	/* Note: there are no details regarding this bit in hpg or swi. */
+	val |= BIT(8);
+
+	writel(val, COPSS_USB_CONTROL_WITH_JDR);
+}
+
+/* configure hs phy mux if using dwc controller */
+void target_usb_phy_mux_configure(void)
+{
+	if(!strcmp(target_usb_controller(), "dwc"))
+	{
+		phy_mux_configure_with_jdr();
+	}
+}
+
+void target_usb_phy_reset(void)
+{
+	uint32_t val;
+
+	/* SS PHY reset */
+	val = readl(GCC_USB3_PHY_BCR) | BIT(0);
+	writel(val, GCC_USB3_PHY_BCR);
+	udelay(10);
+	writel(val & ~BIT(0), GCC_USB3_PHY_BCR);
+
+	/* HS PHY reset */
+	/* Note: reg/bit details are not mentioned in hpg or swi. */
+	val = readl(COPSS_USB_CONTROL_WITH_JDR) | BIT(11);
+	writel(val, COPSS_USB_CONTROL_WITH_JDR);
+	udelay(10);
+	writel(val & ~BIT(11), COPSS_USB_CONTROL_WITH_JDR);
+}
diff --git a/target/fsm9900/meminfo.c b/target/fsm9900/meminfo.c
index 5f9c490..c6dd53e 100644
--- a/target/fsm9900/meminfo.c
+++ b/target/fsm9900/meminfo.c
@@ -43,38 +43,44 @@
  */
 uint32_t target_dev_tree_mem(void *fdt, uint32_t memory_node_offset)
 {
-    struct smem_ram_ptable ram_ptable;
-    unsigned int i;
+	ram_partition ptn_entry;
+	unsigned int index;
 	int ret = 0;
+	uint32_t len = 0;
 
 	/* Make sure RAM partition table is initialized */
-	ASSERT(smem_ram_ptable_init(&ram_ptable));
+	ASSERT(smem_ram_ptable_init_v1());
 
-     /* Calculating the size of the mem_info_ptr */
-    for (i = 0 ; i < ram_ptable.len; i++)
-    {
-        if((ram_ptable.parts[i].category == SDRAM) &&
-           (ram_ptable.parts[i].type == SYS_MEMORY))
-        {
+	len = smem_get_ram_ptable_len();
+
+	/* Calculating the size of the mem_info_ptr */
+	for (index = 0 ; index < len; index++)
+	{
+		smem_get_ram_ptable_entry(&ptn_entry, index);
+
+		if((ptn_entry.category == SDRAM) &&
+			(ptn_entry.type == SYS_MEMORY))
+		{
 
 			/* Pass along all other usable memory regions to Linux */
 			ret = dev_tree_add_mem_info(fdt,
-										memory_node_offset,
-										ram_ptable.parts[i].start,
-										ram_ptable.parts[i].size);
+							memory_node_offset,
+							ptn_entry.start,
+							ptn_entry.size);
 
 			if (ret)
 			{
-				dprintf(CRITICAL, "Failed to add secondary banks memory addresses\n");
+				dprintf(CRITICAL,
+					"Failed to add secondary banks memory addresses\n");
 				goto target_dev_tree_mem_err;
 			}
 
-       }
-    }
+		}
+	}
 
 target_dev_tree_mem_err:
 
-    return ret;
+	return ret;
 }
 
 void *target_get_scratch_address(void)
diff --git a/target/init.c b/target/init.c
index 88c0134..85778ff 100644
--- a/target/init.c
+++ b/target/init.c
@@ -171,3 +171,8 @@
 {
 	return "ci";
 }
+
+/* override for target specific usb phy reset. */
+__WEAK void target_usb_phy_reset(void)
+{
+}
diff --git a/target/msm8974/init.c b/target/msm8974/init.c
index bb7fe08..7812d44 100644
--- a/target/msm8974/init.c
+++ b/target/msm8974/init.c
@@ -751,3 +751,25 @@
 			return "ci";
 	}
 }
+
+/* UTMI MUX configuration to connect PHY to SNPS controller:
+ * Configure primary HS phy mux to use UTMI interface
+ * (connected to usb30 controller).
+ */
+static void tcsr_hs_phy_mux_configure(void)
+{
+	uint32_t reg;
+
+	reg = readl(USB2_PHY_SEL);
+
+	writel(reg | 0x1, USB2_PHY_SEL);
+}
+
+/* configure hs phy mux if using dwc controller */
+void target_usb_phy_mux_configure(void)
+{
+	if(!strcmp(target_usb_controller(), "dwc"))
+	{
+		tcsr_hs_phy_mux_configure();
+	}
+}