platform: apq8084: add HDMI related clocks
Add hdmi core, ahb and pixel clocks to support HDMI interface.
Change-Id: I31e44a480441f62d42df2c63c1a0ea4d516fd978
diff --git a/platform/apq8084/acpuclock.c b/platform/apq8084/acpuclock.c
index 7f903fb..78c7b64 100644
--- a/platform/apq8084/acpuclock.c
+++ b/platform/apq8084/acpuclock.c
@@ -556,6 +556,39 @@
}
}
+void hdmi_clk_enable(void)
+{
+ int ret;
+
+ /* Configure hdmi ahb clock */
+ ret = clk_get_set_enable("hdmi_ahb_clk", 0, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set hdmi_ahb_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure hdmi core clock */
+ ret = clk_get_set_enable("hdmi_core_clk", 19200000, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set hdmi_core_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+
+ /* Configure hdmi pixel clock */
+ ret = clk_get_set_enable("hdmi_extp_clk", 148500000, 1);
+ if(ret) {
+ dprintf(CRITICAL, "failed to set hdmi_extp_clk ret = %d\n", ret);
+ ASSERT(0);
+ }
+}
+
+void hdmi_clk_disable(void)
+{
+ clk_disable(clk_get("hdmi_extp_clk"));
+ clk_disable(clk_get("hdmi_core_clk"));
+ clk_disable(clk_get("hdmi_ahb_clk"));
+}
+
void edp_clk_enable(void)
{
int ret;
diff --git a/platform/apq8084/apq8084-clock.c b/platform/apq8084/apq8084-clock.c
index 08d6d2a..f01aa7e 100644
--- a/platform/apq8084/apq8084-clock.c
+++ b/platform/apq8084/apq8084-clock.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -47,6 +47,7 @@
#define gpll0_mm_source_val 5
#define edppll_270_mm_source_val 4
#define edppll_350_mm_source_val 4
+#define hdmipll_mm_source_val 3
struct clk_freq_tbl rcg_dummy_freq = F_END;
@@ -690,6 +691,69 @@
},
};
+static struct branch_clk mdss_hdmi_ahb_clk = {
+ .cbcr_reg = MDSS_HDMI_AHB_CBCR,
+ .has_sibling = 1,
+ .c = {
+ .dbg_name = "mdss_hdmi_ahb_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_hdmi_clk[] = {
+ F_MM( 19200000, cxo, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk hdmi_clk_src = {
+ .cmd_reg = HDMI_CMD_RCGR,
+ .cfg_reg = HDMI_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_hdmi_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "hdmi_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_hdmi_clk = {
+ .cbcr_reg = MDSS_HDMI_CBCR,
+ .has_sibling = 0,
+ .parent = &hdmi_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_hdmi_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
+static struct clk_freq_tbl ftbl_mdss_extpclk_clk[] = {
+ F_MDSS(148500000, hdmipll, 1, 0, 0),
+ F_END
+};
+
+static struct rcg_clk extpclk_clk_src = {
+ .cmd_reg = EXTPCLK_CMD_RCGR,
+ .cfg_reg = EXTPCLK_CFG_RCGR,
+ .set_rate = clock_lib2_rcg_set_rate_hid,
+ .freq_tbl = ftbl_mdss_extpclk_clk,
+ .current_freq = &rcg_dummy_freq,
+ .c = {
+ .dbg_name = "extpclk_clk_src",
+ .ops = &clk_ops_rcg,
+ },
+};
+
+static struct branch_clk mdss_extpclk_clk = {
+ .cbcr_reg = MDSS_EXTPCLK_CBCR,
+ .has_sibling = 0,
+ .parent = &extpclk_clk_src.c,
+ .c = {
+ .dbg_name = "mdss_extpclk_clk",
+ .ops = &clk_ops_branch,
+ },
+};
+
static struct clk_freq_tbl ftbl_mdss_edpaux_clk[] = {
F_MM(19200000, cxo, 1, 0, 0),
F_END
@@ -838,6 +902,10 @@
CLK_LOOKUP("edp_pixel_clk", mdss_edppixel_clk.c),
CLK_LOOKUP("edp_link_clk", mdss_edplink_clk.c),
CLK_LOOKUP("edp_aux_clk", mdss_edpaux_clk.c),
+
+ CLK_LOOKUP("hdmi_ahb_clk", mdss_hdmi_ahb_clk.c),
+ CLK_LOOKUP("hdmi_core_clk", mdss_hdmi_clk.c),
+ CLK_LOOKUP("hdmi_extp_clk", mdss_extpclk_clk.c),
};
void platform_clock_init(void)
diff --git a/platform/apq8084/include/platform/clock.h b/platform/apq8084/include/platform/clock.h
index 7f4ebfd..a3bb284 100644
--- a/platform/apq8084/include/platform/clock.h
+++ b/platform/apq8084/include/platform/clock.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
@@ -50,6 +50,13 @@
#define MDP_CBCR REG_MM(0x231C)
#define MDP_LUT_CBCR REG_MM(0x2320)
#define MDP_AHB_CBCR REG_MM(0x2308)
+#define MDSS_HDMI_AHB_CBCR REG_MM(0x230C)
+#define MDSS_HDMI_CBCR REG_MM(0x2338)
+#define MDSS_EXTPCLK_CBCR REG_MM(0x2324)
+#define EXTPCLK_CMD_RCGR REG_MM(0x2060)
+#define EXTPCLK_CFG_RCGR REG_MM(0x2064)
+#define HDMI_CMD_RCGR REG_MM(0x2100)
+#define HDMI_CFG_RCGR REG_MM(0x2104)
#define MDP_AXI_CMD_RCGR REG_MM(0x5040)
#define MDP_AXI_CFG_RCGR REG_MM(0x5044)