arch: arm: Add DSB instruction before cache invalidate
An instruction cache maintenance instruction need to be completed
before execute cache clean & invalidate. Fix the loop in the cache
routine for invalidating the cache.
Change-Id: I5ed54a89010f9d8170609966f118f2b5deaca0db
diff --git a/arch/arm/cache-ops.S b/arch/arm/cache-ops.S
index 22d9a2b..cfcbaa4 100644
--- a/arch/arm/cache-ops.S
+++ b/arch/arm/cache-ops.S
@@ -328,6 +328,7 @@
/* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
FUNCTION(arch_clean_invalidate_cache_range)
+ dsb
add r2, r0, r1 // Calculate the end address
bic r0,#(CACHE_LINE-1) // Align start with cache line
0: