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#ifndef __IRQS_FSM9010_H
#define __IRQS_FSM9010_H

/* MSM ACPU Interrupt Numbers */

/* 0-15:  STI/SGI (software triggered/generated interrupts)
 * 16-31: PPI (private peripheral interrupts)
 * 32+:   SPI (shared peripheral interrupts)
 */

#define GIC_PPI_START                          16
#define GIC_SPI_START                          32

#define INT_QTMR_NON_SECURE_PHY_TIMER_EXP      (GIC_PPI_START + 3)
#define INT_QTMR_VIRTUAL_TIMER_EXP             (GIC_PPI_START + 4)

#define INT_QTMR_FRM_0_PHYSICAL_TIMER_EXP      (GIC_SPI_START + 8)

#define USB1_HS_IRQ                            (GIC_SPI_START + 134)
#define USB30_EE1_IRQ                          (GIC_SPI_START + 224)
#define USB30_EE2_IRQ                          (GIC_SPI_START + 225)
#define USB30_POWER_EVENT_IRQ                  (GIC_SPI_START + 226)
#define USB30_HS_PHY_IRQ                       (GIC_SPI_START + 227)

/* Retrofit universal macro names */
#define INT_USB_HS                             USB1_HS_IRQ

#define EE0_KRAIT_HLOS_SPMI_PERIPH_IRQ         (GIC_SPI_START + 190)

#define NR_MSM_IRQS                            256
#define NR_GPIO_IRQS                           90
#define NR_BOARD_IRQS                          0

#define NR_IRQS                                (NR_MSM_IRQS + NR_GPIO_IRQS + \
                                               NR_BOARD_IRQS)

#define BLSP_QUP_IRQ(blsp_id, qup_id)          ((blsp_id == 1) ? \
                                               ((GIC_SPI_START + 95) + qup_id):\
                                               ((GIC_SPI_START + 101) + qup_id))

#define SDCC1_PWRCTL_IRQ                       (GIC_SPI_START + 138)
#endif	/* __IRQS_FSM9010_H */