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Shashank Mittal30262902012-02-21 15:37:24 -08001/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
Chandan Uddaraju78ae6752010-10-19 12:57:10 -07002 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29
30#include <reg.h>
Shashank Mittalcbd271d2011-01-14 15:18:33 -080031#include <endian.h>
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070032#include <mipi_dsi.h>
33#include <dev/fbcon.h>
Greg Griscod6250552011-06-29 14:40:23 -070034#include <stdlib.h>
Greg Grisco1073a5e2011-07-28 18:59:18 -070035#include <string.h>
Kinson Chike5c93432011-06-17 09:10:29 -070036#include <debug.h>
Kinson Chikfe931032011-07-21 10:01:34 -070037#include <target/display.h>
38#include <platform/iomap.h>
39#include <platform/clock.h>
Greg Grisco1073a5e2011-07-28 18:59:18 -070040#include <platform/timer.h>
Shashank Mittal4bfb2e32012-04-16 10:56:27 -070041#include <err.h>
42#include <msm_panel.h>
Kinson Chikfe931032011-07-21 10:01:34 -070043
44extern void mdp_disable(void);
Ajay Dudanib01e5062011-12-03 23:23:42 -080045extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg,
46 unsigned short num_of_lanes);
Kinson Chikfe931032011-07-21 10:01:34 -070047extern void mdp_shutdown(void);
48extern void mdp_start_dma(void);
Deepa Dinamania080a402011-11-05 18:59:26 -070049extern void dsb(void);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070050
Chandan Uddarajufe93e822010-11-21 20:44:47 -080051#if DISPLAY_MIPI_PANEL_TOSHIBA
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070052static struct fbcon_config mipi_fb_cfg = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080053 .height = TSH_MIPI_FB_HEIGHT,
54 .width = TSH_MIPI_FB_WIDTH,
55 .stride = TSH_MIPI_FB_WIDTH,
56 .format = FB_FORMAT_RGB888,
57 .bpp = 24,
58 .update_start = NULL,
59 .update_done = NULL,
Chandan Uddaraju78ae6752010-10-19 12:57:10 -070060};
Ajay Dudanib01e5062011-12-03 23:23:42 -080061
Kinson Chike5c93432011-06-17 09:10:29 -070062struct mipi_dsi_panel_config toshiba_panel_info = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080063 .mode = MIPI_VIDEO_MODE,
64 .num_of_lanes = 1,
65 .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl,
66 .panel_cmds = toshiba_panel_video_mode_cmds,
67 .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds),
Kinson Chike5c93432011-06-17 09:10:29 -070068};
Chandan Uddarajufe93e822010-11-21 20:44:47 -080069#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
70static struct fbcon_config mipi_fb_cfg = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080071 .height = NOV_MIPI_FB_HEIGHT,
72 .width = NOV_MIPI_FB_WIDTH,
73 .stride = NOV_MIPI_FB_WIDTH,
74 .format = FB_FORMAT_RGB888,
75 .bpp = 24,
76 .update_start = NULL,
77 .update_done = NULL,
Chandan Uddarajufe93e822010-11-21 20:44:47 -080078};
Ajay Dudanib01e5062011-12-03 23:23:42 -080079
Kinson Chike5c93432011-06-17 09:10:29 -070080struct mipi_dsi_panel_config novatek_panel_info = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080081 .mode = MIPI_CMD_MODE,
82 .num_of_lanes = 2,
83 .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl,
84 .panel_cmds = novatek_panel_cmd_mode_cmds,
85 .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds),
Kinson Chike5c93432011-06-17 09:10:29 -070086};
Chandan Uddarajufe93e822010-11-21 20:44:47 -080087#else
88static struct fbcon_config mipi_fb_cfg = {
Ajay Dudanib01e5062011-12-03 23:23:42 -080089 .height = 0,
90 .width = 0,
91 .stride = 0,
92 .format = 0,
93 .bpp = 0,
94 .update_start = NULL,
95 .update_done = NULL,
Chandan Uddarajufe93e822010-11-21 20:44:47 -080096};
97#endif
98
99static int cmd_mode_status = 0;
Greg Griscod6250552011-06-29 14:40:23 -0700100void secure_writel(uint32_t, uint32_t);
101uint32_t secure_readl(uint32_t);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700102
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800103struct mipi_dsi_panel_config *get_panel_info(void)
104{
105#if DISPLAY_MIPI_PANEL_TOSHIBA
Ajay Dudanib01e5062011-12-03 23:23:42 -0800106 return &toshiba_panel_info;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800107#elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE
Ajay Dudanib01e5062011-12-03 23:23:42 -0800108 return &novatek_panel_info;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800109#endif
Ajay Dudanib01e5062011-12-03 23:23:42 -0800110 return NULL;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800111}
112
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700113int dsi_cmd_dma_trigger_for_panel()
114{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800115 unsigned long ReadValue;
116 unsigned long count = 0;
117 int status = 0;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700118
Ajay Dudanib01e5062011-12-03 23:23:42 -0800119 writel(0x03030303, DSI_INT_CTRL);
120 writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER);
121 dsb();
122 ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
123 while (ReadValue != 0x00000001) {
124 ReadValue = readl(DSI_INT_CTRL) & 0x00000001;
125 count++;
126 if (count > 0xffff) {
127 status = FAIL;
128 dprintf(CRITICAL,
129 "Panel CMD: command mode dma test failed\n");
130 return status;
131 }
132 }
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700133
Ajay Dudanib01e5062011-12-03 23:23:42 -0800134 writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL);
135 dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n");
136 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700137}
138
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800139int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count)
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700140{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800141 int ret = 0;
142 struct mipi_dsi_cmd *cm;
143 int i = 0;
144 char pload[256];
145 uint32_t off;
Deepa Dinamania080a402011-11-05 18:59:26 -0700146
Ajay Dudanib01e5062011-12-03 23:23:42 -0800147 /* Align pload at 8 byte boundry */
148 off = pload;
149 off &= 0x07;
150 if (off)
151 off = 8 - off;
152 off += pload;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700153
Ajay Dudanib01e5062011-12-03 23:23:42 -0800154 cm = cmds;
155 for (i = 0; i < count; i++) {
156 memcpy((void *)off, (cm->payload), cm->size);
157 writel(off, DSI_DMA_CMD_OFFSET);
158 writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build
159 dsb();
160 ret += dsi_cmd_dma_trigger_for_panel();
161 udelay(80);
162 cm++;
163 }
164 return ret;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800165}
166
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800167/*
168 * mipi_dsi_cmd_rx: can receive at most 16 bytes
169 * per transaction since it only have 4 32bits reigsters
170 * to hold data.
171 * therefore Maximum Return Packet Size need to be set to 16.
172 * any return data more than MRPS need to be break down
173 * to multiple transactions.
174 */
175int mipi_dsi_cmds_rx(char **rp, int len)
176{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800177 uint32_t *lp, data;
178 char *dp;
179 int i, off, cnt;
180 int rlen, res;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800181
Ajay Dudanib01e5062011-12-03 23:23:42 -0800182 if (len <= 2)
183 rlen = 4; /* short read */
184 else
185 rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800186
Ajay Dudanib01e5062011-12-03 23:23:42 -0800187 if (rlen > MIPI_DSI_REG_LEN) {
188 return 0;
189 }
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800190
Ajay Dudanib01e5062011-12-03 23:23:42 -0800191 res = rlen & 0x03;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800192
Ajay Dudanib01e5062011-12-03 23:23:42 -0800193 rlen += res; /* 4 byte align */
194 lp = (uint32_t *) (*rp);
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800195
Ajay Dudanib01e5062011-12-03 23:23:42 -0800196 cnt = rlen;
197 cnt += 3;
198 cnt >>= 2;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800199
Ajay Dudanib01e5062011-12-03 23:23:42 -0800200 if (cnt > 4)
201 cnt = 4; /* 4 x 32 bits registers only */
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800202
Ajay Dudanib01e5062011-12-03 23:23:42 -0800203 off = 0x068; /* DSI_RDBK_DATA0 */
204 off += ((cnt - 1) * 4);
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800205
Ajay Dudanib01e5062011-12-03 23:23:42 -0800206 for (i = 0; i < cnt; i++) {
207 data = (uint32_t) readl(MIPI_DSI_BASE + off);
208 *lp++ = ntohl(data); /* to network byte order */
209 off -= 4;
210 }
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800211
Ajay Dudanib01e5062011-12-03 23:23:42 -0800212 if (len > 2) {
213 /*First 4 bytes + paded bytes will be header next len bytes would be payload */
214 for (i = 0; i < len; i++) {
215 dp = *rp;
216 dp[i] = dp[4 + res + i];
217 }
218 }
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800219
Ajay Dudanib01e5062011-12-03 23:23:42 -0800220 return len;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800221}
222
223static int mipi_dsi_cmd_bta_sw_trigger(void)
224{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800225 uint32_t data;
226 int cnt = 0;
227 int err = 0;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800228
Ajay Dudanib01e5062011-12-03 23:23:42 -0800229 writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */
230 while (cnt < 10000) {
231 data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */
232 if ((data & 0x0010) == 0)
233 break;
234 cnt++;
235 }
236 if (cnt == 10000)
237 err = 1;
238 return err;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800239}
240
241static uint32_t mipi_novatek_manufacture_id(void)
242{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800243 char rec_buf[24];
244 char *rp = rec_buf;
245 uint32_t *lp, data;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800246
Ajay Dudanib01e5062011-12-03 23:23:42 -0800247 mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1);
248 mipi_dsi_cmds_rx(&rp, 3);
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800249
Ajay Dudanib01e5062011-12-03 23:23:42 -0800250 lp = (uint32_t *) rp;
251 data = (uint32_t) * lp;
252 data = ntohl(data);
253 data = data >> 8;
254 return data;
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800255}
256
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800257int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo)
258{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800259 unsigned char DMA_STREAM1 = 0; // for mdp display processor path
260 unsigned char EMBED_MODE1 = 1; // from frame buffer
261 unsigned char POWER_MODE2 = 1; // from frame buffer
262 unsigned char PACK_TYPE1 = 1; // long packet
263 unsigned char VC1 = 0;
264 unsigned char DT1 = 0; // non embedded mode
265 unsigned short WC1 = 0; // for non embedded mode only
266 int status = 0;
267 unsigned char DLNx_EN;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700268
Ajay Dudanib01e5062011-12-03 23:23:42 -0800269 switch (pinfo->num_of_lanes) {
270 default:
271 case 1:
272 DLNx_EN = 1; // 1 lane
273 break;
274 case 2:
275 DLNx_EN = 3; // 2 lane
276 break;
277 case 3:
278 DLNx_EN = 7; // 3 lane
279 break;
280 }
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800281
Ajay Dudanib01e5062011-12-03 23:23:42 -0800282 writel(0x0001, DSI_SOFT_RESET);
283 writel(0x0000, DSI_SOFT_RESET);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800284
Ajay Dudanib01e5062011-12-03 23:23:42 -0800285 writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */
286 writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw
287 // trigger 0x4; dma stream1
Kinson Chike5c93432011-06-17 09:10:29 -0700288
Ajay Dudanib01e5062011-12-03 23:23:42 -0800289 writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this
290 // build
291 writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26
292 | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1,
293 DSI_COMMAND_MODE_DMA_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700294
Ajay Dudanib01e5062011-12-03 23:23:42 -0800295 status = mipi_dsi_cmds_tx(pinfo->panel_cmds, pinfo->num_of_panel_cmds);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700296
Ajay Dudanib01e5062011-12-03 23:23:42 -0800297 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700298}
299
Kinson Chike5c93432011-06-17 09:10:29 -0700300//TODO: Clean up arguments being passed in not being used
Ajay Dudanib01e5062011-12-03 23:23:42 -0800301int
302config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height,
303 unsigned short img_width, unsigned short img_height,
304 unsigned short hsync_porch0_fp,
305 unsigned short hsync_porch0_bp,
306 unsigned short vsync_porch0_fp,
307 unsigned short vsync_porch0_bp,
308 unsigned short hsync_width,
309 unsigned short vsync_width, unsigned short dst_format,
310 unsigned short traffic_mode, unsigned short datalane_num)
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700311{
312
Ajay Dudanib01e5062011-12-03 23:23:42 -0800313 unsigned char DST_FORMAT;
314 unsigned char TRAFIC_MODE;
315 unsigned char DLNx_EN;
316 // video mode data ctrl
317 int status = 0;
318 unsigned long low_pwr_stop_mode = 0;
319 unsigned char eof_bllp_pwr = 0x9;
320 unsigned char interleav = 0;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700321
Ajay Dudanib01e5062011-12-03 23:23:42 -0800322 // disable mdp first
323 mdp_disable();
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700324
Ajay Dudanib01e5062011-12-03 23:23:42 -0800325 writel(0x00000000, DSI_CLK_CTRL);
326 writel(0x00000000, DSI_CLK_CTRL);
327 writel(0x00000000, DSI_CLK_CTRL);
328 writel(0x00000000, DSI_CLK_CTRL);
329 writel(0x00000002, DSI_CLK_CTRL);
330 writel(0x00000006, DSI_CLK_CTRL);
331 writel(0x0000000e, DSI_CLK_CTRL);
332 writel(0x0000001e, DSI_CLK_CTRL);
333 writel(0x0000003e, DSI_CLK_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700334
Ajay Dudanib01e5062011-12-03 23:23:42 -0800335 writel(0, DSI_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700336
Ajay Dudanib01e5062011-12-03 23:23:42 -0800337 writel(0, DSI_ERR_INT_MASK0);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700338
Ajay Dudanib01e5062011-12-03 23:23:42 -0800339 DST_FORMAT = 0; // RGB565
340 dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n");
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700341
Ajay Dudanib01e5062011-12-03 23:23:42 -0800342 DLNx_EN = 1; // 1 lane with clk programming
343 dprintf(SPEW, "Data Lane: 1 lane\n");
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700344
Ajay Dudanib01e5062011-12-03 23:23:42 -0800345 TRAFIC_MODE = 0; // non burst mode with sync pulses
346 dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700347
Ajay Dudanib01e5062011-12-03 23:23:42 -0800348 writel(0x02020202, DSI_INT_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700349
Ajay Dudanib01e5062011-12-03 23:23:42 -0800350 writel(((img_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
351 DSI_VIDEO_MODE_ACTIVE_H);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700352
Ajay Dudanib01e5062011-12-03 23:23:42 -0800353 writel(((img_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
354 DSI_VIDEO_MODE_ACTIVE_V);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700355
Ajay Dudanib01e5062011-12-03 23:23:42 -0800356 writel(((img_height + vsync_porch0_fp + vsync_porch0_bp) << 16)
357 | img_width + hsync_porch0_fp + hsync_porch0_bp,
358 DSI_VIDEO_MODE_TOTAL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700359
Ajay Dudanib01e5062011-12-03 23:23:42 -0800360 writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700361
Ajay Dudanib01e5062011-12-03 23:23:42 -0800362 writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700363
Ajay Dudanib01e5062011-12-03 23:23:42 -0800364 writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700365
Ajay Dudanib01e5062011-12-03 23:23:42 -0800366 writel(1, DSI_EOT_PACKET_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700367
Ajay Dudanib01e5062011-12-03 23:23:42 -0800368 writel(0x00000100, DSI_MISR_VIDEO_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700369
Ajay Dudanib01e5062011-12-03 23:23:42 -0800370 writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8
371 | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700372
Ajay Dudanib01e5062011-12-03 23:23:42 -0800373 writel(0x67, DSI_CAL_STRENGTH_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700374
Ajay Dudanib01e5062011-12-03 23:23:42 -0800375 writel(0x80006711, DSI_CAL_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700376
Ajay Dudanib01e5062011-12-03 23:23:42 -0800377 writel(0x00010100, DSI_MISR_VIDEO_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700378
Ajay Dudanib01e5062011-12-03 23:23:42 -0800379 writel(0x00010100, DSI_INT_CTRL);
380 writel(0x02010202, DSI_INT_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700381
Ajay Dudanib01e5062011-12-03 23:23:42 -0800382 writel(0x02030303, DSI_INT_CTRL);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700383
Ajay Dudanib01e5062011-12-03 23:23:42 -0800384 writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4
385 | 0x103, DSI_CTRL);
386 mdelay(10);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700387
Ajay Dudanib01e5062011-12-03 23:23:42 -0800388 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700389}
390
Ajay Dudanib01e5062011-12-03 23:23:42 -0800391int
392config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height,
393 unsigned short img_width, unsigned short img_height,
394 unsigned short dst_format,
395 unsigned short traffic_mode, unsigned short datalane_num)
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800396{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800397 unsigned char DST_FORMAT;
398 unsigned char TRAFIC_MODE;
399 unsigned char DLNx_EN;
400 // video mode data ctrl
401 int status = 0;
Greg Griscod6250552011-06-29 14:40:23 -0700402 unsigned char interleav = 0;
403 unsigned char ystride = 0x03;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800404 // disable mdp first
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800405
Ajay Dudanib01e5062011-12-03 23:23:42 -0800406 writel(0x00000000, DSI_CLK_CTRL);
407 writel(0x00000000, DSI_CLK_CTRL);
408 writel(0x00000000, DSI_CLK_CTRL);
409 writel(0x00000000, DSI_CLK_CTRL);
410 writel(0x00000002, DSI_CLK_CTRL);
411 writel(0x00000006, DSI_CLK_CTRL);
412 writel(0x0000000e, DSI_CLK_CTRL);
413 writel(0x0000001e, DSI_CLK_CTRL);
414 writel(0x0000003e, DSI_CLK_CTRL);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800415
Ajay Dudanib01e5062011-12-03 23:23:42 -0800416 writel(0x10000000, DSI_ERR_INT_MASK0);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800417
Ajay Dudanib01e5062011-12-03 23:23:42 -0800418 // writel(0, DSI_CTRL);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800419
Ajay Dudanib01e5062011-12-03 23:23:42 -0800420 // writel(0, DSI_ERR_INT_MASK0);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800421
Ajay Dudanib01e5062011-12-03 23:23:42 -0800422 DST_FORMAT = 8; // RGB888
423 dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800424
Ajay Dudanib01e5062011-12-03 23:23:42 -0800425 DLNx_EN = 3; // 2 lane with clk programming
426 dprintf(SPEW, "Data Lane: 2 lane\n");
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800427
Ajay Dudanib01e5062011-12-03 23:23:42 -0800428 TRAFIC_MODE = 0; // non burst mode with sync pulses
429 dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800430
Ajay Dudanib01e5062011-12-03 23:23:42 -0800431 writel(0x02020202, DSI_INT_CTRL);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800432
Ajay Dudanib01e5062011-12-03 23:23:42 -0800433 writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
434 writel((img_width * ystride + 1) << 16 | 0x0039,
435 DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
436 writel((img_width * ystride + 1) << 16 | 0x0039,
437 DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
438 writel(img_height << 16 | img_width,
439 DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
440 writel(img_height << 16 | img_width,
441 DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
442 writel(0xEE, DSI_CAL_STRENGTH_CTRL);
443 writel(0x80000000, DSI_CAL_CTRL);
444 writel(0x40, DSI_TRIG_CTRL);
445 writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
446 writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
447 DSI_CTRL);
448 mdelay(10);
449 writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
450 writel(0x10000000, DSI_MISR_CMD_CTRL);
451 writel(0x00000040, DSI_ERR_INT_MASK0);
452 writel(0x1, DSI_EOT_PACKET_CTRL);
453 // writel(0x0, MDP_OVERLAYPROC0_START);
454 mdp_start_dma();
455 mdelay(10);
456 writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800457
Ajay Dudanib01e5062011-12-03 23:23:42 -0800458 status = 1;
459 return status;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800460}
461
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800462int mipi_dsi_video_config(unsigned short num_of_lanes)
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700463{
464
Ajay Dudanib01e5062011-12-03 23:23:42 -0800465 int status = 0;
466 unsigned long ReadValue;
467 unsigned long count = 0;
468 unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from
469 // bit16, high spd mode 0x0
470 unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or
471 // let cmd mode eng send packets in hs
472 // or lp mode
473 unsigned short image_wd = mipi_fb_cfg.width;
474 unsigned short image_ht = mipi_fb_cfg.height;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800475 unsigned short display_wd = mipi_fb_cfg.width;
476 unsigned short display_ht = mipi_fb_cfg.height;
477 unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK;
478 unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK;
479 unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES;
480 unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES;
481 unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH;
482 unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH;
483 unsigned short dst_format = 0;
484 unsigned short traffic_mode = 0;
Ajay Dudanib01e5062011-12-03 23:23:42 -0800485 unsigned short pack_pattern = 0x12; //BGR
486 unsigned char ystride = 3;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700487
Ajay Dudanib01e5062011-12-03 23:23:42 -0800488 low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA,
489 // bit24:HFP, bit28:PULSE MODE, need enough
490 // time for swithc from LP to HS
491 eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send
492 // packets in hs or lp mode
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700493
Ajay Dudanib01e5062011-12-03 23:23:42 -0800494 status +=
495 config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht,
496 hsync_porch_fp, hsync_porch_bp,
497 vsync_porch_fp, vsync_porch_bp, hsync_width,
498 vsync_width, dst_format, traffic_mode,
499 num_of_lanes);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700500
Ajay Dudanib01e5062011-12-03 23:23:42 -0800501 status +=
502 mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd,
503 image_ht, hsync_porch_fp, hsync_porch_bp,
504 vsync_porch_fp, vsync_porch_bp,
505 hsync_width, vsync_width, MIPI_FB_ADDR,
506 image_wd, pack_pattern, ystride);
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700507
Ajay Dudanib01e5062011-12-03 23:23:42 -0800508 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
509 while (ReadValue != 0x00010000) {
510 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
511 count++;
512 if (count > 0xffff) {
513 status = FAIL;
514 dprintf(CRITICAL, "Video lane test failed\n");
515 return status;
516 }
517 }
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700518
Ajay Dudanib01e5062011-12-03 23:23:42 -0800519 dprintf(SPEW, "Video lane tested successfully\n");
520 return status;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700521}
522
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800523int is_cmd_mode_enabled(void)
524{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800525 return cmd_mode_status;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800526}
527
Kinson Chike5c93432011-06-17 09:10:29 -0700528#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800529void mipi_dsi_cmd_mode_trigger(void)
530{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800531 int status = 0;
532 unsigned short display_wd = mipi_fb_cfg.width;
533 unsigned short display_ht = mipi_fb_cfg.height;
534 unsigned short image_wd = mipi_fb_cfg.width;
535 unsigned short image_ht = mipi_fb_cfg.height;
536 unsigned short dst_format = 0;
537 unsigned short traffic_mode = 0;
538 struct mipi_dsi_panel_config *panel_info = &novatek_panel_info;
539 status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes);
540 mdelay(50);
541 config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht,
542 dst_format, traffic_mode,
543 panel_info->num_of_lanes /* num_of_lanes */ );
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800544}
Kinson Chike5c93432011-06-17 09:10:29 -0700545#endif
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800546
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700547void mipi_dsi_shutdown(void)
548{
Chandan Uddaraju4877d372011-07-21 12:51:51 -0700549#if (!CONT_SPLASH_SCREEN)
Ajay Dudanib01e5062011-12-03 23:23:42 -0800550 mdp_shutdown();
551 writel(0x01010101, DSI_INT_CTRL);
552 writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700553
554#if (DISPLAY_MIPI_PANEL_NOVATEK_BLUE \
555 || DISPLAY_MIPI_PANEL_TOSHIBA)
Ajay Dudanib01e5062011-12-03 23:23:42 -0800556 secure_writel(0x0, DSI_CC_REG);
Shashank Mittal30262902012-02-21 15:37:24 -0800557 secure_writel(0x0, DSI_PIXEL_CC_REG);
Kinson Chike5c93432011-06-17 09:10:29 -0700558#endif
Ajay Dudanib01e5062011-12-03 23:23:42 -0800559 writel(0, DSI_CLK_CTRL);
560 writel(0, DSI_CTRL);
561 writel(0, DSIPHY_PLL_CTRL(0));
Chandan Uddaraju4877d372011-07-21 12:51:51 -0700562#else
563 /* To keep the splash screen displayed till kernel driver takes
564 control, do not turn off the video mode engine and clocks.
565 Only disabling the MIPI DSI IRQs */
566 writel(0x01010101, DSI_INT_CTRL);
567 writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
568#endif
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700569}
570
571struct fbcon_config *mipi_init(void)
572{
Ajay Dudanib01e5062011-12-03 23:23:42 -0800573 int status = 0;
574 struct mipi_dsi_panel_config *panel_info = get_panel_info();
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530575
576 if (panel_info == NULL) {
577 dprintf(CRITICAL, "Panel info is null\n");
578 return NULL;
579 }
580
Ajay Dudanib01e5062011-12-03 23:23:42 -0800581 /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530582#if (!DISPLAY_MIPI_PANEL_RENESAS)
Ajay Dudanib01e5062011-12-03 23:23:42 -0800583 writel(0x00001800, MMSS_SFPB_GPREG);
Aparna Mallavarapuf712f5e2011-08-04 21:11:00 +0530584#endif
Kinson Chike5c93432011-06-17 09:10:29 -0700585
586#if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61
Ajay Dudanib01e5062011-12-03 23:23:42 -0800587 mipi_dsi_phy_init(panel_info);
Kinson Chike5c93432011-06-17 09:10:29 -0700588#else
Ajay Dudanib01e5062011-12-03 23:23:42 -0800589 mipi_dsi_phy_ctrl_config(panel_info);
Kinson Chike5c93432011-06-17 09:10:29 -0700590#endif
591
Ajay Dudanib01e5062011-12-03 23:23:42 -0800592 status += mipi_dsi_panel_initialize(panel_info);
Kinson Chike5c93432011-06-17 09:10:29 -0700593
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800594#if DISPLAY_MIPI_PANEL_NOVATEK_BLUE
Ajay Dudanib01e5062011-12-03 23:23:42 -0800595 mipi_dsi_cmd_bta_sw_trigger();
596 mipi_novatek_manufacture_id();
Shashank Mittalcbd271d2011-01-14 15:18:33 -0800597#endif
Ajay Dudanib01e5062011-12-03 23:23:42 -0800598 mipi_fb_cfg.base = MIPI_FB_ADDR;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700599
Ajay Dudanib01e5062011-12-03 23:23:42 -0800600 if (panel_info->mode == MIPI_VIDEO_MODE)
601 status += mipi_dsi_video_config(panel_info->num_of_lanes);
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800602
Ajay Dudanib01e5062011-12-03 23:23:42 -0800603 if (panel_info->mode == MIPI_CMD_MODE)
604 cmd_mode_status = 1;
Chandan Uddarajufe93e822010-11-21 20:44:47 -0800605
Ajay Dudanib01e5062011-12-03 23:23:42 -0800606 return &mipi_fb_cfg;
Chandan Uddaraju78ae6752010-10-19 12:57:10 -0700607}
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700608
609int mipi_config(struct msm_fb_panel_data *panel)
610{
611 int ret = NO_ERROR;
612 struct msm_panel_info *pinfo;
613 struct mipi_dsi_panel_config mipi_pinfo;
614
615 if (!panel)
616 return ERR_INVALID_ARGS;
617
618 pinfo = &(panel->panel_info);
619 mipi_pinfo.mode = pinfo->mipi.mode;
620 mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes;
621 mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db;
622 mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds;
623 mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds;
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530624 mipi_pinfo.lane_swap = pinfo->mipi.lane_swap;
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700625
626 /* Enable MMSS_AHB_ARB_MATER_PORT_E for
627 arbiter master0 and master 1 request */
628#if (!DISPLAY_MIPI_PANEL_RENESAS)
629 writel(0x00001800, MMSS_SFPB_GPREG);
630#endif
631
632 mipi_dsi_phy_init(&mipi_pinfo);
633
634 ret += mipi_dsi_panel_initialize(&mipi_pinfo);
635
Channagoud Kadabi01c91822012-06-06 15:53:30 +0530636 if (pinfo->rotate && panel->rotate)
637 pinfo->rotate();
638
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700639 return ret;
640}
641
642int mipi_dsi_video_mode_config(unsigned short disp_width,
643 unsigned short disp_height,
644 unsigned short img_width,
645 unsigned short img_height,
646 unsigned short hsync_porch0_fp,
647 unsigned short hsync_porch0_bp,
648 unsigned short vsync_porch0_fp,
649 unsigned short vsync_porch0_bp,
650 unsigned short hsync_width,
651 unsigned short vsync_width,
652 unsigned short dst_format,
653 unsigned short traffic_mode,
654 unsigned char lane_en,
655 unsigned low_pwr_stop_mode,
656 unsigned char eof_bllp_pwr,
657 unsigned char interleav)
658{
659
660 int status = 0;
661
662 /* disable mdp first */
663 mdp_disable();
664
665 writel(0x00000000, DSI_CLK_CTRL);
666 writel(0x00000000, DSI_CLK_CTRL);
667 writel(0x00000000, DSI_CLK_CTRL);
668 writel(0x00000000, DSI_CLK_CTRL);
669 writel(0x00000002, DSI_CLK_CTRL);
670 writel(0x00000006, DSI_CLK_CTRL);
671 writel(0x0000000e, DSI_CLK_CTRL);
672 writel(0x0000001e, DSI_CLK_CTRL);
673 writel(0x0000003e, DSI_CLK_CTRL);
674
675 writel(0, DSI_CTRL);
676
677 writel(0, DSI_ERR_INT_MASK0);
678
679 writel(0x02020202, DSI_INT_CTRL);
680
681 writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp,
682 DSI_VIDEO_MODE_ACTIVE_H);
683
684 writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp),
685 DSI_VIDEO_MODE_ACTIVE_V);
686
687 if (mdp_get_revision() >= MDP_REV_41) {
688 writel(((disp_height + vsync_porch0_fp
689 + vsync_porch0_bp - 1) << 16)
690 | (disp_width + hsync_porch0_fp
691 + hsync_porch0_bp - 1),
692 DSI_VIDEO_MODE_TOTAL);
693 } else {
694 writel(((disp_height + vsync_porch0_fp
695 + vsync_porch0_bp) << 16)
696 | (disp_width + hsync_porch0_fp
697 + hsync_porch0_bp),
698 DSI_VIDEO_MODE_TOTAL);
699 }
700
701 writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC);
702
703 writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC);
704
705 writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS);
706
707 writel(1, DSI_EOT_PACKET_CTRL);
708
709 writel(0x00000100, DSI_MISR_VIDEO_CTRL);
710
Channagoud Kadabi539ef722012-03-29 16:02:50 +0530711 if (mdp_get_revision() >= MDP_REV_41) {
712 writel(low_pwr_stop_mode << 16 |
713 eof_bllp_pwr << 12 | traffic_mode << 8
714 | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
715 } else {
716 writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 |
717 eof_bllp_pwr << 12 | traffic_mode << 8
718 | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL);
719 }
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700720
721 writel(0x67, DSI_CAL_STRENGTH_CTRL);
722 writel(0x80006711, DSI_CAL_CTRL);
723 writel(0x00010100, DSI_MISR_VIDEO_CTRL);
724
725 writel(0x00010100, DSI_INT_CTRL);
726 writel(0x02010202, DSI_INT_CTRL);
727 writel(0x02030303, DSI_INT_CTRL);
728
729 writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4
730 | 0x103, DSI_CTRL);
731
732 return status;
733}
734
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530735int mipi_dsi_cmd_mode_config(unsigned short disp_width,
736 unsigned short disp_height,
737 unsigned short img_width,
738 unsigned short img_height,
739 unsigned short dst_format,
740 unsigned short traffic_mode)
741{
742 unsigned char DST_FORMAT;
743 unsigned char TRAFIC_MODE;
744 unsigned char DLNx_EN;
745 // video mode data ctrl
746 int status = 0;
747 unsigned char interleav = 0;
748 unsigned char ystride = 0x03;
749 // disable mdp first
750
751 writel(0x00000000, DSI_CLK_CTRL);
752 writel(0x00000000, DSI_CLK_CTRL);
753 writel(0x00000000, DSI_CLK_CTRL);
754 writel(0x00000000, DSI_CLK_CTRL);
755 writel(0x00000002, DSI_CLK_CTRL);
756 writel(0x00000006, DSI_CLK_CTRL);
757 writel(0x0000000e, DSI_CLK_CTRL);
758 writel(0x0000001e, DSI_CLK_CTRL);
759 writel(0x0000003e, DSI_CLK_CTRL);
760
761 writel(0x10000000, DSI_ERR_INT_MASK0);
762
763
764 DST_FORMAT = 8; // RGB888
765 dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n");
766
767 DLNx_EN = 3; // 2 lane with clk programming
768 dprintf(SPEW, "Data Lane: 2 lane\n");
769
770 TRAFIC_MODE = 0; // non burst mode with sync pulses
771 dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n");
772
773 writel(0x02020202, DSI_INT_CTRL);
774
775 writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL);
776 writel((img_width * ystride + 1) << 16 | 0x0039,
777 DSI_COMMAND_MODE_MDP_STREAM0_CTRL);
778 writel((img_width * ystride + 1) << 16 | 0x0039,
779 DSI_COMMAND_MODE_MDP_STREAM1_CTRL);
780 writel(img_height << 16 | img_width,
781 DSI_COMMAND_MODE_MDP_STREAM0_TOTAL);
782 writel(img_height << 16 | img_width,
783 DSI_COMMAND_MODE_MDP_STREAM1_TOTAL);
784 writel(0xEE, DSI_CAL_STRENGTH_CTRL);
785 writel(0x80000000, DSI_CAL_CTRL);
786 writel(0x40, DSI_TRIG_CTRL);
787 writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL);
788 writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105,
789 DSI_CTRL);
790 writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL);
791 writel(0x10000000, DSI_MISR_CMD_CTRL);
792 writel(0x00000040, DSI_ERR_INT_MASK0);
793 writel(0x1, DSI_EOT_PACKET_CTRL);
794
795 return NO_ERROR;
796}
797
Shashank Mittal4bfb2e32012-04-16 10:56:27 -0700798int mipi_dsi_on()
799{
800 int ret = NO_ERROR;
801 unsigned long ReadValue;
802 unsigned long count = 0;
803
804 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
805
806 mdelay(10);
807
808 while (ReadValue != 0x00010000) {
809 ReadValue = readl(DSI_INT_CTRL) & 0x00010000;
810 count++;
811 if (count > 0xffff) {
812 dprintf(CRITICAL, "Video lane test failed\n");
813 return ERROR;
814 }
815 }
816
817 dprintf(SPEW, "Video lane tested successfully\n");
818 return ret;
819}
820
821int mipi_dsi_off()
822{
823 writel(0x01010101, DSI_INT_CTRL);
824 writel(0x13FF3BFF, DSI_ERR_INT_MASK0);
825
826#if (!CONT_SPLASH_SCREEN)
827 writel(0, DSI_CLK_CTRL);
828 writel(0, DSI_CTRL);
829 writel(0, DSIPHY_PLL_CTRL(0));
830#endif
831
832 return NO_ERROR;
833}
Channagoud Kadabi10189fd2012-05-25 13:33:39 +0530834
835int mipi_cmd_trigger()
836{
837 writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER);
838
839 return NO_ERROR;
840}