Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
| 43 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 44 | |
| 45 | static int mdp_rev; |
| 46 | |
| 47 | void mdp_set_revision(int rev) |
| 48 | { |
| 49 | mdp_rev = rev; |
| 50 | } |
| 51 | |
| 52 | int mdp_get_revision() |
| 53 | { |
| 54 | return mdp_rev; |
| 55 | } |
| 56 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 57 | uint32_t mdss_mdp_intf_offset() |
| 58 | { |
| 59 | uint32_t mdss_mdp_intf_off; |
| 60 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 61 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 62 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) |
| 63 | mdss_mdp_intf_off = 0x59100; |
| 64 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 65 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 66 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 67 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 68 | |
| 69 | return mdss_mdp_intf_off; |
| 70 | } |
| 71 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 72 | void mdp_clk_gating_ctrl(void) |
| 73 | { |
| 74 | writel(0x40000000, MDP_CLK_CTRL0); |
| 75 | udelay(20); |
| 76 | writel(0x40000040, MDP_CLK_CTRL0); |
| 77 | writel(0x40000000, MDP_CLK_CTRL1); |
| 78 | writel(0x00400000, MDP_CLK_CTRL3); |
| 79 | udelay(20); |
| 80 | writel(0x00404000, MDP_CLK_CTRL3); |
| 81 | writel(0x40000000, MDP_CLK_CTRL4); |
| 82 | } |
| 83 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 84 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 85 | *pinfo, uint32_t pipe_base) |
| 86 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 87 | uint32_t src_size, out_size, stride, pipe_swap; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 88 | uint32_t fb_off = 0; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 89 | |
| 90 | /* write active region size*/ |
| 91 | src_size = (fb->height << 16) + fb->width; |
| 92 | out_size = src_size; |
| 93 | |
| 94 | if (pinfo->lcdc.dual_pipe) { |
| 95 | out_size = (fb->height << 16) + (fb->width / 2); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 96 | pipe_swap = (pinfo->lcdc.pipe_swap == TRUE) ? 1 : 0; |
| 97 | |
| 98 | if (pipe_swap && ((pipe_base == MDP_VP_0_RGB_0_BASE) || |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 99 | (pipe_base == MDP_VP_0_DMA_0_BASE) || |
| 100 | (pipe_base == MDP_VP_0_VIG_0_BASE))) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 101 | fb_off = (pinfo->xres / 2); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 102 | else if (!pipe_swap && ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 103 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 104 | (pipe_base == MDP_VP_0_VIG_1_BASE))) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 105 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | stride = (fb->stride * fb->bpp/8); |
| 109 | |
| 110 | writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
| 111 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 112 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 113 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 114 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 115 | writel(fb_off, pipe_base + PIPE_SSPP_SRC_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 116 | writel(0x00, pipe_base + PIPE_SSPP_OUT_XY); |
| 117 | |
| 118 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 119 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 120 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
| 121 | writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
| 122 | } |
| 123 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 124 | static void mdss_vbif_setup() |
| 125 | { |
| 126 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 127 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 128 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 129 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 130 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 131 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 132 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 133 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 134 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 135 | |
| 136 | /* |
| 137 | * Following configuration is needed because on some versions, |
| 138 | * recommended reset values are not stored. |
| 139 | */ |
| 140 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 141 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 142 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 143 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 144 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 145 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 146 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 147 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 148 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 149 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 150 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 151 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 152 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | } |
| 156 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 157 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 158 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 159 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 160 | uint32_t i, j; |
| 161 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 162 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 163 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 164 | /* max 3 MMB per register */ |
| 165 | reg_val |= client_id << (((j++) % 3) * 8); |
| 166 | if ((j % 3) == 0) { |
| 167 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 168 | free_smp_offset); |
| 169 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 170 | free_smp_offset); |
| 171 | reg_val = 0; |
| 172 | free_smp_offset += 4; |
| 173 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 174 | } |
| 175 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 176 | if (j % 3) { |
| 177 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 178 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 179 | free_smp_offset += 4; |
| 180 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 181 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 182 | return free_smp_offset; |
| 183 | } |
| 184 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 185 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 186 | uint32_t right_pipe) |
| 187 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 188 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 189 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 190 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 191 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 192 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 193 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 194 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) { |
| 195 | /* 8Kb per SMP on 8916 */ |
| 196 | smp_size = 8192; |
| 197 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 198 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 199 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 200 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 201 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 202 | fixed_smp_cnt = 2; |
| 203 | else |
| 204 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 205 | } |
| 206 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 207 | switch (pinfo->pipe_type) { |
| 208 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 209 | right_sspp_client_id = 0x11; /* 17 */ |
| 210 | break; |
| 211 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 212 | right_sspp_client_id = 0xD; /* 13 */ |
| 213 | break; |
| 214 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 215 | default: |
| 216 | right_sspp_client_id = 0x4; /* 4 */ |
| 217 | break; |
| 218 | } |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 219 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 220 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 221 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106)) { |
| 222 | switch (pinfo->pipe_type) { |
| 223 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 224 | left_sspp_client_id = 0x7; /* 7 */ |
| 225 | break; |
| 226 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 227 | left_sspp_client_id = 0x4; /* 4 */ |
| 228 | break; |
| 229 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 230 | default: |
| 231 | left_sspp_client_id = 0x1; /* 1 */ |
| 232 | break; |
| 233 | } |
| 234 | } else { |
| 235 | switch (pinfo->pipe_type) { |
| 236 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 237 | left_sspp_client_id = 0x10; /* 16 */ |
| 238 | break; |
| 239 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 240 | left_sspp_client_id = 0xA; /* 10 */ |
| 241 | break; |
| 242 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 243 | default: |
| 244 | left_sspp_client_id = 0x1; /* 1 */ |
| 245 | break; |
| 246 | } |
| 247 | } |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 248 | |
| 249 | /* Each pipe driving half the screen */ |
| 250 | if (pinfo->lcdc.dual_pipe) |
| 251 | xres /= 2; |
| 252 | |
| 253 | /* bpp = bytes per pixel of input image */ |
| 254 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 255 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 256 | |
| 257 | if (smp_cnt > 4) { |
| 258 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 259 | smp_cnt); |
| 260 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 261 | } |
| 262 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 263 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 264 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 265 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 266 | |
| 267 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 268 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 269 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 270 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 271 | } |
| 272 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 273 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 274 | fixed_smp_cnt, free_smp_offset); |
| 275 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 276 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 277 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 278 | } |
| 279 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 280 | void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 281 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 282 | uint32_t hsync_period, vsync_period; |
| 283 | uint32_t hsync_start_x, hsync_end_x; |
| 284 | uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 285 | uint32_t mdss_mdp_intf_off; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 286 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 287 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 288 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 289 | |
| 290 | if (pinfo == NULL) |
| 291 | return ERR_INVALID_ARGS; |
| 292 | |
| 293 | lcdc = &(pinfo->lcdc); |
| 294 | if (lcdc == NULL) |
| 295 | return ERR_INVALID_ARGS; |
| 296 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 297 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 298 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 299 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 300 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 301 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 302 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 303 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 308 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 309 | hsync_period = lcdc->h_pulse_width + |
| 310 | lcdc->h_back_porch + |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 311 | adjust_xres + lcdc->xres_pad + lcdc->h_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 312 | vsync_period = (lcdc->v_pulse_width + |
| 313 | lcdc->v_back_porch + |
| 314 | pinfo->yres + lcdc->yres_pad + |
| 315 | lcdc->v_front_porch); |
| 316 | |
| 317 | hsync_start_x = |
| 318 | lcdc->h_pulse_width + |
| 319 | lcdc->h_back_porch; |
| 320 | hsync_end_x = |
| 321 | hsync_period - lcdc->h_front_porch - 1; |
| 322 | |
| 323 | display_vstart = (lcdc->v_pulse_width + |
| 324 | lcdc->v_back_porch) |
| 325 | * hsync_period + lcdc->hsync_skew; |
| 326 | display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period) |
| 327 | +lcdc->hsync_skew - 1; |
| 328 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 329 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
| 330 | display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch; |
| 331 | display_vend -= lcdc->h_front_porch; |
| 332 | } |
| 333 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 334 | hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width; |
| 335 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 336 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 337 | writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off); |
| 338 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
| 339 | mdss_mdp_intf_off); |
| 340 | writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off); |
| 341 | writel(lcdc->v_pulse_width*hsync_period, |
| 342 | MDP_VSYNC_PULSE_WIDTH_F0 + |
| 343 | mdss_mdp_intf_off); |
| 344 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off); |
| 345 | writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off); |
| 346 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
| 347 | mdss_mdp_intf_off); |
| 348 | writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off); |
| 349 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
| 350 | mdss_mdp_intf_off); |
| 351 | writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off); |
| 352 | writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off); |
| 353 | writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off); |
| 354 | writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off); |
| 355 | writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off); |
| 356 | writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off); |
| 357 | writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off); |
| 358 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 359 | if (intf_base == MDP_INTF_0_BASE) /* eDP */ |
| 360 | writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
| 361 | else |
| 362 | writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 363 | } |
| 364 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 365 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 366 | *pinfo) |
| 367 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 368 | uint32_t mdp_rgb_size, height, width; |
| 369 | uint32_t reg_val; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 370 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 371 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 372 | width = fb->width; |
| 373 | |
| 374 | if (pinfo->lcdc.dual_pipe) |
| 375 | width /= 2; |
| 376 | |
| 377 | /* write active region size*/ |
| 378 | mdp_rgb_size = (height << 16) | width; |
| 379 | |
| 380 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 381 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 382 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 383 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 384 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 385 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 386 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 387 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 388 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 389 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 390 | |
| 391 | /* Baselayer for layer mixer 0 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 392 | switch (pinfo->pipe_type) { |
| 393 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 394 | reg_val = 0x0000200; |
| 395 | break; |
| 396 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 397 | reg_val = 0x0040000; |
| 398 | break; |
| 399 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 400 | default: |
| 401 | reg_val = 0x1; |
| 402 | break; |
| 403 | } |
| 404 | |
| 405 | writel(reg_val, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 406 | |
| 407 | if (pinfo->lcdc.dual_pipe) { |
| 408 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 409 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 410 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 411 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 412 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 413 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 414 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 415 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 416 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 417 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 418 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 419 | /* Baselayer for layer mixer 1 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 420 | switch (pinfo->pipe_type) { |
| 421 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 422 | reg_val = 0x1000; |
| 423 | break; |
| 424 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 425 | reg_val = 0x200000; |
| 426 | break; |
| 427 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 428 | default: |
| 429 | reg_val = 0x8; |
| 430 | break; |
| 431 | } |
| 432 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 433 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 434 | writel(reg_val, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 435 | else |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 436 | writel(reg_val, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 437 | } |
| 438 | } |
| 439 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 440 | void mdss_qos_remapper_setup(void) |
| 441 | { |
| 442 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 443 | uint32_t map; |
| 444 | |
| 445 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 446 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 447 | MDSS_MDP_HW_REV_102)) |
| 448 | map = 0xE9; |
| 449 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 450 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 451 | map = 0xA5; |
| 452 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 453 | MDSS_MDP_HW_REV_106)) |
| 454 | map = 0xAA; |
| 455 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 456 | MDSS_MDP_HW_REV_103)) |
| 457 | map = 0xFA; |
| 458 | else |
| 459 | return; |
| 460 | |
| 461 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 462 | } |
| 463 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 464 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 465 | struct fbcon_config *fb) |
| 466 | { |
| 467 | int ret = NO_ERROR; |
| 468 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 469 | uint32_t intf_sel = 0x100; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 470 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 471 | |
| 472 | mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); |
| 473 | |
| 474 | if (pinfo->mipi.dual_dsi) |
| 475 | mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 476 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 477 | mdp_clk_gating_ctrl(); |
| 478 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 479 | switch (pinfo->pipe_type) { |
| 480 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 481 | left_pipe = MDP_VP_0_RGB_0_BASE; |
| 482 | right_pipe = MDP_VP_0_RGB_1_BASE; |
| 483 | break; |
| 484 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 485 | left_pipe = MDP_VP_0_DMA_0_BASE; |
| 486 | right_pipe = MDP_VP_0_DMA_1_BASE; |
| 487 | break; |
| 488 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 489 | default: |
| 490 | left_pipe = MDP_VP_0_VIG_0_BASE; |
| 491 | right_pipe = MDP_VP_0_VIG_1_BASE; |
| 492 | break; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 493 | } |
| 494 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 495 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 496 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 497 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 498 | mdss_qos_remapper_setup(); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 499 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 500 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 501 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 502 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 503 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 504 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 505 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 506 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 507 | writel(0x1F20, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 508 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 509 | if (pinfo->mipi.dual_dsi) { |
| 510 | writel(0x1F30, MDP_CTL_1_BASE + CTL_TOP); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 511 | intf_sel |= BIT(16); /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 512 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 513 | |
| 514 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 515 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 516 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 517 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 518 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 519 | |
| 520 | return 0; |
| 521 | } |
| 522 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 523 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 524 | { |
| 525 | int ret = NO_ERROR; |
| 526 | struct lcdc_panel_info *lcdc = NULL; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 527 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 528 | |
| 529 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 530 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 531 | switch (pinfo->pipe_type) { |
| 532 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 533 | left_pipe = MDP_VP_0_RGB_0_BASE; |
| 534 | right_pipe = MDP_VP_0_RGB_1_BASE; |
| 535 | break; |
| 536 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 537 | left_pipe = MDP_VP_0_DMA_0_BASE; |
| 538 | right_pipe = MDP_VP_0_DMA_1_BASE; |
| 539 | break; |
| 540 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 541 | default: |
| 542 | left_pipe = MDP_VP_0_VIG_0_BASE; |
| 543 | right_pipe = MDP_VP_0_VIG_1_BASE; |
| 544 | break; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 545 | } |
| 546 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 547 | mdp_clk_gating_ctrl(); |
| 548 | |
| 549 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 550 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 551 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 552 | mdss_qos_remapper_setup(); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 553 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 554 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 555 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 556 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 557 | |
| 558 | mdss_layer_mixer_setup(fb, pinfo); |
| 559 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 560 | if (pinfo->lcdc.dual_pipe) |
| 561 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 562 | else |
| 563 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 564 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 565 | writel(0x9, MDP_DISP_INTF_SEL); |
| 566 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 567 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 568 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 569 | |
| 570 | return 0; |
| 571 | } |
| 572 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 573 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 574 | struct fbcon_config *fb) |
| 575 | { |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 576 | uint32_t intf_sel = BIT(8); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 577 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 578 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 579 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 580 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 581 | uint32_t mdss_mdp_intf_off = 0; |
| 582 | |
| 583 | if (pinfo == NULL) |
| 584 | return ERR_INVALID_ARGS; |
| 585 | |
| 586 | lcdc = &(pinfo->lcdc); |
| 587 | if (lcdc == NULL) |
| 588 | return ERR_INVALID_ARGS; |
| 589 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 590 | if (pinfo->lcdc.split_display) { |
| 591 | writel(0x102, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 592 | writel(0x102, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 593 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 594 | } |
| 595 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 596 | mdss_mdp_intf_off = mdss_mdp_intf_offset(); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 597 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 598 | mdp_clk_gating_ctrl(); |
| 599 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 600 | if (pinfo->mipi.dual_dsi) |
| 601 | intf_sel |= BIT(16); /* INTF 2 enable */ |
| 602 | |
| 603 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 604 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 605 | switch (pinfo->pipe_type) { |
| 606 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 607 | left_pipe = MDP_VP_0_RGB_0_BASE; |
| 608 | right_pipe = MDP_VP_0_RGB_1_BASE; |
| 609 | break; |
| 610 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 611 | left_pipe = MDP_VP_0_DMA_0_BASE; |
| 612 | right_pipe = MDP_VP_0_DMA_1_BASE; |
| 613 | break; |
| 614 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 615 | default: |
| 616 | left_pipe = MDP_VP_0_VIG_0_BASE; |
| 617 | right_pipe = MDP_VP_0_VIG_1_BASE; |
| 618 | break; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 619 | } |
| 620 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 621 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 622 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 623 | mdss_qos_remapper_setup(); |
| 624 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 625 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 626 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 627 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 628 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 629 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 630 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 631 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 632 | writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 633 | writel(0x21f20, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 634 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 635 | if (pinfo->mipi.dual_dsi) { |
| 636 | writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
| 637 | writel(0x21F30, MDP_CTL_1_BASE + CTL_TOP); |
| 638 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 639 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 640 | return ret; |
| 641 | } |
| 642 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 643 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 644 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 645 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 646 | switch (pinfo->pipe_type) { |
| 647 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 648 | ctl0_reg_val = 0x22048; |
| 649 | ctl1_reg_val = 0x24090; |
| 650 | break; |
| 651 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 652 | ctl0_reg_val = 0x22840; |
| 653 | ctl1_reg_val = 0x25080; |
| 654 | break; |
| 655 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 656 | default: |
| 657 | ctl0_reg_val = 0x22041; |
| 658 | ctl1_reg_val = 0x24082; |
| 659 | break; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 660 | } |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 661 | |
| 662 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 663 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 664 | writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 665 | |
| 666 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 667 | } |
| 668 | |
| 669 | int mdp_dsi_video_off() |
| 670 | { |
| 671 | if(!target_cont_splash_screen()) |
| 672 | { |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 673 | writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN + |
| 674 | mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 675 | mdelay(60); |
| 676 | /* Ping-Pong done Tear Check Read/Write */ |
| 677 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 678 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 679 | } |
| 680 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 681 | writel(0x00000000, MDP_INTR_EN); |
| 682 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 683 | return NO_ERROR; |
| 684 | } |
| 685 | |
| 686 | int mdp_dsi_cmd_off() |
| 687 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 688 | if(!target_cont_splash_screen()) |
| 689 | { |
| 690 | /* Ping-Pong done Tear Check Read/Write */ |
| 691 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 692 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 693 | } |
| 694 | writel(0x00000000, MDP_INTR_EN); |
| 695 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 696 | return NO_ERROR; |
| 697 | } |
| 698 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 699 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 700 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 701 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 702 | switch (pinfo->pipe_type) { |
| 703 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 704 | ctl0_reg_val = 0x22048; |
| 705 | ctl1_reg_val = 0x24090; |
| 706 | break; |
| 707 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 708 | ctl0_reg_val = 0x22840; |
| 709 | ctl1_reg_val = 0x25080; |
| 710 | break; |
| 711 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 712 | default: |
| 713 | ctl0_reg_val = 0x22041; |
| 714 | ctl1_reg_val = 0x24082; |
| 715 | break; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 716 | } |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 717 | |
| 718 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 719 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 720 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 721 | return NO_ERROR; |
| 722 | } |
| 723 | |
| 724 | void mdp_disable(void) |
| 725 | { |
| 726 | |
| 727 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 728 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 729 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 730 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame^] | 731 | uint32_t ctl0_reg_val; |
| 732 | switch (pinfo->pipe_type) { |
| 733 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 734 | ctl0_reg_val = 0x22048; |
| 735 | break; |
| 736 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 737 | ctl0_reg_val = 0x22840; |
| 738 | break; |
| 739 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 740 | default: |
| 741 | ctl0_reg_val = 0x22041; |
| 742 | break; |
| 743 | } |
| 744 | |
| 745 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 746 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 747 | return NO_ERROR; |
| 748 | } |
| 749 | |
| 750 | int mdp_edp_off(void) |
| 751 | { |
| 752 | if (!target_cont_splash_screen()) { |
| 753 | |
| 754 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 755 | mdss_mdp_intf_offset()); |
| 756 | mdelay(60); |
| 757 | /* Ping-Pong done Tear Check Read/Write */ |
| 758 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 759 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 760 | writel(0x00000000, MDP_INTR_EN); |
| 761 | } |
| 762 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 763 | writel(0x00000000, MDP_INTR_EN); |
| 764 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 765 | return NO_ERROR; |
| 766 | } |