Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2013, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 35 | #include <string.h> |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 36 | #include <debug.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 37 | #include <target/display.h> |
| 38 | #include <platform/iomap.h> |
| 39 | #include <platform/clock.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 40 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 41 | #include <err.h> |
| 42 | #include <msm_panel.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 43 | |
| 44 | extern void mdp_disable(void); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 45 | extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 46 | unsigned short num_of_lanes); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 47 | extern void mdp_shutdown(void); |
| 48 | extern void mdp_start_dma(void); |
Deepa Dinamani | a080a40 | 2011-11-05 18:59:26 -0700 | [diff] [blame] | 49 | extern void dsb(void); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 50 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 51 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 52 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 53 | .height = TSH_MIPI_FB_HEIGHT, |
| 54 | .width = TSH_MIPI_FB_WIDTH, |
| 55 | .stride = TSH_MIPI_FB_WIDTH, |
| 56 | .format = FB_FORMAT_RGB888, |
| 57 | .bpp = 24, |
| 58 | .update_start = NULL, |
| 59 | .update_done = NULL, |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 60 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 61 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 62 | struct mipi_dsi_panel_config toshiba_panel_info = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 63 | .mode = MIPI_VIDEO_MODE, |
| 64 | .num_of_lanes = 1, |
| 65 | .dsi_phy_config = &mipi_dsi_toshiba_panel_phy_ctrl, |
| 66 | .panel_cmds = toshiba_panel_video_mode_cmds, |
| 67 | .num_of_panel_cmds = ARRAY_SIZE(toshiba_panel_video_mode_cmds), |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 68 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 69 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
| 70 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 71 | .height = NOV_MIPI_FB_HEIGHT, |
| 72 | .width = NOV_MIPI_FB_WIDTH, |
| 73 | .stride = NOV_MIPI_FB_WIDTH, |
| 74 | .format = FB_FORMAT_RGB888, |
| 75 | .bpp = 24, |
| 76 | .update_start = NULL, |
| 77 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 78 | }; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 79 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 80 | struct mipi_dsi_panel_config novatek_panel_info = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 81 | .mode = MIPI_CMD_MODE, |
| 82 | .num_of_lanes = 2, |
| 83 | .dsi_phy_config = &mipi_dsi_novatek_panel_phy_ctrl, |
| 84 | .panel_cmds = novatek_panel_cmd_mode_cmds, |
| 85 | .num_of_panel_cmds = ARRAY_SIZE(novatek_panel_cmd_mode_cmds), |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 86 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 87 | #else |
| 88 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 89 | .height = 0, |
| 90 | .width = 0, |
| 91 | .stride = 0, |
| 92 | .format = 0, |
| 93 | .bpp = 0, |
| 94 | .update_start = NULL, |
| 95 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 96 | }; |
| 97 | #endif |
| 98 | |
| 99 | static int cmd_mode_status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 100 | void secure_writel(uint32_t, uint32_t); |
| 101 | uint32_t secure_readl(uint32_t); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 102 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 103 | struct mipi_dsi_panel_config *get_panel_info(void) |
| 104 | { |
| 105 | #if DISPLAY_MIPI_PANEL_TOSHIBA |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 106 | return &toshiba_panel_info; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 107 | #elif DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 108 | return &novatek_panel_info; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 109 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 110 | return NULL; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 111 | } |
| 112 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 113 | int dsi_cmd_dma_trigger_for_panel() |
| 114 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 115 | unsigned long ReadValue; |
| 116 | unsigned long count = 0; |
| 117 | int status = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 118 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 119 | writel(0x03030303, DSI_INT_CTRL); |
| 120 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 121 | dsb(); |
| 122 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 123 | while (ReadValue != 0x00000001) { |
| 124 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 125 | count++; |
| 126 | if (count > 0xffff) { |
| 127 | status = FAIL; |
| 128 | dprintf(CRITICAL, |
| 129 | "Panel CMD: command mode dma test failed\n"); |
| 130 | return status; |
| 131 | } |
| 132 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 133 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 134 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
| 135 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
| 136 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 137 | } |
| 138 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 139 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 140 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 141 | int ret = 0; |
| 142 | struct mipi_dsi_cmd *cm; |
| 143 | int i = 0; |
| 144 | char pload[256]; |
| 145 | uint32_t off; |
Deepa Dinamani | a080a40 | 2011-11-05 18:59:26 -0700 | [diff] [blame] | 146 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 147 | /* Align pload at 8 byte boundry */ |
| 148 | off = pload; |
| 149 | off &= 0x07; |
| 150 | if (off) |
| 151 | off = 8 - off; |
| 152 | off += pload; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 153 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 154 | cm = cmds; |
| 155 | for (i = 0; i < count; i++) { |
| 156 | memcpy((void *)off, (cm->payload), cm->size); |
| 157 | writel(off, DSI_DMA_CMD_OFFSET); |
| 158 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 159 | dsb(); |
| 160 | ret += dsi_cmd_dma_trigger_for_panel(); |
| 161 | udelay(80); |
| 162 | cm++; |
| 163 | } |
| 164 | return ret; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 165 | } |
| 166 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 167 | /* |
| 168 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 169 | * per transaction since it only have 4 32bits reigsters |
| 170 | * to hold data. |
| 171 | * therefore Maximum Return Packet Size need to be set to 16. |
| 172 | * any return data more than MRPS need to be break down |
| 173 | * to multiple transactions. |
| 174 | */ |
| 175 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 176 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 177 | uint32_t *lp, data; |
| 178 | char *dp; |
| 179 | int i, off, cnt; |
| 180 | int rlen, res; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 181 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 182 | if (len <= 2) |
| 183 | rlen = 4; /* short read */ |
| 184 | else |
| 185 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 186 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 187 | if (rlen > MIPI_DSI_REG_LEN) { |
| 188 | return 0; |
| 189 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 190 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 191 | res = rlen & 0x03; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 192 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 193 | rlen += res; /* 4 byte align */ |
| 194 | lp = (uint32_t *) (*rp); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 195 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 196 | cnt = rlen; |
| 197 | cnt += 3; |
| 198 | cnt >>= 2; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 199 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 200 | if (cnt > 4) |
| 201 | cnt = 4; /* 4 x 32 bits registers only */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 202 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 203 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 204 | off += ((cnt - 1) * 4); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 205 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 206 | for (i = 0; i < cnt; i++) { |
| 207 | data = (uint32_t) readl(MIPI_DSI_BASE + off); |
| 208 | *lp++ = ntohl(data); /* to network byte order */ |
| 209 | off -= 4; |
| 210 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 211 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 212 | if (len > 2) { |
| 213 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 214 | for (i = 0; i < len; i++) { |
| 215 | dp = *rp; |
| 216 | dp[i] = dp[4 + res + i]; |
| 217 | } |
| 218 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 219 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 220 | return len; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | static int mipi_dsi_cmd_bta_sw_trigger(void) |
| 224 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 225 | uint32_t data; |
| 226 | int cnt = 0; |
| 227 | int err = 0; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 228 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 229 | writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */ |
| 230 | while (cnt < 10000) { |
| 231 | data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */ |
| 232 | if ((data & 0x0010) == 0) |
| 233 | break; |
| 234 | cnt++; |
| 235 | } |
| 236 | if (cnt == 10000) |
| 237 | err = 1; |
| 238 | return err; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | static uint32_t mipi_novatek_manufacture_id(void) |
| 242 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 243 | char rec_buf[24]; |
| 244 | char *rp = rec_buf; |
| 245 | uint32_t *lp, data; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 246 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 247 | mipi_dsi_cmds_tx(&novatek_panel_manufacture_id_cmd, 1); |
| 248 | mipi_dsi_cmds_rx(&rp, 3); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 249 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 250 | lp = (uint32_t *) rp; |
| 251 | data = (uint32_t) * lp; |
| 252 | data = ntohl(data); |
| 253 | data = data >> 8; |
| 254 | return data; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 255 | } |
| 256 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame^] | 257 | int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 258 | { |
| 259 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 260 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 261 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 262 | uint8_t PACK_TYPE1; // long packet |
| 263 | uint8_t VC1 = 0; |
| 264 | uint8_t DT1 = 0; // non embedded mode |
| 265 | uint8_t WC1 = 0; // for non embedded mode only |
| 266 | int status = 0; |
| 267 | uint8_t DLNx_EN; |
| 268 | |
| 269 | switch (pinfo->num_of_lanes) { |
| 270 | default: |
| 271 | case 1: |
| 272 | DLNx_EN = 1; // 1 lane |
| 273 | break; |
| 274 | case 2: |
| 275 | DLNx_EN = 3; // 2 lane |
| 276 | break; |
| 277 | case 3: |
| 278 | DLNx_EN = 7; // 3 lane |
| 279 | break; |
| 280 | case 4: |
| 281 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 282 | break; |
| 283 | } |
| 284 | |
| 285 | PACK_TYPE1 = pinfo->pack; |
| 286 | |
| 287 | writel(0x0001, DSI_SOFT_RESET); |
| 288 | writel(0x0000, DSI_SOFT_RESET); |
| 289 | |
| 290 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
| 291 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 292 | // trigger 0x4; dma stream1 |
| 293 | |
| 294 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
| 295 | // build |
| 296 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 297 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 298 | DSI_COMMAND_MODE_DMA_CTRL); |
| 299 | |
| 300 | if (pinfo->panel_cmds) |
| 301 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 302 | pinfo->num_of_panel_cmds); |
| 303 | |
| 304 | return status; |
| 305 | } |
| 306 | |
| 307 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 308 | int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 309 | { |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 310 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 311 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 312 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 313 | uint8_t PACK_TYPE1; // long packet |
| 314 | uint8_t VC1 = 0; |
| 315 | uint8_t DT1 = 0; // non embedded mode |
| 316 | uint8_t WC1 = 0; // for non embedded mode only |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 317 | int status = 0; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 318 | uint8_t DLNx_EN; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 319 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 320 | switch (pinfo->num_of_lanes) { |
| 321 | default: |
| 322 | case 1: |
| 323 | DLNx_EN = 1; // 1 lane |
| 324 | break; |
| 325 | case 2: |
| 326 | DLNx_EN = 3; // 2 lane |
| 327 | break; |
| 328 | case 3: |
| 329 | DLNx_EN = 7; // 3 lane |
| 330 | break; |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 331 | case 4: |
| 332 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 333 | break; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 334 | } |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 335 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 336 | PACK_TYPE1 = pinfo->pack; |
| 337 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 338 | writel(0x0001, DSI_SOFT_RESET); |
| 339 | writel(0x0000, DSI_SOFT_RESET); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 340 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 341 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
| 342 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 343 | // trigger 0x4; dma stream1 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 344 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 345 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
| 346 | // build |
| 347 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 348 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 349 | DSI_COMMAND_MODE_DMA_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 350 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 351 | if (pinfo->panel_cmds) |
| 352 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 353 | pinfo->num_of_panel_cmds); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 354 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 355 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 356 | } |
| 357 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 358 | //TODO: Clean up arguments being passed in not being used |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 359 | int |
| 360 | config_dsi_video_mode(unsigned short disp_width, unsigned short disp_height, |
| 361 | unsigned short img_width, unsigned short img_height, |
| 362 | unsigned short hsync_porch0_fp, |
| 363 | unsigned short hsync_porch0_bp, |
| 364 | unsigned short vsync_porch0_fp, |
| 365 | unsigned short vsync_porch0_bp, |
| 366 | unsigned short hsync_width, |
| 367 | unsigned short vsync_width, unsigned short dst_format, |
| 368 | unsigned short traffic_mode, unsigned short datalane_num) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 369 | { |
| 370 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 371 | unsigned char DST_FORMAT; |
| 372 | unsigned char TRAFIC_MODE; |
| 373 | unsigned char DLNx_EN; |
| 374 | // video mode data ctrl |
| 375 | int status = 0; |
| 376 | unsigned long low_pwr_stop_mode = 0; |
| 377 | unsigned char eof_bllp_pwr = 0x9; |
| 378 | unsigned char interleav = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 379 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 380 | // disable mdp first |
| 381 | mdp_disable(); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 382 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 383 | writel(0x00000000, DSI_CLK_CTRL); |
| 384 | writel(0x00000000, DSI_CLK_CTRL); |
| 385 | writel(0x00000000, DSI_CLK_CTRL); |
| 386 | writel(0x00000000, DSI_CLK_CTRL); |
| 387 | writel(0x00000002, DSI_CLK_CTRL); |
| 388 | writel(0x00000006, DSI_CLK_CTRL); |
| 389 | writel(0x0000000e, DSI_CLK_CTRL); |
| 390 | writel(0x0000001e, DSI_CLK_CTRL); |
| 391 | writel(0x0000003e, DSI_CLK_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 392 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 393 | writel(0, DSI_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 394 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 395 | writel(0, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 396 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 397 | DST_FORMAT = 0; // RGB565 |
| 398 | dprintf(SPEW, "DSI_Video_Mode - Dst Format: RGB565\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 399 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 400 | DLNx_EN = 1; // 1 lane with clk programming |
| 401 | dprintf(SPEW, "Data Lane: 1 lane\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 402 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 403 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 404 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 405 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 406 | writel(0x02020202, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 407 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 408 | writel(((hsync_width + img_width + hsync_porch0_bp) << 16) |
| 409 | | (hsync_width + hsync_porch0_bp), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 410 | DSI_VIDEO_MODE_ACTIVE_H); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 411 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 412 | writel(((vsync_width + img_height + vsync_porch0_bp) << 16) |
| 413 | | (vsync_width + vsync_porch0_bp), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 414 | DSI_VIDEO_MODE_ACTIVE_V); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 415 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 416 | writel(((vsync_width + img_height + vsync_porch0_fp + vsync_porch0_bp - 1) << 16) |
| 417 | | (hsync_width + img_width + hsync_porch0_fp + hsync_porch0_bp - 1), |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 418 | DSI_VIDEO_MODE_TOTAL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 419 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 420 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 421 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 422 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 423 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 424 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 425 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 426 | writel(1, DSI_EOT_PACKET_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 427 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 428 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 429 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 430 | writel(low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | TRAFIC_MODE << 8 |
| 431 | | DST_FORMAT << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 432 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 433 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 434 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 435 | writel(0x80006711, DSI_CAL_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 436 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 437 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 438 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 439 | writel(0x00010100, DSI_INT_CTRL); |
| 440 | writel(0x02010202, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 441 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 442 | writel(0x02030303, DSI_INT_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 443 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 444 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 |
| 445 | | 0x103, DSI_CTRL); |
| 446 | mdelay(10); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 447 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 448 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 449 | } |
| 450 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 451 | int |
| 452 | config_dsi_cmd_mode(unsigned short disp_width, unsigned short disp_height, |
| 453 | unsigned short img_width, unsigned short img_height, |
| 454 | unsigned short dst_format, |
| 455 | unsigned short traffic_mode, unsigned short datalane_num) |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 456 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 457 | unsigned char DST_FORMAT; |
| 458 | unsigned char TRAFIC_MODE; |
| 459 | unsigned char DLNx_EN; |
| 460 | // video mode data ctrl |
| 461 | int status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 462 | unsigned char interleav = 0; |
| 463 | unsigned char ystride = 0x03; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 464 | // disable mdp first |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 465 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 466 | writel(0x00000000, DSI_CLK_CTRL); |
| 467 | writel(0x00000000, DSI_CLK_CTRL); |
| 468 | writel(0x00000000, DSI_CLK_CTRL); |
| 469 | writel(0x00000000, DSI_CLK_CTRL); |
| 470 | writel(0x00000002, DSI_CLK_CTRL); |
| 471 | writel(0x00000006, DSI_CLK_CTRL); |
| 472 | writel(0x0000000e, DSI_CLK_CTRL); |
| 473 | writel(0x0000001e, DSI_CLK_CTRL); |
| 474 | writel(0x0000003e, DSI_CLK_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 475 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 476 | writel(0x10000000, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 477 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 478 | // writel(0, DSI_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 479 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 480 | // writel(0, DSI_ERR_INT_MASK0); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 481 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 482 | DST_FORMAT = 8; // RGB888 |
| 483 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 484 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 485 | DLNx_EN = 3; // 2 lane with clk programming |
| 486 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 487 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 488 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 489 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 490 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 491 | writel(0x02020202, DSI_INT_CTRL); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 492 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 493 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 494 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 495 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 496 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 497 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 498 | writel(img_height << 16 | img_width, |
| 499 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 500 | writel(img_height << 16 | img_width, |
| 501 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 502 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 503 | writel(0x80000000, DSI_CAL_CTRL); |
| 504 | writel(0x40, DSI_TRIG_CTRL); |
| 505 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 506 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 507 | DSI_CTRL); |
| 508 | mdelay(10); |
| 509 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 510 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 511 | writel(0x00000040, DSI_ERR_INT_MASK0); |
| 512 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 513 | // writel(0x0, MDP_OVERLAYPROC0_START); |
| 514 | mdp_start_dma(); |
| 515 | mdelay(10); |
| 516 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 517 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 518 | status = 1; |
| 519 | return status; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 520 | } |
| 521 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 522 | int mipi_dsi_video_config(unsigned short num_of_lanes) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 523 | { |
| 524 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 525 | int status = 0; |
| 526 | unsigned long ReadValue; |
| 527 | unsigned long count = 0; |
| 528 | unsigned long low_pwr_stop_mode = 0; // low power mode 0x1111 start from |
| 529 | // bit16, high spd mode 0x0 |
| 530 | unsigned char eof_bllp_pwr = 0x9; // bit 12, 15, 1:low power stop mode or |
| 531 | // let cmd mode eng send packets in hs |
| 532 | // or lp mode |
| 533 | unsigned short image_wd = mipi_fb_cfg.width; |
| 534 | unsigned short image_ht = mipi_fb_cfg.height; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 535 | unsigned short display_wd = mipi_fb_cfg.width; |
| 536 | unsigned short display_ht = mipi_fb_cfg.height; |
| 537 | unsigned short hsync_porch_fp = MIPI_HSYNC_FRONT_PORCH_DCLK; |
| 538 | unsigned short hsync_porch_bp = MIPI_HSYNC_BACK_PORCH_DCLK; |
| 539 | unsigned short vsync_porch_fp = MIPI_VSYNC_FRONT_PORCH_LINES; |
| 540 | unsigned short vsync_porch_bp = MIPI_VSYNC_BACK_PORCH_LINES; |
| 541 | unsigned short hsync_width = MIPI_HSYNC_PULSE_WIDTH; |
| 542 | unsigned short vsync_width = MIPI_VSYNC_PULSE_WIDTH; |
| 543 | unsigned short dst_format = 0; |
| 544 | unsigned short traffic_mode = 0; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 545 | unsigned short pack_pattern = 0x12; //BGR |
| 546 | unsigned char ystride = 3; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 547 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 548 | low_pwr_stop_mode = 0x1111; // low pwr mode bit16:HSA, bit20:HBA, |
| 549 | // bit24:HFP, bit28:PULSE MODE, need enough |
| 550 | // time for swithc from LP to HS |
| 551 | eof_bllp_pwr = 0x9; // low power stop mode or let cmd mode eng send |
| 552 | // packets in hs or lp mode |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 553 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 554 | status += |
| 555 | config_dsi_video_mode(display_wd, display_ht, image_wd, image_ht, |
| 556 | hsync_porch_fp, hsync_porch_bp, |
| 557 | vsync_porch_fp, vsync_porch_bp, hsync_width, |
| 558 | vsync_width, dst_format, traffic_mode, |
| 559 | num_of_lanes); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 560 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 561 | status += |
| 562 | mdp_setup_dma_p_video_mode(display_wd, display_ht, image_wd, |
| 563 | image_ht, hsync_porch_fp, hsync_porch_bp, |
| 564 | vsync_porch_fp, vsync_porch_bp, |
| 565 | hsync_width, vsync_width, MIPI_FB_ADDR, |
| 566 | image_wd, pack_pattern, ystride); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 567 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 568 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 569 | while (ReadValue != 0x00010000) { |
| 570 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 571 | count++; |
| 572 | if (count > 0xffff) { |
| 573 | status = FAIL; |
| 574 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 575 | return status; |
| 576 | } |
| 577 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 578 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 579 | dprintf(SPEW, "Video lane tested successfully\n"); |
| 580 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 581 | } |
| 582 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 583 | int is_cmd_mode_enabled(void) |
| 584 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 585 | return cmd_mode_status; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 586 | } |
| 587 | |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 588 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 589 | void mipi_dsi_cmd_mode_trigger(void) |
| 590 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 591 | int status = 0; |
| 592 | unsigned short display_wd = mipi_fb_cfg.width; |
| 593 | unsigned short display_ht = mipi_fb_cfg.height; |
| 594 | unsigned short image_wd = mipi_fb_cfg.width; |
| 595 | unsigned short image_ht = mipi_fb_cfg.height; |
| 596 | unsigned short dst_format = 0; |
| 597 | unsigned short traffic_mode = 0; |
| 598 | struct mipi_dsi_panel_config *panel_info = &novatek_panel_info; |
| 599 | status += mipi_dsi_cmd_config(mipi_fb_cfg, panel_info->num_of_lanes); |
| 600 | mdelay(50); |
| 601 | config_dsi_cmd_mode(display_wd, display_ht, image_wd, image_ht, |
| 602 | dst_format, traffic_mode, |
| 603 | panel_info->num_of_lanes /* num_of_lanes */ ); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 604 | } |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 605 | #endif |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 606 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 607 | void mipi_dsi_shutdown(void) |
| 608 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 609 | if(!target_cont_splash_screen()) |
| 610 | { |
| 611 | mdp_shutdown(); |
| 612 | writel(0x01010101, DSI_INT_CTRL); |
| 613 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 614 | |
| 615 | #if (DISPLAY_MIPI_PANEL_NOVATEK_BLUE \ |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 616 | || DISPLAY_MIPI_PANEL_TOSHIBA) |
| 617 | secure_writel(0x0, DSI_CC_REG); |
| 618 | secure_writel(0x0, DSI_PIXEL_CC_REG); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 619 | #endif |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 620 | |
| 621 | writel(0, DSI_CLK_CTRL); |
| 622 | writel(0, DSI_CTRL); |
| 623 | writel(0, DSIPHY_PLL_CTRL(0)); |
| 624 | } |
| 625 | else |
| 626 | { |
Chandan Uddaraju | 4877d37 | 2011-07-21 12:51:51 -0700 | [diff] [blame] | 627 | /* To keep the splash screen displayed till kernel driver takes |
| 628 | control, do not turn off the video mode engine and clocks. |
| 629 | Only disabling the MIPI DSI IRQs */ |
| 630 | writel(0x01010101, DSI_INT_CTRL); |
| 631 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 632 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 633 | } |
| 634 | |
| 635 | struct fbcon_config *mipi_init(void) |
| 636 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 637 | int status = 0; |
| 638 | struct mipi_dsi_panel_config *panel_info = get_panel_info(); |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 639 | |
| 640 | if (panel_info == NULL) { |
| 641 | dprintf(CRITICAL, "Panel info is null\n"); |
| 642 | return NULL; |
| 643 | } |
| 644 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 645 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for arbiter master0 and master 1 request */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 646 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G) |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 647 | writel(0x00001800, MMSS_SFPB_GPREG); |
Aparna Mallavarapu | f712f5e | 2011-08-04 21:11:00 +0530 | [diff] [blame] | 648 | #endif |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 649 | |
| 650 | #if DISPLAY_MIPI_PANEL_TOSHIBA_MDT61 |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 651 | mipi_dsi_phy_init(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 652 | #else |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 653 | mipi_dsi_phy_ctrl_config(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 654 | #endif |
| 655 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 656 | status += mipi_dsi_panel_initialize(panel_info); |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 657 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 658 | #if DISPLAY_MIPI_PANEL_NOVATEK_BLUE |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 659 | mipi_dsi_cmd_bta_sw_trigger(); |
| 660 | mipi_novatek_manufacture_id(); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 661 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 662 | mipi_fb_cfg.base = MIPI_FB_ADDR; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 663 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 664 | if (panel_info->mode == MIPI_VIDEO_MODE) |
| 665 | status += mipi_dsi_video_config(panel_info->num_of_lanes); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 666 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 667 | if (panel_info->mode == MIPI_CMD_MODE) |
| 668 | cmd_mode_status = 1; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 669 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 670 | return &mipi_fb_cfg; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 671 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 672 | |
| 673 | int mipi_config(struct msm_fb_panel_data *panel) |
| 674 | { |
| 675 | int ret = NO_ERROR; |
| 676 | struct msm_panel_info *pinfo; |
| 677 | struct mipi_dsi_panel_config mipi_pinfo; |
| 678 | |
| 679 | if (!panel) |
| 680 | return ERR_INVALID_ARGS; |
| 681 | |
| 682 | pinfo = &(panel->panel_info); |
| 683 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 684 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 685 | mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db; |
| 686 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 687 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 688 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 689 | mipi_pinfo.pack = 1; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 690 | |
| 691 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for |
| 692 | arbiter master0 and master 1 request */ |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 693 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 694 | writel(0x00001800, MMSS_SFPB_GPREG); |
| 695 | #endif |
| 696 | |
| 697 | mipi_dsi_phy_init(&mipi_pinfo); |
| 698 | |
| 699 | ret += mipi_dsi_panel_initialize(&mipi_pinfo); |
| 700 | |
Channagoud Kadabi | 01c9182 | 2012-06-06 15:53:30 +0530 | [diff] [blame] | 701 | if (pinfo->rotate && panel->rotate) |
| 702 | pinfo->rotate(); |
| 703 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 704 | return ret; |
| 705 | } |
| 706 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame^] | 707 | int mdss_dsi_video_mode_config(uint16_t disp_width, |
| 708 | uint16_t disp_height, |
| 709 | uint16_t img_width, |
| 710 | uint16_t img_height, |
| 711 | uint16_t hsync_porch0_fp, |
| 712 | uint16_t hsync_porch0_bp, |
| 713 | uint16_t vsync_porch0_fp, |
| 714 | uint16_t vsync_porch0_bp, |
| 715 | uint16_t hsync_width, |
| 716 | uint16_t vsync_width, |
| 717 | uint16_t dst_format, |
| 718 | uint16_t traffic_mode, |
| 719 | uint8_t lane_en, |
| 720 | uint16_t low_pwr_stop_mode, |
| 721 | uint8_t eof_bllp_pwr, |
| 722 | uint8_t interleav) |
| 723 | { |
| 724 | |
| 725 | int status = 0; |
| 726 | |
| 727 | /* disable mdp first */ |
| 728 | mdp_disable(); |
| 729 | |
| 730 | writel(0x00000000, DSI_CLK_CTRL); |
| 731 | writel(0x00000000, DSI_CLK_CTRL); |
| 732 | writel(0x00000000, DSI_CLK_CTRL); |
| 733 | writel(0x00000000, DSI_CLK_CTRL); |
| 734 | writel(0x00000002, DSI_CLK_CTRL); |
| 735 | writel(0x00000006, DSI_CLK_CTRL); |
| 736 | writel(0x0000000e, DSI_CLK_CTRL); |
| 737 | writel(0x0000001e, DSI_CLK_CTRL); |
| 738 | writel(0x0000023f, DSI_CLK_CTRL); |
| 739 | |
| 740 | writel(0, DSI_CTRL); |
| 741 | |
| 742 | writel(0, DSI_ERR_INT_MASK0); |
| 743 | |
| 744 | writel(0x02020202, DSI_INT_CTRL); |
| 745 | |
| 746 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
| 747 | DSI_VIDEO_MODE_ACTIVE_H); |
| 748 | |
| 749 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
| 750 | DSI_VIDEO_MODE_ACTIVE_V); |
| 751 | |
| 752 | if (mdp_get_revision() >= MDP_REV_41) { |
| 753 | writel(((disp_height + vsync_porch0_fp |
| 754 | + vsync_porch0_bp - 1) << 16) |
| 755 | | (disp_width + hsync_porch0_fp |
| 756 | + hsync_porch0_bp - 1), |
| 757 | DSI_VIDEO_MODE_TOTAL); |
| 758 | } else { |
| 759 | writel(((disp_height + vsync_porch0_fp |
| 760 | + vsync_porch0_bp) << 16) |
| 761 | | (disp_width + hsync_porch0_fp |
| 762 | + hsync_porch0_bp), |
| 763 | DSI_VIDEO_MODE_TOTAL); |
| 764 | } |
| 765 | |
| 766 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
| 767 | |
| 768 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
| 769 | |
| 770 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
| 771 | |
| 772 | writel(0x0, DSI_EOT_PACKET_CTRL); |
| 773 | |
| 774 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
| 775 | |
| 776 | if (mdp_get_revision() >= MDP_REV_41) { |
| 777 | writel(low_pwr_stop_mode << 16 | |
| 778 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 779 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 780 | } else { |
| 781 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 782 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 783 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 784 | } |
| 785 | |
| 786 | writel(0x3fd08, DSI_HS_TIMER_CTRL); |
| 787 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
| 788 | writel(0x80006711, DSI_CAL_CTRL); |
| 789 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
| 790 | |
| 791 | writel(0x00010100, DSI_INT_CTRL); |
| 792 | writel(0x02010202, DSI_INT_CTRL); |
| 793 | writel(0x02030303, DSI_INT_CTRL); |
| 794 | |
| 795 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
| 796 | | 0x103, DSI_CTRL); |
| 797 | |
| 798 | return status; |
| 799 | } |
| 800 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 801 | int mdss_dsi_config(struct msm_fb_panel_data *panel) |
| 802 | { |
| 803 | int ret = NO_ERROR; |
| 804 | struct msm_panel_info *pinfo; |
| 805 | struct mipi_dsi_panel_config mipi_pinfo; |
| 806 | |
| 807 | if (!panel) |
| 808 | return ERR_INVALID_ARGS; |
| 809 | |
| 810 | pinfo = &(panel->panel_info); |
| 811 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 812 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 813 | mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db; |
| 814 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 815 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
| 816 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
| 817 | mipi_pinfo.pack = 0; |
| 818 | |
| 819 | mdss_dsi_phy_init(&mipi_pinfo); |
| 820 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame^] | 821 | ret += mdss_dsi_panel_initialize(&mipi_pinfo); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 822 | |
| 823 | if (pinfo->rotate && panel->rotate) |
| 824 | pinfo->rotate(); |
| 825 | |
| 826 | return ret; |
| 827 | } |
| 828 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 829 | int mipi_dsi_video_mode_config(unsigned short disp_width, |
| 830 | unsigned short disp_height, |
| 831 | unsigned short img_width, |
| 832 | unsigned short img_height, |
| 833 | unsigned short hsync_porch0_fp, |
| 834 | unsigned short hsync_porch0_bp, |
| 835 | unsigned short vsync_porch0_fp, |
| 836 | unsigned short vsync_porch0_bp, |
| 837 | unsigned short hsync_width, |
| 838 | unsigned short vsync_width, |
| 839 | unsigned short dst_format, |
| 840 | unsigned short traffic_mode, |
| 841 | unsigned char lane_en, |
| 842 | unsigned low_pwr_stop_mode, |
| 843 | unsigned char eof_bllp_pwr, |
| 844 | unsigned char interleav) |
| 845 | { |
| 846 | |
| 847 | int status = 0; |
| 848 | |
| 849 | /* disable mdp first */ |
| 850 | mdp_disable(); |
| 851 | |
| 852 | writel(0x00000000, DSI_CLK_CTRL); |
| 853 | writel(0x00000000, DSI_CLK_CTRL); |
| 854 | writel(0x00000000, DSI_CLK_CTRL); |
| 855 | writel(0x00000000, DSI_CLK_CTRL); |
| 856 | writel(0x00000002, DSI_CLK_CTRL); |
| 857 | writel(0x00000006, DSI_CLK_CTRL); |
| 858 | writel(0x0000000e, DSI_CLK_CTRL); |
| 859 | writel(0x0000001e, DSI_CLK_CTRL); |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 860 | writel(0x0000023f, DSI_CLK_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 861 | |
| 862 | writel(0, DSI_CTRL); |
| 863 | |
| 864 | writel(0, DSI_ERR_INT_MASK0); |
| 865 | |
| 866 | writel(0x02020202, DSI_INT_CTRL); |
| 867 | |
| 868 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
| 869 | DSI_VIDEO_MODE_ACTIVE_H); |
| 870 | |
| 871 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
| 872 | DSI_VIDEO_MODE_ACTIVE_V); |
| 873 | |
| 874 | if (mdp_get_revision() >= MDP_REV_41) { |
| 875 | writel(((disp_height + vsync_porch0_fp |
| 876 | + vsync_porch0_bp - 1) << 16) |
| 877 | | (disp_width + hsync_porch0_fp |
| 878 | + hsync_porch0_bp - 1), |
| 879 | DSI_VIDEO_MODE_TOTAL); |
| 880 | } else { |
| 881 | writel(((disp_height + vsync_porch0_fp |
| 882 | + vsync_porch0_bp) << 16) |
| 883 | | (disp_width + hsync_porch0_fp |
| 884 | + hsync_porch0_bp), |
| 885 | DSI_VIDEO_MODE_TOTAL); |
| 886 | } |
| 887 | |
| 888 | writel((hsync_width << 16) | 0, DSI_VIDEO_MODE_HSYNC); |
| 889 | |
| 890 | writel(0 << 16 | 0, DSI_VIDEO_MODE_VSYNC); |
| 891 | |
| 892 | writel(vsync_width << 16 | 0, DSI_VIDEO_MODE_VSYNC_VPOS); |
| 893 | |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 894 | writel(0x0, DSI_EOT_PACKET_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 895 | |
| 896 | writel(0x00000100, DSI_MISR_VIDEO_CTRL); |
| 897 | |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 898 | if (mdp_get_revision() >= MDP_REV_41) { |
| 899 | writel(low_pwr_stop_mode << 16 | |
| 900 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 901 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 902 | } else { |
| 903 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 904 | eof_bllp_pwr << 12 | traffic_mode << 8 |
| 905 | | dst_format << 4 | 0x0, DSI_VIDEO_MODE_CTRL); |
| 906 | } |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 907 | |
Chandan Uddaraju | eb1decb | 2013-04-23 14:27:49 -0700 | [diff] [blame] | 908 | writel(0x3fd08, DSI_HS_TIMER_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 909 | writel(0x67, DSI_CAL_STRENGTH_CTRL); |
| 910 | writel(0x80006711, DSI_CAL_CTRL); |
| 911 | writel(0x00010100, DSI_MISR_VIDEO_CTRL); |
| 912 | |
| 913 | writel(0x00010100, DSI_INT_CTRL); |
| 914 | writel(0x02010202, DSI_INT_CTRL); |
| 915 | writel(0x02030303, DSI_INT_CTRL); |
| 916 | |
| 917 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
| 918 | | 0x103, DSI_CTRL); |
| 919 | |
| 920 | return status; |
| 921 | } |
| 922 | |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 923 | int mdss_dsi_cmd_mode_config(uint16_t disp_width, |
| 924 | uint16_t disp_height, |
| 925 | uint16_t img_width, |
| 926 | uint16_t img_height, |
| 927 | uint16_t dst_format, |
| 928 | uint16_t traffic_mode) |
| 929 | { |
| 930 | uint8_t DST_FORMAT; |
| 931 | uint8_t TRAFIC_MODE; |
| 932 | uint8_t DLNx_EN; |
| 933 | // video mode data ctrl |
| 934 | int status = 0; |
| 935 | uint8_t interleav = 0; |
| 936 | uint8_t ystride = 0x03; |
| 937 | // disable mdp first |
| 938 | |
| 939 | writel(0x00000000, DSI_CLK_CTRL); |
| 940 | writel(0x00000000, DSI_CLK_CTRL); |
| 941 | writel(0x00000000, DSI_CLK_CTRL); |
| 942 | writel(0x00000000, DSI_CLK_CTRL); |
| 943 | writel(0x00000002, DSI_CLK_CTRL); |
| 944 | writel(0x00000006, DSI_CLK_CTRL); |
| 945 | writel(0x0000000e, DSI_CLK_CTRL); |
| 946 | writel(0x0000001e, DSI_CLK_CTRL); |
| 947 | writel(0x0000023f, DSI_CLK_CTRL); |
| 948 | |
| 949 | writel(0, DSI_CTRL); |
| 950 | |
| 951 | writel(0, DSI_ERR_INT_MASK0); |
| 952 | |
| 953 | writel(0x02020202, DSI_INT_CTRL); |
| 954 | |
| 955 | DST_FORMAT = 8; // RGB888 |
| 956 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
| 957 | |
| 958 | DLNx_EN = 0xf; // 4 lane with clk programming |
| 959 | dprintf(SPEW, "Data Lane: 4 lane\n"); |
| 960 | |
| 961 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 962 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
| 963 | |
| 964 | writel(DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 965 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 966 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 967 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 968 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 969 | writel(img_height << 16 | img_width, |
| 970 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 971 | writel(img_height << 16 | img_width, |
| 972 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 973 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 974 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 975 | DSI_CTRL); |
| 976 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 977 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 978 | |
| 979 | return NO_ERROR; |
| 980 | } |
| 981 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 982 | int mipi_dsi_cmd_mode_config(unsigned short disp_width, |
| 983 | unsigned short disp_height, |
| 984 | unsigned short img_width, |
| 985 | unsigned short img_height, |
| 986 | unsigned short dst_format, |
| 987 | unsigned short traffic_mode) |
| 988 | { |
| 989 | unsigned char DST_FORMAT; |
| 990 | unsigned char TRAFIC_MODE; |
| 991 | unsigned char DLNx_EN; |
| 992 | // video mode data ctrl |
| 993 | int status = 0; |
| 994 | unsigned char interleav = 0; |
| 995 | unsigned char ystride = 0x03; |
| 996 | // disable mdp first |
| 997 | |
| 998 | writel(0x00000000, DSI_CLK_CTRL); |
| 999 | writel(0x00000000, DSI_CLK_CTRL); |
| 1000 | writel(0x00000000, DSI_CLK_CTRL); |
| 1001 | writel(0x00000000, DSI_CLK_CTRL); |
| 1002 | writel(0x00000002, DSI_CLK_CTRL); |
| 1003 | writel(0x00000006, DSI_CLK_CTRL); |
| 1004 | writel(0x0000000e, DSI_CLK_CTRL); |
| 1005 | writel(0x0000001e, DSI_CLK_CTRL); |
| 1006 | writel(0x0000003e, DSI_CLK_CTRL); |
| 1007 | |
| 1008 | writel(0x10000000, DSI_ERR_INT_MASK0); |
| 1009 | |
| 1010 | |
| 1011 | DST_FORMAT = 8; // RGB888 |
| 1012 | dprintf(SPEW, "DSI_Cmd_Mode - Dst Format: RGB888\n"); |
| 1013 | |
| 1014 | DLNx_EN = 3; // 2 lane with clk programming |
| 1015 | dprintf(SPEW, "Data Lane: 2 lane\n"); |
| 1016 | |
| 1017 | TRAFIC_MODE = 0; // non burst mode with sync pulses |
| 1018 | dprintf(SPEW, "Traffic mode: non burst mode with sync pulses\n"); |
| 1019 | |
| 1020 | writel(0x02020202, DSI_INT_CTRL); |
| 1021 | |
| 1022 | writel(0x00100000 | DST_FORMAT, DSI_COMMAND_MODE_MDP_CTRL); |
| 1023 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1024 | DSI_COMMAND_MODE_MDP_STREAM0_CTRL); |
| 1025 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 1026 | DSI_COMMAND_MODE_MDP_STREAM1_CTRL); |
| 1027 | writel(img_height << 16 | img_width, |
| 1028 | DSI_COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 1029 | writel(img_height << 16 | img_width, |
| 1030 | DSI_COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 1031 | writel(0xEE, DSI_CAL_STRENGTH_CTRL); |
| 1032 | writel(0x80000000, DSI_CAL_CTRL); |
| 1033 | writel(0x40, DSI_TRIG_CTRL); |
| 1034 | writel(0x13c2c, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL); |
| 1035 | writel(interleav << 30 | 0 << 24 | 0 << 20 | DLNx_EN << 4 | 0x105, |
| 1036 | DSI_CTRL); |
| 1037 | writel(0x10000000, DSI_COMMAND_MODE_DMA_CTRL); |
| 1038 | writel(0x10000000, DSI_MISR_CMD_CTRL); |
| 1039 | writel(0x00000040, DSI_ERR_INT_MASK0); |
| 1040 | writel(0x1, DSI_EOT_PACKET_CTRL); |
| 1041 | |
| 1042 | return NO_ERROR; |
| 1043 | } |
| 1044 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1045 | int mipi_dsi_on() |
| 1046 | { |
| 1047 | int ret = NO_ERROR; |
| 1048 | unsigned long ReadValue; |
| 1049 | unsigned long count = 0; |
| 1050 | |
| 1051 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 1052 | |
| 1053 | mdelay(10); |
| 1054 | |
| 1055 | while (ReadValue != 0x00010000) { |
| 1056 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 1057 | count++; |
| 1058 | if (count > 0xffff) { |
| 1059 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 1060 | return ERROR; |
| 1061 | } |
| 1062 | } |
| 1063 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 1064 | dprintf(INFO, "Video lane tested successfully\n"); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1065 | return ret; |
| 1066 | } |
| 1067 | |
| 1068 | int mipi_dsi_off() |
| 1069 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 1070 | if(!target_cont_splash_screen()) |
| 1071 | { |
| 1072 | writel(0, DSI_CLK_CTRL); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 1073 | writel(0x1F1, DSI_CTRL); |
| 1074 | writel(0x00000001, DSIPHY_SW_RESET); |
| 1075 | writel(0x00000000, DSIPHY_SW_RESET); |
| 1076 | mdelay(10); |
| 1077 | writel(0x0001, DSI_SOFT_RESET); |
| 1078 | writel(0x0000, DSI_SOFT_RESET); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 1079 | writel(0x1115501, DSI_INT_CTRL); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 1080 | writel(0, DSI_CTRL); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 1081 | } |
| 1082 | |
| 1083 | writel(0x1115501, DSI_INT_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 1084 | |
| 1085 | return NO_ERROR; |
| 1086 | } |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1087 | |
| 1088 | int mipi_cmd_trigger() |
| 1089 | { |
| 1090 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
| 1091 | |
| 1092 | return NO_ERROR; |
| 1093 | } |