Amol Jadi | ead84fc | 2012-07-26 18:24:38 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved. |
Kinson Chik | f1a4351 | 2011-07-14 11:28:39 -0700 | [diff] [blame] | 2 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 28 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 29 | #include <string.h> |
| 30 | #include <stdlib.h> |
| 31 | #include <debug.h> |
| 32 | #include <reg.h> |
| 33 | #include "mmc.h" |
| 34 | #include <partition_parser.h> |
| 35 | #include <platform/iomap.h> |
| 36 | #include <platform/timer.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 37 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 38 | #if MMC_BOOT_ADM |
| 39 | #include "adm.h" |
| 40 | #endif |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 41 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 42 | #if MMC_BOOT_BAM |
| 43 | #include "bam.h" |
| 44 | #include "mmc_dml.h" |
| 45 | #endif |
| 46 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 47 | #ifndef NULL |
| 48 | #define NULL 0 |
| 49 | #endif |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 50 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 51 | #define MMC_BOOT_DATA_READ 0 |
| 52 | #define MMC_BOOT_DATA_WRITE 1 |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 53 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 54 | static unsigned int mmc_boot_data_transfer(unsigned int *data_ptr, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 55 | unsigned int data_len, |
| 56 | unsigned char direction); |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 57 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 58 | static unsigned int mmc_boot_fifo_read(unsigned int *data_ptr, |
| 59 | unsigned int data_len); |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 60 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 61 | static unsigned int mmc_boot_fifo_write(unsigned int *data_ptr, |
| 62 | unsigned int data_len); |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 63 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 64 | static unsigned int mmc_boot_status_error(unsigned mmc_status); |
| 65 | |
| 66 | #if MMC_BOOT_BAM |
| 67 | |
| 68 | void mmc_boot_dml_init(); |
| 69 | |
| 70 | static void mmc_boot_dml_producer_trans_init(unsigned trans_end, |
| 71 | unsigned size); |
| 72 | |
| 73 | static void mmc_boot_dml_consumer_trans_init(); |
| 74 | |
| 75 | static uint32_t mmc_boot_dml_chk_producer_idle(); |
| 76 | |
| 77 | static void mmc_boot_dml_wait_producer_idle(); |
| 78 | static void mmc_boot_dml_wait_consumer_idle(); |
| 79 | static void mmc_boot_dml_reset(); |
| 80 | static int mmc_bam_init(uint32_t bam_base); |
| 81 | static int mmc_bam_transfer_data(); |
| 82 | static unsigned int |
| 83 | mmc_boot_bam_setup_desc(unsigned int *data_ptr, |
| 84 | unsigned int data_len, unsigned char direction); |
| 85 | |
| 86 | |
| 87 | #endif |
| 88 | |
| 89 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 90 | #define ROUND_TO_PAGE(x,y) (((x) + (y)) & (~(y))) |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 91 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 92 | /* data access time unit in ns */ |
| 93 | static const unsigned int taac_unit[] = |
| 94 | { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000 }; |
| 95 | /* data access time value x 10 */ |
| 96 | static const unsigned int taac_value[] = |
| 97 | { 0, 10, 12, 13, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 70, 80 }; |
Greg Grisco | 6e75477 | 2011-06-23 12:19:39 -0700 | [diff] [blame] | 98 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 99 | /* data transfer rate in kbit/s */ |
| 100 | static const unsigned int xfer_rate_unit[] = |
| 101 | { 100, 1000, 10000, 100000, 0, 0, 0, 0 }; |
| 102 | /* data transfer rate value x 10*/ |
| 103 | static const unsigned int xfer_rate_value[] = |
| 104 | { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80 }; |
| 105 | |
| 106 | unsigned char mmc_slot = 0; |
| 107 | unsigned int mmc_boot_mci_base = 0; |
| 108 | |
| 109 | static unsigned char ext_csd_buf[512]; |
| 110 | static unsigned char wp_status_buf[8]; |
| 111 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 112 | #if MMC_BOOT_BAM |
| 113 | |
| 114 | static uint32_t mmc_sdc_bam_base[] = |
| 115 | { MSM_SDC1_BAM_BASE, MSM_SDC2_BAM_BASE, MSM_SDC3_BAM_BASE, MSM_SDC4_BAM_BASE }; |
| 116 | |
| 117 | static uint32_t mmc_sdc_dml_base[] = |
| 118 | { MSM_SDC1_DML_BASE, MSM_SDC2_DML_BASE, MSM_SDC3_DML_BASE, MSM_SDC4_DML_BASE }; |
| 119 | |
| 120 | uint32_t dml_base; |
| 121 | static struct bam_instance bam; |
| 122 | |
| 123 | #define MMC_BOOT_BAM_FIFO_SIZE 100 |
| 124 | |
| 125 | #define MMC_BOOT_BAM_READ_PIPE_INDEX 0 |
| 126 | #define MMC_BOOT_BAM_WRITE_PIPE_INDEX 1 |
| 127 | |
| 128 | #define MMC_BOOT_BAM_READ_PIPE 0 |
| 129 | #define MMC_BOOT_BAM_WRITE_PIPE 1 |
| 130 | |
| 131 | /* Align at BAM_DESC_SIZE boundary */ |
| 132 | static struct bam_desc desc_fifo[MMC_BOOT_BAM_FIFO_SIZE] __attribute__ ((aligned(BAM_DESC_SIZE))); |
| 133 | |
| 134 | #endif |
| 135 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 136 | int mmc_clock_enable_disable(unsigned id, unsigned enable); |
| 137 | int mmc_clock_get_rate(unsigned id); |
| 138 | int mmc_clock_set_rate(unsigned id, unsigned rate); |
| 139 | |
| 140 | struct mmc_boot_host mmc_host; |
| 141 | struct mmc_boot_card mmc_card; |
| 142 | |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 143 | static unsigned int mmc_wp(unsigned int addr, unsigned int size, |
| 144 | unsigned char set_clear_wp); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 145 | static unsigned int mmc_boot_send_ext_cmd(struct mmc_boot_card *card, |
| 146 | unsigned char *buf); |
| 147 | static unsigned int mmc_boot_read_reg(struct mmc_boot_card *card, |
| 148 | unsigned int data_len, |
| 149 | unsigned int command, |
| 150 | unsigned int addr, unsigned int *out); |
| 151 | |
| 152 | unsigned int SWAP_ENDIAN(unsigned int val) |
| 153 | { |
| 154 | return ((val & 0xFF) << 24) | |
| 155 | (((val >> 8) & 0xFF) << 16) | (((val >> 16) & 0xFF) << 8) | (val >> |
| 156 | 24); |
Amol Jadi | 84a546a | 2011-03-02 12:09:11 -0800 | [diff] [blame] | 157 | } |
| 158 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 159 | /* Sets a timeout for read operation. |
| 160 | */ |
| 161 | static unsigned int |
| 162 | mmc_boot_set_read_timeout(struct mmc_boot_host *host, |
| 163 | struct mmc_boot_card *card) |
| 164 | { |
| 165 | unsigned int timeout_ns = 0; |
Neeti Desai | 5f26aff | 2011-09-30 10:27:40 -0700 | [diff] [blame] | 166 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 167 | if ((host == NULL) || (card == NULL)) { |
| 168 | return MMC_BOOT_E_INVAL; |
| 169 | } |
| 170 | |
| 171 | if ((card->type == MMC_BOOT_TYPE_MMCHC) |
| 172 | || (card->type == MMC_BOOT_TYPE_SDHC)) { |
| 173 | card->rd_timeout_ns = 100000000; |
| 174 | } else if ((card->type == MMC_BOOT_TYPE_STD_SD) |
| 175 | || (card->type == MMC_BOOT_TYPE_STD_MMC)) { |
| 176 | timeout_ns = 10 * ((card->csd.taac_ns) + |
| 177 | (card->csd.nsac_clk_cycle / |
| 178 | (host->mclk_rate / 1000000000))); |
| 179 | card->rd_timeout_ns = timeout_ns; |
| 180 | } else { |
| 181 | return MMC_BOOT_E_NOT_SUPPORTED; |
| 182 | } |
| 183 | |
| 184 | dprintf(SPEW, " Read timeout set: %d ns\n", card->rd_timeout_ns); |
| 185 | |
| 186 | return MMC_BOOT_E_SUCCESS; |
Neeti Desai | 5f26aff | 2011-09-30 10:27:40 -0700 | [diff] [blame] | 187 | } |
| 188 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 189 | /* Sets a timeout for write operation. |
| 190 | */ |
| 191 | static unsigned int |
| 192 | mmc_boot_set_write_timeout(struct mmc_boot_host *host, |
| 193 | struct mmc_boot_card *card) |
| 194 | { |
| 195 | unsigned int timeout_ns = 0; |
| 196 | |
| 197 | if ((host == NULL) || (card == NULL)) { |
| 198 | return MMC_BOOT_E_INVAL; |
| 199 | } |
| 200 | |
| 201 | if ((card->type == MMC_BOOT_TYPE_MMCHC) |
| 202 | || (card->type == MMC_BOOT_TYPE_SDHC)) { |
| 203 | card->wr_timeout_ns = 100000000; |
| 204 | } else if (card->type == MMC_BOOT_TYPE_STD_SD |
| 205 | || (card->type == MMC_BOOT_TYPE_STD_MMC)) { |
| 206 | timeout_ns = 10 * ((card->csd.taac_ns) + |
| 207 | (card->csd.nsac_clk_cycle / |
| 208 | (host->mclk_rate / 1000000000))); |
| 209 | timeout_ns = timeout_ns << card->csd.r2w_factor; |
| 210 | card->wr_timeout_ns = timeout_ns; |
| 211 | } else { |
| 212 | return MMC_BOOT_E_NOT_SUPPORTED; |
| 213 | } |
| 214 | |
| 215 | dprintf(SPEW, " Write timeout set: %d ns\n", card->wr_timeout_ns); |
| 216 | |
| 217 | return MMC_BOOT_E_SUCCESS; |
| 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Decodes CSD response received from the card. Note that we have defined only |
| 222 | * few of the CSD elements in csd structure. We'll only decode those values. |
| 223 | */ |
| 224 | static unsigned int |
| 225 | mmc_boot_decode_and_save_csd(struct mmc_boot_card *card, unsigned int *raw_csd) |
| 226 | { |
| 227 | unsigned int mmc_sizeof = 0; |
| 228 | unsigned int mmc_unit = 0; |
| 229 | unsigned int mmc_value = 0; |
| 230 | unsigned int mmc_temp = 0; |
| 231 | |
| 232 | struct mmc_boot_csd mmc_csd; |
| 233 | |
| 234 | if ((card == NULL) || (raw_csd == NULL)) { |
| 235 | return MMC_BOOT_E_INVAL; |
| 236 | } |
| 237 | |
| 238 | mmc_sizeof = sizeof(unsigned int) * 8; |
| 239 | |
| 240 | mmc_csd.cmmc_structure = UNPACK_BITS(raw_csd, 126, 2, mmc_sizeof); |
| 241 | |
| 242 | if ((card->type == MMC_BOOT_TYPE_SDHC) |
| 243 | || (card->type == MMC_BOOT_TYPE_STD_SD)) { |
| 244 | /* Parse CSD according to SD card spec. */ |
| 245 | |
| 246 | /* CSD register is little bit differnet for CSD version 2.0 High Capacity |
| 247 | * and CSD version 1.0/2.0 Standard memory cards. In Version 2.0 some of |
| 248 | * the fields have fixed values and it's not necessary for host to refer |
| 249 | * these fields in CSD sent by card */ |
| 250 | |
| 251 | if (mmc_csd.cmmc_structure == 1) { |
| 252 | /* CSD Version 2.0 */ |
| 253 | mmc_csd.card_cmd_class = |
| 254 | UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); |
| 255 | mmc_csd.write_blk_len = 512; /* Fixed value is 9 = 2^9 = 512 */ |
| 256 | mmc_csd.read_blk_len = 512; /* Fixed value is 9 = 512 */ |
| 257 | mmc_csd.r2w_factor = 0x2; /* Fixed value: 010b */ |
| 258 | mmc_csd.c_size_mult = 0; /* not there in version 2.0 */ |
| 259 | mmc_csd.c_size = |
| 260 | UNPACK_BITS(raw_csd, 48, 22, mmc_sizeof); |
| 261 | mmc_csd.nsac_clk_cycle = |
| 262 | UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; |
| 263 | |
| 264 | //TODO: Investigate the nsac and taac. Spec suggests not using this for timeouts. |
| 265 | |
| 266 | mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); |
| 267 | mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); |
| 268 | mmc_csd.taac_ns = |
| 269 | (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; |
| 270 | |
| 271 | mmc_csd.erase_blk_len = 1; |
| 272 | mmc_csd.read_blk_misalign = 0; |
| 273 | mmc_csd.write_blk_misalign = 0; |
| 274 | mmc_csd.read_blk_partial = 0; |
| 275 | mmc_csd.write_blk_partial = 0; |
| 276 | |
| 277 | mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof); |
| 278 | mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof); |
| 279 | mmc_csd.tran_speed = |
| 280 | (xfer_rate_value[mmc_value] * |
| 281 | xfer_rate_unit[mmc_unit]) / 10; |
| 282 | |
| 283 | mmc_csd.wp_grp_size = 0x0; |
| 284 | mmc_csd.wp_grp_enable = 0x0; |
| 285 | mmc_csd.perm_wp = |
| 286 | UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); |
| 287 | mmc_csd.temp_wp = |
| 288 | UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); |
| 289 | |
| 290 | /* Calculate the card capcity */ |
| 291 | card->capacity = (1 + mmc_csd.c_size) * 512 * 1024; |
| 292 | } else { |
| 293 | /* CSD Version 1.0 */ |
| 294 | mmc_csd.card_cmd_class = |
| 295 | UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); |
| 296 | |
| 297 | mmc_temp = UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof); |
| 298 | mmc_csd.write_blk_len = (mmc_temp > 8 |
| 299 | && mmc_temp < |
| 300 | 12) ? (1 << mmc_temp) : 512; |
| 301 | |
| 302 | mmc_temp = UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof); |
| 303 | mmc_csd.read_blk_len = (mmc_temp > 8 |
| 304 | && mmc_temp < |
| 305 | 12) ? (1 << mmc_temp) : 512; |
| 306 | |
| 307 | mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); |
| 308 | mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); |
| 309 | mmc_csd.taac_ns = |
| 310 | (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; |
| 311 | |
| 312 | mmc_unit = UNPACK_BITS(raw_csd, 96, 3, mmc_sizeof); |
| 313 | mmc_value = UNPACK_BITS(raw_csd, 99, 4, mmc_sizeof); |
| 314 | mmc_csd.tran_speed = |
| 315 | (xfer_rate_value[mmc_value] * |
| 316 | xfer_rate_unit[mmc_unit]) / 10; |
| 317 | |
| 318 | mmc_csd.nsac_clk_cycle = |
| 319 | UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; |
| 320 | |
| 321 | mmc_csd.r2w_factor = |
| 322 | UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof); |
| 323 | mmc_csd.sector_size = |
| 324 | UNPACK_BITS(raw_csd, 39, 7, mmc_sizeof) + 1; |
| 325 | |
| 326 | mmc_csd.erase_blk_len = |
| 327 | UNPACK_BITS(raw_csd, 46, 1, mmc_sizeof); |
| 328 | mmc_csd.read_blk_misalign = |
| 329 | UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof); |
| 330 | mmc_csd.write_blk_misalign = |
| 331 | UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof); |
| 332 | mmc_csd.read_blk_partial = |
| 333 | UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof); |
| 334 | mmc_csd.write_blk_partial = |
| 335 | UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof); |
| 336 | |
| 337 | mmc_csd.c_size_mult = |
| 338 | UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof); |
| 339 | mmc_csd.c_size = |
| 340 | UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof); |
| 341 | mmc_csd.wp_grp_size = |
| 342 | UNPACK_BITS(raw_csd, 32, 7, mmc_sizeof); |
| 343 | mmc_csd.wp_grp_enable = |
| 344 | UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof); |
| 345 | mmc_csd.perm_wp = |
| 346 | UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); |
| 347 | mmc_csd.temp_wp = |
| 348 | UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); |
| 349 | |
| 350 | /* Calculate the card capacity */ |
| 351 | mmc_temp = |
| 352 | (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + |
| 353 | 1); |
| 354 | card->capacity = mmc_temp * mmc_csd.read_blk_len; |
| 355 | } |
| 356 | } else { |
| 357 | /* Parse CSD according to MMC card spec. */ |
| 358 | mmc_csd.spec_vers = UNPACK_BITS(raw_csd, 122, 4, mmc_sizeof); |
| 359 | mmc_csd.card_cmd_class = |
| 360 | UNPACK_BITS(raw_csd, 84, 12, mmc_sizeof); |
| 361 | mmc_csd.write_blk_len = |
| 362 | 1 << UNPACK_BITS(raw_csd, 22, 4, mmc_sizeof); |
| 363 | mmc_csd.read_blk_len = |
| 364 | 1 << UNPACK_BITS(raw_csd, 80, 4, mmc_sizeof); |
| 365 | mmc_csd.r2w_factor = UNPACK_BITS(raw_csd, 26, 3, mmc_sizeof); |
| 366 | mmc_csd.c_size_mult = UNPACK_BITS(raw_csd, 47, 3, mmc_sizeof); |
| 367 | mmc_csd.c_size = UNPACK_BITS(raw_csd, 62, 12, mmc_sizeof); |
| 368 | mmc_csd.nsac_clk_cycle = |
| 369 | UNPACK_BITS(raw_csd, 104, 8, mmc_sizeof) * 100; |
| 370 | |
| 371 | mmc_unit = UNPACK_BITS(raw_csd, 112, 3, mmc_sizeof); |
| 372 | mmc_value = UNPACK_BITS(raw_csd, 115, 4, mmc_sizeof); |
| 373 | mmc_csd.taac_ns = |
| 374 | (taac_value[mmc_value] * taac_unit[mmc_unit]) / 10; |
| 375 | |
| 376 | mmc_csd.read_blk_misalign = |
| 377 | UNPACK_BITS(raw_csd, 77, 1, mmc_sizeof); |
| 378 | mmc_csd.write_blk_misalign = |
| 379 | UNPACK_BITS(raw_csd, 78, 1, mmc_sizeof); |
| 380 | mmc_csd.read_blk_partial = |
| 381 | UNPACK_BITS(raw_csd, 79, 1, mmc_sizeof); |
| 382 | mmc_csd.write_blk_partial = |
| 383 | UNPACK_BITS(raw_csd, 21, 1, mmc_sizeof); |
| 384 | mmc_csd.tran_speed = 0x00; /* Ignore -- no use of this value. */ |
| 385 | |
| 386 | mmc_csd.erase_grp_size = |
| 387 | UNPACK_BITS(raw_csd, 42, 5, mmc_sizeof); |
| 388 | mmc_csd.erase_grp_mult = |
| 389 | UNPACK_BITS(raw_csd, 37, 5, mmc_sizeof); |
| 390 | mmc_csd.wp_grp_size = UNPACK_BITS(raw_csd, 32, 5, mmc_sizeof); |
| 391 | mmc_csd.wp_grp_enable = UNPACK_BITS(raw_csd, 31, 1, mmc_sizeof); |
| 392 | mmc_csd.perm_wp = UNPACK_BITS(raw_csd, 13, 1, mmc_sizeof); |
| 393 | mmc_csd.temp_wp = UNPACK_BITS(raw_csd, 12, 1, mmc_sizeof); |
| 394 | |
| 395 | /* Calculate the card capcity */ |
| 396 | if (mmc_csd.c_size != 0xFFF) { |
| 397 | /* For cards less than or equal to 2GB */ |
| 398 | mmc_temp = |
| 399 | (1 << (mmc_csd.c_size_mult + 2)) * (mmc_csd.c_size + |
| 400 | 1); |
| 401 | card->capacity = mmc_temp * mmc_csd.read_blk_len; |
| 402 | } else { |
| 403 | /* For cards greater than 2GB, Ext CSD register's SEC_COUNT |
| 404 | * is used to calculate the size. |
| 405 | */ |
| 406 | unsigned long long sec_count; |
| 407 | |
| 408 | sec_count = (ext_csd_buf[215] << 24) | |
| 409 | (ext_csd_buf[214] << 16) | |
| 410 | (ext_csd_buf[213] << 8) | ext_csd_buf[212]; |
| 411 | |
| 412 | card->capacity = sec_count * 512; |
| 413 | } |
| 414 | } |
| 415 | |
| 416 | /* save the information in card structure */ |
| 417 | memcpy((struct mmc_boot_csd *)&card->csd, |
| 418 | (struct mmc_boot_csd *)&mmc_csd, sizeof(struct mmc_boot_csd)); |
| 419 | |
| 420 | dprintf(SPEW, "Decoded CSD fields:\n"); |
| 421 | dprintf(SPEW, "cmmc_structure: %d\n", mmc_csd.cmmc_structure); |
| 422 | dprintf(SPEW, "card_cmd_class: %x\n", mmc_csd.card_cmd_class); |
| 423 | dprintf(SPEW, "write_blk_len: %d\n", mmc_csd.write_blk_len); |
| 424 | dprintf(SPEW, "read_blk_len: %d\n", mmc_csd.read_blk_len); |
| 425 | dprintf(SPEW, "r2w_factor: %d\n", mmc_csd.r2w_factor); |
| 426 | dprintf(SPEW, "sector_size: %d\n", mmc_csd.sector_size); |
| 427 | dprintf(SPEW, "c_size_mult:%d\n", mmc_csd.c_size_mult); |
| 428 | dprintf(SPEW, "c_size: %d\n", mmc_csd.c_size); |
| 429 | dprintf(SPEW, "nsac_clk_cycle: %d\n", mmc_csd.nsac_clk_cycle); |
| 430 | dprintf(SPEW, "taac_ns: %d\n", mmc_csd.taac_ns); |
| 431 | dprintf(SPEW, "tran_speed: %d kbps\n", mmc_csd.tran_speed); |
| 432 | dprintf(SPEW, "erase_blk_len: %d\n", mmc_csd.erase_blk_len); |
| 433 | dprintf(SPEW, "read_blk_misalign: %d\n", mmc_csd.read_blk_misalign); |
| 434 | dprintf(SPEW, "write_blk_misalign: %d\n", mmc_csd.write_blk_misalign); |
| 435 | dprintf(SPEW, "read_blk_partial: %d\n", mmc_csd.read_blk_partial); |
| 436 | dprintf(SPEW, "write_blk_partial: %d\n", mmc_csd.write_blk_partial); |
| 437 | dprintf(SPEW, "Card Capacity: %llu Bytes\n", card->capacity); |
| 438 | |
| 439 | return MMC_BOOT_E_SUCCESS; |
| 440 | } |
| 441 | |
| 442 | /* |
| 443 | * Decode CID sent by the card. |
| 444 | */ |
| 445 | static unsigned int |
| 446 | mmc_boot_decode_and_save_cid(struct mmc_boot_card *card, unsigned int *raw_cid) |
| 447 | { |
| 448 | struct mmc_boot_cid mmc_cid; |
| 449 | unsigned int mmc_sizeof = 0; |
| 450 | int i = 0; |
| 451 | |
| 452 | if ((card == NULL) || (raw_cid == NULL)) { |
| 453 | return MMC_BOOT_E_INVAL; |
| 454 | } |
| 455 | |
| 456 | mmc_sizeof = sizeof(unsigned int) * 8; |
| 457 | |
| 458 | if ((card->type == MMC_BOOT_TYPE_SDHC) |
| 459 | || (card->type == MMC_BOOT_TYPE_STD_SD)) { |
| 460 | mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof); |
| 461 | mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof); |
| 462 | |
| 463 | for (i = 0; i < 5; i++) { |
| 464 | mmc_cid.pnm[i] = (unsigned char)UNPACK_BITS(raw_cid, |
| 465 | (104 - |
| 466 | 8 * (i + |
| 467 | 1)), |
| 468 | 8, |
| 469 | mmc_sizeof); |
| 470 | } |
| 471 | mmc_cid.pnm[5] = 0; |
| 472 | mmc_cid.pnm[6] = 0; |
| 473 | |
| 474 | mmc_cid.prv = UNPACK_BITS(raw_cid, 56, 8, mmc_sizeof); |
| 475 | mmc_cid.psn = UNPACK_BITS(raw_cid, 24, 32, mmc_sizeof); |
| 476 | mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof); |
| 477 | mmc_cid.year = UNPACK_BITS(raw_cid, 12, 8, mmc_sizeof); |
| 478 | mmc_cid.year += 2000; |
| 479 | } else { |
| 480 | mmc_cid.mid = UNPACK_BITS(raw_cid, 120, 8, mmc_sizeof); |
| 481 | mmc_cid.oid = UNPACK_BITS(raw_cid, 104, 16, mmc_sizeof); |
| 482 | |
| 483 | for (i = 0; i < 6; i++) { |
| 484 | mmc_cid.pnm[i] = (unsigned char)UNPACK_BITS(raw_cid, |
| 485 | (104 - |
| 486 | 8 * (i + |
| 487 | 1)), |
| 488 | 8, |
| 489 | mmc_sizeof); |
| 490 | } |
| 491 | mmc_cid.pnm[6] = 0; |
| 492 | |
| 493 | mmc_cid.prv = UNPACK_BITS(raw_cid, 48, 8, mmc_sizeof); |
| 494 | mmc_cid.psn = UNPACK_BITS(raw_cid, 16, 32, mmc_sizeof); |
| 495 | mmc_cid.month = UNPACK_BITS(raw_cid, 8, 4, mmc_sizeof); |
| 496 | mmc_cid.year = UNPACK_BITS(raw_cid, 12, 4, mmc_sizeof); |
| 497 | mmc_cid.year += 1997; |
| 498 | } |
| 499 | |
| 500 | /* save it in card database */ |
| 501 | memcpy((struct mmc_boot_cid *)&card->cid, |
| 502 | (struct mmc_boot_cid *)&mmc_cid, sizeof(struct mmc_boot_cid)); |
| 503 | |
| 504 | dprintf(SPEW, "Decoded CID fields:\n"); |
| 505 | dprintf(SPEW, "Manufacturer ID: %x\n", mmc_cid.mid); |
| 506 | dprintf(SPEW, "OEM ID: 0x%x\n", mmc_cid.oid); |
| 507 | dprintf(SPEW, "Product Name: %s\n", mmc_cid.pnm); |
| 508 | dprintf(SPEW, "Product revision: %d.%d\n", (mmc_cid.prv >> 4), |
| 509 | (mmc_cid.prv & 0xF)); |
| 510 | dprintf(SPEW, "Product serial number: %X\n", mmc_cid.psn); |
| 511 | dprintf(SPEW, "Manufacturing date: %d %d\n", mmc_cid.month, |
| 512 | mmc_cid.year); |
| 513 | |
| 514 | return MMC_BOOT_E_SUCCESS; |
| 515 | } |
| 516 | |
| 517 | /* |
| 518 | * Sends specified command to a card and waits for a response. |
| 519 | */ |
| 520 | static unsigned int mmc_boot_send_command(struct mmc_boot_command *cmd) |
| 521 | { |
| 522 | unsigned int mmc_cmd = 0; |
| 523 | unsigned int mmc_status = 0; |
| 524 | unsigned int mmc_resp = 0; |
| 525 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 526 | unsigned int cmd_index = 0; |
| 527 | int i = 0; |
| 528 | |
| 529 | /* basic check */ |
| 530 | if (cmd == NULL) { |
| 531 | return MMC_BOOT_E_INVAL; |
| 532 | } |
| 533 | |
| 534 | /* 1. Write command argument to MMC_BOOT_MCI_ARGUMENT register */ |
| 535 | writel(cmd->argument, MMC_BOOT_MCI_ARGUMENT); |
| 536 | |
| 537 | /* Writes to MCI port are not effective for 3 ticks of PCLK. |
| 538 | * The min pclk is 144KHz which gives 6.94 us/tick. |
| 539 | * Thus 21us == 3 ticks. |
| 540 | */ |
| 541 | udelay(21); |
| 542 | |
| 543 | /* 2. Set appropriate fields and write MMC_BOOT_MCI_CMD */ |
| 544 | /* 2a. Write command index in CMD_INDEX field */ |
| 545 | cmd_index = cmd->cmd_index; |
| 546 | mmc_cmd |= cmd->cmd_index; |
| 547 | /* 2b. Set RESPONSE bit to 1 for all cmds except CMD0 */ |
| 548 | if (cmd_index != CMD0_GO_IDLE_STATE) { |
| 549 | mmc_cmd |= MMC_BOOT_MCI_CMD_RESPONSE; |
| 550 | } |
| 551 | |
| 552 | /* 2c. Set LONGRESP bit to 1 for CMD2, CMD9 and CMD10 */ |
| 553 | if (IS_RESP_136_BITS(cmd->resp_type)) { |
| 554 | mmc_cmd |= MMC_BOOT_MCI_CMD_LONGRSP; |
| 555 | } |
| 556 | |
| 557 | /* 2d. Set INTERRUPT bit to 1 to disable command timeout */ |
| 558 | |
| 559 | /* 2e. Set PENDING bit to 1 for CMD12 in the beginning of stream |
| 560 | mode data transfer */ |
| 561 | if (cmd->xfer_mode == MMC_BOOT_XFER_MODE_STREAM) { |
| 562 | mmc_cmd |= MMC_BOOT_MCI_CMD_PENDING; |
| 563 | } |
| 564 | |
| 565 | /* 2f. Set ENABLE bit to 1 */ |
| 566 | mmc_cmd |= MMC_BOOT_MCI_CMD_ENABLE; |
| 567 | |
| 568 | /* 2g. Set PROG_ENA bit to 1 for CMD12, CMD13 issued at the end of |
| 569 | write data transfer */ |
| 570 | if ((cmd_index == CMD12_STOP_TRANSMISSION || |
| 571 | cmd_index == CMD13_SEND_STATUS) && cmd->prg_enabled) { |
| 572 | mmc_cmd |= MMC_BOOT_MCI_CMD_PROG_ENA; |
| 573 | } |
| 574 | |
| 575 | /* 2h. Set MCIABORT bit to 1 for CMD12 when working with SDIO card */ |
| 576 | /* 2i. Set CCS_ENABLE bit to 1 for CMD61 when Command Completion Signal |
| 577 | of CE-ATA device is enabled */ |
| 578 | |
| 579 | /* 2j. clear all static status bits */ |
| 580 | writel(MMC_BOOT_MCI_STATIC_STATUS, MMC_BOOT_MCI_CLEAR); |
| 581 | |
| 582 | /* 2k. Write to MMC_BOOT_MCI_CMD register */ |
| 583 | writel(mmc_cmd, MMC_BOOT_MCI_CMD); |
| 584 | |
| 585 | dprintf(SPEW, "Command sent: CMD%d MCI_CMD_REG:%x MCI_ARG:%x\n", |
| 586 | cmd_index, mmc_cmd, cmd->argument); |
| 587 | |
| 588 | /* 3. Wait for interrupt or poll on the following bits of MCI_STATUS |
| 589 | register */ |
| 590 | do { |
| 591 | /* 3a. Read MCI_STATUS register */ |
| 592 | while (readl(MMC_BOOT_MCI_STATUS) & |
| 593 | MMC_BOOT_MCI_STAT_CMD_ACTIVE) ; |
| 594 | |
| 595 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 596 | |
| 597 | /* 3b. CMD_SENT bit supposed to be set to 1 only after CMD0 is sent - |
| 598 | no response required. */ |
| 599 | if ((cmd->resp_type == MMC_BOOT_RESP_NONE) && |
| 600 | (mmc_status & MMC_BOOT_MCI_STAT_CMD_SENT)) { |
| 601 | break; |
| 602 | } |
| 603 | |
| 604 | /* 3c. If CMD_TIMEOUT bit is set then no response was received */ |
| 605 | else if (mmc_status & MMC_BOOT_MCI_STAT_CMD_TIMEOUT) { |
| 606 | mmc_return = MMC_BOOT_E_TIMEOUT; |
| 607 | break; |
| 608 | } |
| 609 | /* 3d. If CMD_RESPONSE_END bit is set to 1 then command's response was |
| 610 | received and CRC check passed |
| 611 | Spcial case for ACMD41: it seems to always fail CRC even if |
| 612 | the response is valid |
| 613 | */ |
| 614 | else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_RESP_END) |
| 615 | || (cmd_index == CMD1_SEND_OP_COND) |
| 616 | || (cmd_index == CMD8_SEND_IF_COND)) { |
| 617 | /* 3i. Read MCI_RESP_CMD register to verify that response index is |
| 618 | equal to command index */ |
| 619 | mmc_resp = readl(MMC_BOOT_MCI_RESP_CMD) & 0x3F; |
| 620 | |
| 621 | /* However, long response does not contain the command index field. |
| 622 | * In that case, response index field must be set to 111111b (0x3F) */ |
| 623 | if ((mmc_resp == cmd_index) || |
| 624 | (cmd->resp_type == MMC_BOOT_RESP_R2 || |
| 625 | cmd->resp_type == MMC_BOOT_RESP_R3 || |
| 626 | cmd->resp_type == MMC_BOOT_RESP_R6 || |
| 627 | cmd->resp_type == MMC_BOOT_RESP_R7)) { |
| 628 | /* 3j. If resp index is equal to cmd index, read command resp |
| 629 | from MCI_RESPn registers |
| 630 | - MCI_RESP0/1/2/3 for CMD2/9/10 |
| 631 | - MCI_RESP0 for all other registers */ |
| 632 | if (IS_RESP_136_BITS(cmd->resp_type)) { |
| 633 | for (i = 0; i < 4; i++) { |
| 634 | cmd->resp[3 - i] = |
| 635 | readl(MMC_BOOT_MCI_RESP_0 + |
| 636 | (i * 4)); |
| 637 | |
| 638 | } |
| 639 | } else { |
| 640 | cmd->resp[0] = |
| 641 | readl(MMC_BOOT_MCI_RESP_0); |
| 642 | } |
| 643 | } else { |
| 644 | /* command index mis-match */ |
| 645 | mmc_return = MMC_BOOT_E_CMD_INDX_MISMATCH; |
| 646 | } |
| 647 | |
| 648 | dprintf(SPEW, "Command response received: %X\n", |
| 649 | cmd->resp[0]); |
| 650 | break; |
| 651 | } |
| 652 | |
| 653 | /* 3e. If CMD_CRC_FAIL bit is set to 1 then cmd's response was recvd, |
| 654 | but CRC check failed. */ |
| 655 | else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_CRC_FAIL)) { |
| 656 | if (cmd_index == ACMD41_SEND_OP_COND) { |
| 657 | cmd->resp[0] = readl(MMC_BOOT_MCI_RESP_0); |
| 658 | } else |
| 659 | mmc_return = MMC_BOOT_E_CRC_FAIL; |
| 660 | break; |
| 661 | } |
| 662 | |
| 663 | } |
| 664 | while (1); |
| 665 | |
| 666 | return mmc_return; |
| 667 | } |
| 668 | |
| 669 | /* |
| 670 | * Reset all the cards to idle condition (CMD 0) |
| 671 | */ |
| 672 | static unsigned int mmc_boot_reset_cards(void) |
| 673 | { |
| 674 | struct mmc_boot_command cmd; |
| 675 | |
| 676 | memset((struct mmc_boot_command *)&cmd, 0, |
| 677 | sizeof(struct mmc_boot_command)); |
| 678 | |
| 679 | cmd.cmd_index = CMD0_GO_IDLE_STATE; |
| 680 | cmd.argument = 0; // stuff bits - ignored |
| 681 | cmd.cmd_type = MMC_BOOT_CMD_BCAST; |
| 682 | cmd.resp_type = MMC_BOOT_RESP_NONE; |
| 683 | |
| 684 | /* send command */ |
| 685 | return mmc_boot_send_command(&cmd); |
| 686 | } |
| 687 | |
| 688 | /* |
| 689 | * Send CMD1 to know whether the card supports host VDD profile or not. |
| 690 | */ |
| 691 | static unsigned int |
| 692 | mmc_boot_send_op_cond(struct mmc_boot_host *host, struct mmc_boot_card *card) |
| 693 | { |
| 694 | struct mmc_boot_command cmd; |
| 695 | unsigned int mmc_resp = 0; |
| 696 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 697 | |
| 698 | /* basic check */ |
| 699 | if ((host == NULL) || (card == NULL)) { |
| 700 | return MMC_BOOT_E_INVAL; |
| 701 | } |
| 702 | |
| 703 | memset((struct mmc_boot_command *)&cmd, 0, |
| 704 | sizeof(struct mmc_boot_command)); |
| 705 | |
| 706 | /* CMD1 format: |
| 707 | * [31] Busy bit |
| 708 | * [30:29] Access mode |
| 709 | * [28:24] reserved |
| 710 | * [23:15] 2.7-3.6 |
| 711 | * [14:8] 2.0-2.6 |
| 712 | * [7] 1.7-1.95 |
| 713 | * [6:0] reserved |
| 714 | */ |
| 715 | |
| 716 | cmd.cmd_index = CMD1_SEND_OP_COND; |
| 717 | cmd.argument = host->ocr; |
| 718 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 719 | cmd.resp_type = MMC_BOOT_RESP_R3; |
| 720 | |
| 721 | mmc_ret = mmc_boot_send_command(&cmd); |
| 722 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 723 | return mmc_ret; |
| 724 | } |
| 725 | |
| 726 | /* Now it's time to examine response */ |
| 727 | mmc_resp = cmd.resp[0]; |
| 728 | |
| 729 | /* Response contains card's ocr. Update card's information */ |
| 730 | card->ocr = mmc_resp; |
| 731 | |
| 732 | /* Check the response for busy status */ |
| 733 | if (!(mmc_resp & MMC_BOOT_OCR_BUSY)) { |
| 734 | return MMC_BOOT_E_CARD_BUSY; |
| 735 | } |
| 736 | |
| 737 | if (mmc_resp & MMC_BOOT_OCR_SEC_MODE) { |
| 738 | card->type = MMC_BOOT_TYPE_MMCHC; |
| 739 | } else { |
| 740 | card->type = MMC_BOOT_TYPE_STD_MMC; |
| 741 | } |
| 742 | return MMC_BOOT_E_SUCCESS; |
| 743 | } |
| 744 | |
| 745 | /* |
| 746 | * Request any card to send its uniquie card identification (CID) number (CMD2). |
| 747 | */ |
| 748 | static unsigned int mmc_boot_all_send_cid(struct mmc_boot_card *card) |
| 749 | { |
| 750 | struct mmc_boot_command cmd; |
| 751 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 752 | |
| 753 | /* basic check */ |
| 754 | if (card == NULL) { |
| 755 | return MMC_BOOT_E_INVAL; |
| 756 | } |
| 757 | |
| 758 | memset((struct mmc_boot_command *)&cmd, 0, |
| 759 | sizeof(struct mmc_boot_command)); |
| 760 | |
| 761 | /* CMD2 Format: |
| 762 | * [31:0] stuff bits |
| 763 | */ |
| 764 | cmd.cmd_index = CMD2_ALL_SEND_CID; |
| 765 | cmd.argument = 0; |
| 766 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 767 | cmd.resp_type = MMC_BOOT_RESP_R2; |
| 768 | |
| 769 | /* send command */ |
| 770 | mmc_ret = mmc_boot_send_command(&cmd); |
| 771 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 772 | return mmc_ret; |
| 773 | } |
| 774 | |
| 775 | /* Response contains card's 128 bits CID register */ |
| 776 | mmc_ret = mmc_boot_decode_and_save_cid(card, cmd.resp); |
| 777 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 778 | return mmc_ret; |
| 779 | } |
| 780 | return MMC_BOOT_E_SUCCESS; |
| 781 | } |
| 782 | |
| 783 | /* |
| 784 | * Ask any card to send it's relative card address (RCA).This RCA number is |
| 785 | * shorter than CID and is used by the host to address the card in future (CMD3) |
| 786 | */ |
| 787 | static unsigned int mmc_boot_send_relative_address(struct mmc_boot_card *card) |
| 788 | { |
| 789 | struct mmc_boot_command cmd; |
| 790 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 791 | |
| 792 | /* basic check */ |
| 793 | if (card == NULL) { |
| 794 | return MMC_BOOT_E_INVAL; |
| 795 | } |
| 796 | |
| 797 | memset((struct mmc_boot_command *)&cmd, 0, |
| 798 | sizeof(struct mmc_boot_command)); |
| 799 | |
| 800 | /* CMD3 Format: |
| 801 | * [31:0] stuff bits |
| 802 | */ |
| 803 | if (card->type == MMC_BOOT_TYPE_SDHC |
| 804 | || card->type == MMC_BOOT_TYPE_STD_SD) { |
| 805 | cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR; |
| 806 | cmd.argument = 0; |
| 807 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 808 | cmd.resp_type = MMC_BOOT_RESP_R6; |
| 809 | |
| 810 | /* send command */ |
| 811 | mmc_ret = mmc_boot_send_command(&cmd); |
| 812 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 813 | return mmc_ret; |
| 814 | } |
| 815 | /* For sD, card will send RCA. Store it */ |
| 816 | card->rca = (cmd.resp[0] >> 16); |
| 817 | } else { |
| 818 | cmd.cmd_index = CMD3_SEND_RELATIVE_ADDR; |
| 819 | cmd.argument = (MMC_RCA << 16); |
| 820 | card->rca = (cmd.argument >> 16); |
| 821 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 822 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 823 | |
| 824 | /* send command */ |
| 825 | mmc_ret = mmc_boot_send_command(&cmd); |
| 826 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 827 | return mmc_ret; |
| 828 | } |
| 829 | } |
| 830 | |
| 831 | return MMC_BOOT_E_SUCCESS; |
| 832 | } |
| 833 | |
| 834 | /* |
| 835 | * Requests card to send it's CSD register's contents. (CMD9) |
| 836 | */ |
| 837 | static unsigned int |
| 838 | mmc_boot_send_csd(struct mmc_boot_card *card, unsigned int *raw_csd) |
| 839 | { |
| 840 | struct mmc_boot_command cmd; |
| 841 | unsigned int mmc_arg = 0; |
| 842 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 843 | |
| 844 | /* basic check */ |
| 845 | if (card == NULL) { |
| 846 | return MMC_BOOT_E_INVAL; |
| 847 | } |
| 848 | |
| 849 | memset((struct mmc_boot_command *)&cmd, 0, |
| 850 | sizeof(struct mmc_boot_command)); |
| 851 | |
| 852 | /* CMD9 Format: |
| 853 | * [31:16] RCA |
| 854 | * [15:0] stuff bits |
| 855 | */ |
| 856 | mmc_arg |= card->rca << 16; |
| 857 | |
| 858 | cmd.cmd_index = CMD9_SEND_CSD; |
| 859 | cmd.argument = mmc_arg; |
| 860 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 861 | cmd.resp_type = MMC_BOOT_RESP_R2; |
| 862 | |
| 863 | /* send command */ |
| 864 | mmc_ret = mmc_boot_send_command(&cmd); |
| 865 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 866 | return mmc_ret; |
| 867 | } |
| 868 | |
| 869 | /* response contains the card csd */ |
| 870 | memcpy(raw_csd, cmd.resp, sizeof(cmd.resp)); |
| 871 | |
| 872 | return MMC_BOOT_E_SUCCESS; |
| 873 | } |
| 874 | |
| 875 | /* |
| 876 | * Selects a card by sending CMD7 to the card with its RCA. |
| 877 | * If RCA field is set as 0 ( or any other address ), |
| 878 | * the card will be de-selected. (CMD7) |
| 879 | */ |
| 880 | static unsigned int |
| 881 | mmc_boot_select_card(struct mmc_boot_card *card, unsigned int rca) |
| 882 | { |
| 883 | struct mmc_boot_command cmd; |
| 884 | unsigned int mmc_arg = 0; |
| 885 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 886 | |
| 887 | /* basic check */ |
| 888 | if (card == NULL) { |
| 889 | return MMC_BOOT_E_INVAL; |
| 890 | } |
| 891 | |
| 892 | memset((struct mmc_boot_command *)&cmd, 0, |
| 893 | sizeof(struct mmc_boot_command)); |
| 894 | |
| 895 | /* CMD7 Format: |
| 896 | * [31:16] RCA |
| 897 | * [15:0] stuff bits |
| 898 | */ |
| 899 | mmc_arg |= rca << 16; |
| 900 | |
| 901 | cmd.cmd_index = CMD7_SELECT_DESELECT_CARD; |
| 902 | cmd.argument = mmc_arg; |
| 903 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 904 | /* If we are deselecting card, we do not get response */ |
| 905 | if (rca == card->rca && rca) { |
| 906 | if (card->type == MMC_BOOT_TYPE_SDHC |
| 907 | || card->type == MMC_BOOT_TYPE_STD_SD) |
| 908 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 909 | else |
| 910 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 911 | } else { |
| 912 | cmd.resp_type = MMC_BOOT_RESP_NONE; |
| 913 | } |
| 914 | |
| 915 | /* send command */ |
| 916 | mmc_ret = mmc_boot_send_command(&cmd); |
| 917 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 918 | return mmc_ret; |
| 919 | } |
| 920 | |
| 921 | /* As of now no need to look into a response. If it's required |
| 922 | * we'll explore later on */ |
| 923 | |
| 924 | return MMC_BOOT_E_SUCCESS; |
| 925 | } |
| 926 | |
| 927 | /* |
| 928 | * Send command to set block length. |
| 929 | */ |
| 930 | static unsigned int |
| 931 | mmc_boot_set_block_len(struct mmc_boot_card *card, unsigned int block_len) |
| 932 | { |
| 933 | struct mmc_boot_command cmd; |
| 934 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 935 | |
| 936 | /* basic check */ |
| 937 | if (card == NULL) { |
| 938 | return MMC_BOOT_E_INVAL; |
| 939 | } |
| 940 | |
| 941 | memset((struct mmc_boot_command *)&cmd, 0, |
| 942 | sizeof(struct mmc_boot_command)); |
| 943 | |
| 944 | /* CMD16 Format: |
| 945 | * [31:0] block length |
| 946 | */ |
| 947 | |
| 948 | cmd.cmd_index = CMD16_SET_BLOCKLEN; |
| 949 | cmd.argument = block_len; |
| 950 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 951 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 952 | |
| 953 | /* send command */ |
| 954 | mmc_ret = mmc_boot_send_command(&cmd); |
| 955 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 956 | return mmc_ret; |
| 957 | } |
| 958 | |
| 959 | /* If blocklength is larger than 512 bytes, |
| 960 | * the card sets BLOCK_LEN_ERROR bit. */ |
| 961 | if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) { |
| 962 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 963 | } |
| 964 | return MMC_BOOT_E_SUCCESS; |
| 965 | } |
| 966 | |
| 967 | /* |
| 968 | * Requests the card to stop transmission of data. |
| 969 | */ |
| 970 | static unsigned int |
| 971 | mmc_boot_send_stop_transmission(struct mmc_boot_card *card, |
| 972 | unsigned int prg_enabled) |
| 973 | { |
| 974 | struct mmc_boot_command cmd; |
| 975 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 976 | |
| 977 | /* basic check */ |
| 978 | if (card == NULL) { |
| 979 | return MMC_BOOT_E_INVAL; |
| 980 | } |
| 981 | |
| 982 | memset((struct mmc_boot_command *)&cmd, 0, |
| 983 | sizeof(struct mmc_boot_command)); |
| 984 | |
| 985 | /* CMD12 Format: |
| 986 | * [31:0] stuff bits |
| 987 | */ |
| 988 | |
| 989 | cmd.cmd_index = CMD12_STOP_TRANSMISSION; |
| 990 | cmd.argument = 0; |
| 991 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 992 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 993 | cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK; |
| 994 | cmd.prg_enabled = prg_enabled; |
| 995 | |
| 996 | /* send command */ |
| 997 | mmc_ret = mmc_boot_send_command(&cmd); |
| 998 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 999 | return mmc_ret; |
| 1000 | } |
| 1001 | return MMC_BOOT_E_SUCCESS; |
| 1002 | } |
| 1003 | |
| 1004 | /* |
| 1005 | * Get the card's current status |
| 1006 | */ |
| 1007 | static unsigned int |
| 1008 | mmc_boot_get_card_status(struct mmc_boot_card *card, |
| 1009 | unsigned int prg_enabled, unsigned int *status) |
| 1010 | { |
| 1011 | struct mmc_boot_command cmd; |
| 1012 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1013 | |
| 1014 | /* basic check */ |
| 1015 | if (card == NULL) { |
| 1016 | return MMC_BOOT_E_INVAL; |
| 1017 | } |
| 1018 | |
| 1019 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1020 | sizeof(struct mmc_boot_command)); |
| 1021 | |
| 1022 | /* CMD13 Format: |
| 1023 | * [31:16] RCA |
| 1024 | * [15:0] stuff bits |
| 1025 | */ |
| 1026 | cmd.cmd_index = CMD13_SEND_STATUS; |
| 1027 | cmd.argument = card->rca << 16; |
| 1028 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1029 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1030 | cmd.prg_enabled = prg_enabled; |
| 1031 | |
| 1032 | /* send command */ |
| 1033 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1034 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1035 | return mmc_ret; |
| 1036 | } |
| 1037 | |
| 1038 | /* Checking ADDR_OUT_OF_RANGE error in CMD13 response */ |
| 1039 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 1040 | return MMC_BOOT_E_FAILURE; |
| 1041 | } |
| 1042 | |
| 1043 | *status = cmd.resp[0]; |
| 1044 | return MMC_BOOT_E_SUCCESS; |
| 1045 | } |
| 1046 | |
| 1047 | /* |
| 1048 | * Decode type of error caused during read and write |
| 1049 | */ |
| 1050 | static unsigned int mmc_boot_status_error(unsigned mmc_status) |
| 1051 | { |
| 1052 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1053 | |
| 1054 | /* If DATA_CRC_FAIL bit is set to 1 then CRC error was detected by |
| 1055 | card/device during the data transfer */ |
| 1056 | if (mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL) { |
| 1057 | mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL; |
| 1058 | } |
| 1059 | /* If DATA_TIMEOUT bit is set to 1 then the data transfer time exceeded |
| 1060 | the data timeout period without completing the transfer */ |
| 1061 | else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT) { |
| 1062 | mmc_ret = MMC_BOOT_E_DATA_TIMEOUT; |
| 1063 | } |
| 1064 | /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to receive data from |
| 1065 | the card before empty storage for new received data was available. |
| 1066 | Verify that bit FLOW_ENA in MCI_CLK is set to 1 during the data xfer. */ |
| 1067 | else if (mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN) { |
| 1068 | /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. so no need to verify |
| 1069 | for now */ |
| 1070 | mmc_ret = MMC_BOOT_E_RX_OVRRUN; |
| 1071 | } |
| 1072 | /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send data to |
| 1073 | the card before new data for sending was available. Verify that bit |
| 1074 | FLOW_ENA in MCI_CLK is set to 1 during the data xfer. */ |
| 1075 | else if (mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN) { |
| 1076 | /* Note: We've set FLOW_ENA bit in MCI_CLK to 1.so skipping it now */ |
| 1077 | mmc_ret = MMC_BOOT_E_RX_OVRRUN; |
| 1078 | } |
| 1079 | return mmc_ret; |
| 1080 | } |
| 1081 | |
| 1082 | /* |
| 1083 | * Send ext csd command. |
| 1084 | */ |
| 1085 | static unsigned int |
| 1086 | mmc_boot_send_ext_cmd(struct mmc_boot_card *card, unsigned char *buf) |
| 1087 | { |
| 1088 | struct mmc_boot_command cmd; |
| 1089 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1090 | unsigned int mmc_reg = 0; |
| 1091 | unsigned int *mmc_ptr = (unsigned int *)buf; |
| 1092 | |
| 1093 | memset(buf, 0, 512); |
| 1094 | |
| 1095 | /* basic check */ |
| 1096 | if (card == NULL) { |
| 1097 | return MMC_BOOT_E_INVAL; |
| 1098 | } |
| 1099 | |
| 1100 | /* set block len */ |
| 1101 | if ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1102 | && (card->type != MMC_BOOT_TYPE_SDHC)) { |
| 1103 | mmc_ret = mmc_boot_set_block_len(card, 512); |
| 1104 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1105 | dprintf(CRITICAL, |
| 1106 | "Error No.%d: Failure setting block length for Card (RCA:%s)\n", |
| 1107 | mmc_ret, (char *)(card->rca)); |
| 1108 | return mmc_ret; |
| 1109 | } |
| 1110 | } |
| 1111 | |
| 1112 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 1113 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1114 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 1115 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1116 | |
| 1117 | /* Write data timeout period to MCI_DATA_TIMER register. */ |
| 1118 | /* Data timeout period should be in card bus clock periods */ |
| 1119 | mmc_reg = 0xFFFFFFFF; |
| 1120 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 1121 | writel(512, MMC_BOOT_MCI_DATA_LENGTH); |
| 1122 | |
| 1123 | /* Set appropriate fields and write the MCI_DATA_CTL register. */ |
| 1124 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 1125 | mmc_reg = |
| 1126 | MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (512 << |
| 1127 | MMC_BOOT_MCI_BLKSIZE_POS); |
| 1128 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1129 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1130 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 1131 | #endif |
| 1132 | |
| 1133 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 1134 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1135 | #if MMC_BOOT_BAM |
| 1136 | /* Setup SDCC BAM descriptors for Read operation. */ |
| 1137 | mmc_ret = mmc_boot_bam_setup_desc(mmc_ptr, 512, MMC_BOOT_DATA_READ); |
| 1138 | #endif |
| 1139 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1140 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1141 | sizeof(struct mmc_boot_command)); |
| 1142 | /* CMD8 */ |
| 1143 | cmd.cmd_index = CMD8_SEND_EXT_CSD; |
| 1144 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1145 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1146 | cmd.xfer_mode = MMC_BOOT_XFER_MODE_BLOCK; |
| 1147 | |
| 1148 | /* send command */ |
| 1149 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1150 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1151 | return mmc_ret; |
| 1152 | } |
| 1153 | |
| 1154 | /* Read the transfer data from SDCC FIFO. */ |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1155 | mmc_ret = mmc_boot_data_transfer(mmc_ptr, 512, MMC_BOOT_DATA_READ); |
| 1156 | |
| 1157 | /* Reset DPSM */ |
| 1158 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1159 | |
| 1160 | return mmc_ret; |
| 1161 | } |
| 1162 | |
| 1163 | /* |
| 1164 | * Switch command |
| 1165 | */ |
| 1166 | static unsigned int |
| 1167 | mmc_boot_switch_cmd(struct mmc_boot_card *card, |
| 1168 | unsigned access, unsigned index, unsigned value) |
| 1169 | { |
| 1170 | |
| 1171 | struct mmc_boot_command cmd; |
| 1172 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1173 | |
| 1174 | /* basic check */ |
| 1175 | if (card == NULL) { |
| 1176 | return MMC_BOOT_E_INVAL; |
| 1177 | } |
| 1178 | |
| 1179 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1180 | sizeof(struct mmc_boot_command)); |
| 1181 | |
| 1182 | /* CMD6 Format: |
| 1183 | * [31:26] set to 0 |
| 1184 | * [25:24] access |
| 1185 | * [23:16] index |
| 1186 | * [15:8] value |
| 1187 | * [7:3] set to 0 |
| 1188 | * [2:0] cmd set |
| 1189 | */ |
| 1190 | cmd.cmd_index = CMD6_SWITCH_FUNC; |
| 1191 | cmd.argument |= (access << 24); |
| 1192 | cmd.argument |= (index << 16); |
| 1193 | cmd.argument |= (value << 8); |
| 1194 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1195 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 1196 | |
| 1197 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1198 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1199 | return mmc_ret; |
| 1200 | } |
| 1201 | |
| 1202 | return MMC_BOOT_E_SUCCESS; |
| 1203 | } |
| 1204 | |
| 1205 | /* |
| 1206 | * A command to set the data bus width for card. Set width to either |
| 1207 | */ |
| 1208 | static unsigned int |
| 1209 | mmc_boot_set_bus_width(struct mmc_boot_card *card, unsigned int width) |
| 1210 | { |
| 1211 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1212 | unsigned int mmc_reg = 0; |
| 1213 | unsigned int mmc_width = 0; |
| 1214 | unsigned int status; |
| 1215 | unsigned int wait_count = 100; |
| 1216 | |
| 1217 | if (width != MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 1218 | mmc_width = width - 1; |
| 1219 | } |
| 1220 | |
| 1221 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, |
| 1222 | MMC_BOOT_EXT_CMMC_BUS_WIDTH, mmc_width); |
| 1223 | |
| 1224 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1225 | return mmc_ret; |
| 1226 | } |
| 1227 | |
| 1228 | /* Wait for the card to complete the switch command processing */ |
| 1229 | do { |
| 1230 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 1231 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1232 | return mmc_ret; |
| 1233 | } |
| 1234 | |
| 1235 | wait_count--; |
| 1236 | if (wait_count == 0) { |
| 1237 | return MMC_BOOT_E_FAILURE; |
| 1238 | } |
| 1239 | } |
| 1240 | while (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE); |
| 1241 | |
| 1242 | /* set MCI_CLK accordingly */ |
| 1243 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1244 | mmc_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE; |
| 1245 | if (width == MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 1246 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT; |
| 1247 | } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) { |
| 1248 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT; |
| 1249 | } else if (width == MMC_BOOT_BUS_WIDTH_8_BIT) { |
| 1250 | mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT; |
| 1251 | } |
| 1252 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1253 | |
| 1254 | mdelay(10); // Giving some time to card to stabilize. |
| 1255 | |
| 1256 | return MMC_BOOT_E_SUCCESS; |
| 1257 | } |
| 1258 | |
| 1259 | /* |
| 1260 | * A command to start data read from card. Either a single block or |
| 1261 | * multiple blocks can be read. Multiple blocks read will continuously |
| 1262 | * transfer data from card to host unless requested to stop by issuing |
| 1263 | * CMD12 - STOP_TRANSMISSION. |
| 1264 | */ |
| 1265 | static unsigned int |
| 1266 | mmc_boot_send_read_command(struct mmc_boot_card *card, |
| 1267 | unsigned int xfer_type, unsigned int data_addr) |
| 1268 | { |
| 1269 | struct mmc_boot_command cmd; |
| 1270 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1271 | |
| 1272 | /* basic check */ |
| 1273 | if (card == NULL) { |
| 1274 | return MMC_BOOT_E_INVAL; |
| 1275 | } |
| 1276 | |
| 1277 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1278 | sizeof(struct mmc_boot_command)); |
| 1279 | |
| 1280 | /* CMD17/18 Format: |
| 1281 | * [31:0] Data Address |
| 1282 | */ |
| 1283 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1284 | cmd.cmd_index = CMD18_READ_MULTIPLE_BLOCK; |
| 1285 | } else { |
| 1286 | cmd.cmd_index = CMD17_READ_SINGLE_BLOCK; |
| 1287 | } |
| 1288 | |
| 1289 | cmd.argument = data_addr; |
| 1290 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1291 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1292 | |
| 1293 | /* send command */ |
| 1294 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1295 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1296 | return mmc_ret; |
| 1297 | } |
| 1298 | |
| 1299 | /* Response contains 32 bit Card status. Here we'll check |
| 1300 | BLOCK_LEN_ERROR and ADDRESS_ERROR */ |
| 1301 | if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) { |
| 1302 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 1303 | } |
| 1304 | /* Misaligned address not matching block length */ |
| 1305 | if (cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR) { |
| 1306 | return MMC_BOOT_E_ADDRESS_ERR; |
| 1307 | } |
| 1308 | |
| 1309 | return MMC_BOOT_E_SUCCESS; |
| 1310 | } |
| 1311 | |
| 1312 | /* |
| 1313 | * A command to start data write to card. Either a single block or |
| 1314 | * multiple blocks can be written. Multiple block write will continuously |
| 1315 | * transfer data from host to card unless requested to stop by issuing |
| 1316 | * CMD12 - STOP_TRANSMISSION. |
| 1317 | */ |
| 1318 | static unsigned int |
| 1319 | mmc_boot_send_write_command(struct mmc_boot_card *card, |
| 1320 | unsigned int xfer_type, unsigned int data_addr) |
| 1321 | { |
| 1322 | struct mmc_boot_command cmd; |
| 1323 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1324 | |
| 1325 | /* basic check */ |
| 1326 | if (card == NULL) { |
| 1327 | return MMC_BOOT_E_INVAL; |
| 1328 | } |
| 1329 | |
| 1330 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1331 | sizeof(struct mmc_boot_command)); |
| 1332 | |
| 1333 | /* CMD24/25 Format: |
| 1334 | * [31:0] Data Address |
| 1335 | */ |
| 1336 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1337 | cmd.cmd_index = CMD25_WRITE_MULTIPLE_BLOCK; |
| 1338 | } else { |
| 1339 | cmd.cmd_index = CMD24_WRITE_SINGLE_BLOCK; |
| 1340 | } |
| 1341 | |
| 1342 | cmd.argument = data_addr; |
| 1343 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1344 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1345 | |
| 1346 | /* send command */ |
| 1347 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1348 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1349 | return mmc_ret; |
| 1350 | } |
| 1351 | |
| 1352 | /* Response contains 32 bit Card status. Here we'll check |
| 1353 | BLOCK_LEN_ERROR and ADDRESS_ERROR */ |
| 1354 | if (cmd.resp[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) { |
| 1355 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 1356 | } |
| 1357 | /* Misaligned address not matching block length */ |
| 1358 | if (cmd.resp[0] & MMC_BOOT_R1_ADDR_ERR) { |
| 1359 | return MMC_BOOT_E_ADDRESS_ERR; |
| 1360 | } |
| 1361 | |
| 1362 | return MMC_BOOT_E_SUCCESS; |
| 1363 | } |
| 1364 | |
| 1365 | /* |
| 1366 | * Write data_len data to address specified by data_addr. data_len is |
| 1367 | * multiple of blocks for block data transfer. |
| 1368 | */ |
| 1369 | unsigned int |
| 1370 | mmc_boot_write_to_card(struct mmc_boot_host *host, |
| 1371 | struct mmc_boot_card *card, |
| 1372 | unsigned long long data_addr, |
| 1373 | unsigned int data_len, unsigned int *in) |
| 1374 | { |
| 1375 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1376 | unsigned int mmc_status = 0; |
| 1377 | unsigned int mmc_reg = 0; |
| 1378 | unsigned int addr; |
| 1379 | unsigned int xfer_type; |
| 1380 | unsigned int status; |
| 1381 | |
| 1382 | if ((host == NULL) || (card == NULL)) { |
| 1383 | return MMC_BOOT_E_INVAL; |
| 1384 | } |
| 1385 | |
| 1386 | /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block |
| 1387 | length. So no need to send CMD16. */ |
| 1388 | if ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1389 | && (card->type != MMC_BOOT_TYPE_SDHC)) { |
| 1390 | mmc_ret = mmc_boot_set_block_len(card, card->wr_block_len); |
| 1391 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1392 | dprintf(CRITICAL, "Error No.%d: Failure setting block length for Card\ |
| 1393 | (RCA:%s)\n", mmc_ret, |
| 1394 | (char *)(card->rca)); |
| 1395 | return mmc_ret; |
| 1396 | } |
| 1397 | } |
| 1398 | |
| 1399 | /* use multi-block mode to transfer for data larger than a block */ |
| 1400 | xfer_type = |
| 1401 | (data_len > |
| 1402 | card-> |
| 1403 | rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK : |
| 1404 | MMC_BOOT_XFER_SINGLE_BLOCK; |
| 1405 | |
| 1406 | /* For MMCHC/SDHC data address is specified in unit of 512B */ |
| 1407 | addr = ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1408 | && (card->type != |
| 1409 | MMC_BOOT_TYPE_SDHC)) ? (unsigned int)data_addr : (unsigned |
| 1410 | int) |
| 1411 | (data_addr / 512); |
| 1412 | |
| 1413 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 1414 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 1415 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 1416 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 1417 | |
| 1418 | /* Write data timeout period to MCI_DATA_TIMER register */ |
| 1419 | /* Data timeout period should be in card bus clock periods */ |
| 1420 | /*TODO: Fix timeout value */ |
| 1421 | mmc_reg = 0xFFFFFFFF; |
| 1422 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 1423 | |
| 1424 | /* Write the total size of the transfer data to MCI_DATA_LENGTH register */ |
| 1425 | writel(data_len, MMC_BOOT_MCI_DATA_LENGTH); |
| 1426 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1427 | #if MMC_BOOT_BAM |
| 1428 | mmc_boot_bam_setup_desc(in, data_len, MMC_BOOT_DATA_WRITE); |
| 1429 | #endif |
| 1430 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1431 | /* Send command to the card/device in order to start the write data xfer. |
| 1432 | The possible commands are CMD24/25/53/60/61 */ |
| 1433 | mmc_ret = mmc_boot_send_write_command(card, xfer_type, addr); |
| 1434 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1435 | dprintf(CRITICAL, "Error No.%d: Failure sending write command to the\ |
| 1436 | Card(RCA:%x)\n", mmc_ret, |
| 1437 | card->rca); |
| 1438 | return mmc_ret; |
| 1439 | } |
| 1440 | |
| 1441 | /* Set appropriate fields and write the MCI_DATA_CTL register */ |
| 1442 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 1443 | mmc_reg = 0; |
| 1444 | mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE; |
| 1445 | /* Clear DIRECTION bit to 0 to enable transfer from host to card */ |
| 1446 | /* Clear MODE bit to 0 to enable block oriented data transfer. For |
| 1447 | MMC cards only, if stream data transfer mode is desired, set |
| 1448 | MODE bit to 1. */ |
| 1449 | |
| 1450 | /* Set DM_ENABLE bit to 1 in order to enable DMA, otherwise set 0 */ |
| 1451 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1452 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1453 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 1454 | #endif |
| 1455 | |
| 1456 | /* Write size of block to be used during the data transfer to |
| 1457 | BLOCKSIZE field */ |
| 1458 | mmc_reg |= card->wr_block_len << MMC_BOOT_MCI_BLKSIZE_POS; |
| 1459 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 1460 | |
| 1461 | /* write data to FIFO */ |
| 1462 | mmc_ret = |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1463 | mmc_boot_data_transfer(in, data_len, MMC_BOOT_DATA_WRITE); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1464 | |
| 1465 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1466 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \ |
| 1467 | Card(RCA:%x)\n", mmc_ret, |
| 1468 | card->rca); |
| 1469 | /* In case of any failure happening for multi block transfer */ |
| 1470 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) |
| 1471 | mmc_boot_send_stop_transmission(card, 1); |
| 1472 | return mmc_ret; |
| 1473 | } |
| 1474 | |
| 1475 | /* Send command to the card/device in order to poll the de-assertion of |
| 1476 | card/device BUSY condition. It is important to set PROG_ENA bit in |
| 1477 | MCI_CLK register before sending the command. Possible commands are |
| 1478 | CMD12/13. */ |
| 1479 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1480 | mmc_ret = mmc_boot_send_stop_transmission(card, 1); |
| 1481 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1482 | dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \ |
| 1483 | command to the Card(RCA:%x)\n", mmc_ret, |
| 1484 | card->rca); |
| 1485 | return mmc_ret; |
| 1486 | } |
| 1487 | } else { |
| 1488 | mmc_ret = mmc_boot_get_card_status(card, 1, &status); |
| 1489 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1490 | dprintf(CRITICAL, |
| 1491 | "Error No.%d: Failure getting card status of Card(RCA:%x)\n", |
| 1492 | mmc_ret, card->rca); |
| 1493 | return mmc_ret; |
| 1494 | } |
| 1495 | } |
| 1496 | |
| 1497 | /* Wait for interrupt or poll on PROG_DONE bit of MCI_STATUS register. If |
| 1498 | PROG_DONE bit is set to 1 it means that the card finished it programming |
| 1499 | and stopped driving DAT0 line to 0 */ |
| 1500 | do { |
| 1501 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 1502 | if (mmc_status & MMC_BOOT_MCI_STAT_PROG_DONE) { |
| 1503 | break; |
| 1504 | } |
| 1505 | } |
| 1506 | while (1); |
| 1507 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1508 | #if MMC_BOOT_BAM |
| 1509 | /* Wait for DML trasaction to end */ |
| 1510 | mmc_boot_dml_wait_consumer_idle(); |
| 1511 | #endif |
| 1512 | |
| 1513 | /* Reset DPSM */ |
| 1514 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
| 1515 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1516 | return MMC_BOOT_E_SUCCESS; |
| 1517 | } |
| 1518 | |
| 1519 | /* |
| 1520 | * Adjust the interface speed to optimal speed |
| 1521 | */ |
| 1522 | static unsigned int |
| 1523 | mmc_boot_adjust_interface_speed(struct mmc_boot_host *host, |
| 1524 | struct mmc_boot_card *card) |
| 1525 | { |
| 1526 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1527 | unsigned int status; |
| 1528 | unsigned int wait_count = 100; |
| 1529 | |
| 1530 | /* Setting HS_TIMING in EXT_CSD (CMD6) */ |
| 1531 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, |
| 1532 | MMC_BOOT_EXT_CMMC_HS_TIMING, 1); |
| 1533 | |
| 1534 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1535 | return mmc_ret; |
| 1536 | } |
| 1537 | |
| 1538 | /* Wait for the card to complete the switch command processing */ |
| 1539 | do { |
| 1540 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 1541 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
Amol Jadi | ead84fc | 2012-07-26 18:24:38 -0700 | [diff] [blame] | 1542 | dprintf(CRITICAL, "WARNING: Failed to get card status after" |
| 1543 | "cmd6. ret = %d wait_count = %d\n", |
| 1544 | mmc_ret, wait_count); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1545 | } |
| 1546 | |
| 1547 | wait_count--; |
| 1548 | if (wait_count == 0) { |
| 1549 | return MMC_BOOT_E_FAILURE; |
| 1550 | } |
| 1551 | } |
| 1552 | while (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE); |
| 1553 | |
| 1554 | clock_config_mmc(mmc_slot, MMC_CLK_50MHZ); |
| 1555 | |
| 1556 | host->mclk_rate = MMC_CLK_50MHZ; |
| 1557 | |
| 1558 | return MMC_BOOT_E_SUCCESS; |
| 1559 | } |
| 1560 | |
| 1561 | static unsigned int |
| 1562 | mmc_boot_set_block_count(struct mmc_boot_card *card, unsigned int block_count) |
| 1563 | { |
| 1564 | struct mmc_boot_command cmd; |
| 1565 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1566 | |
| 1567 | /* basic check */ |
| 1568 | if (card == NULL) { |
| 1569 | return MMC_BOOT_E_INVAL; |
| 1570 | } |
| 1571 | |
| 1572 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1573 | sizeof(struct mmc_boot_command)); |
| 1574 | |
| 1575 | /* CMD23 Format: |
| 1576 | * [15:0] number of blocks |
| 1577 | */ |
| 1578 | |
| 1579 | cmd.cmd_index = CMD23_SET_BLOCK_COUNT; |
| 1580 | cmd.argument = block_count; |
| 1581 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1582 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1583 | |
| 1584 | /* send command */ |
| 1585 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1586 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1587 | return mmc_ret; |
| 1588 | } |
| 1589 | |
| 1590 | if (cmd.resp[0] & MMC_BOOT_R1_OUT_OF_RANGE) { |
| 1591 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 1592 | } |
| 1593 | |
| 1594 | return MMC_BOOT_E_SUCCESS; |
| 1595 | } |
| 1596 | |
| 1597 | /* |
| 1598 | * Reads a data of data_len from the address specified. data_len |
| 1599 | * should be multiple of block size for block data transfer. |
| 1600 | */ |
| 1601 | unsigned int |
| 1602 | mmc_boot_read_from_card(struct mmc_boot_host *host, |
| 1603 | struct mmc_boot_card *card, |
| 1604 | unsigned long long data_addr, |
| 1605 | unsigned int data_len, unsigned int *out) |
| 1606 | { |
| 1607 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1608 | unsigned int mmc_reg = 0; |
| 1609 | unsigned int xfer_type; |
| 1610 | unsigned int addr = 0; |
| 1611 | unsigned char open_ended_read = 1; |
| 1612 | |
| 1613 | if ((host == NULL) || (card == NULL)) { |
| 1614 | return MMC_BOOT_E_INVAL; |
| 1615 | } |
| 1616 | |
| 1617 | /* Set block length. High Capacity MMC/SD card uses fixed 512 bytes block |
| 1618 | length. So no need to send CMD16. */ |
| 1619 | if ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1620 | && (card->type != MMC_BOOT_TYPE_SDHC)) { |
| 1621 | mmc_ret = mmc_boot_set_block_len(card, card->rd_block_len); |
| 1622 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1623 | dprintf(CRITICAL, |
| 1624 | "Error No.%d: Failure setting block length for Card (RCA:%s)\n", |
| 1625 | mmc_ret, (char *)(card->rca)); |
| 1626 | return mmc_ret; |
| 1627 | } |
| 1628 | } |
| 1629 | |
| 1630 | /* use multi-block mode to transfer for data larger than a block */ |
| 1631 | xfer_type = |
| 1632 | (data_len > |
| 1633 | card-> |
| 1634 | rd_block_len) ? MMC_BOOT_XFER_MULTI_BLOCK : |
| 1635 | MMC_BOOT_XFER_SINGLE_BLOCK; |
| 1636 | |
| 1637 | if (xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) { |
| 1638 | if ((card->type == MMC_BOOT_TYPE_MMCHC) |
| 1639 | || (card->type == MMC_BOOT_TYPE_STD_MMC)) { |
| 1640 | /* Virtio model does not support open-ended multi-block reads. |
| 1641 | * So, block count must be set before sending read command. |
| 1642 | * All SD cards do not support this command. Restrict this to MMC. |
| 1643 | */ |
| 1644 | mmc_ret = |
| 1645 | mmc_boot_set_block_count(card, |
| 1646 | data_len / |
| 1647 | (card->rd_block_len)); |
| 1648 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1649 | dprintf(CRITICAL, |
| 1650 | "Error No.%d: Failure setting read block count for Card (RCA:%s)\n", |
| 1651 | mmc_ret, (char *)(card->rca)); |
| 1652 | return mmc_ret; |
| 1653 | } |
| 1654 | |
| 1655 | open_ended_read = 0; |
| 1656 | } |
| 1657 | } |
| 1658 | |
| 1659 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 1660 | /* Note: It's already enabled */ |
| 1661 | |
| 1662 | /* If Data Mover is used for data transfer then prepare Command |
| 1663 | List Entry and enable the Data mover to work with SDCC2 */ |
| 1664 | |
| 1665 | /* Write data timeout period to MCI_DATA_TIMER register. */ |
| 1666 | /* Data timeout period should be in card bus clock periods */ |
| 1667 | mmc_reg = (unsigned long)(card->rd_timeout_ns / 1000000) * |
| 1668 | (host->mclk_rate / 1000); |
| 1669 | mmc_reg += 1000; // add some extra clock cycles to be safe |
| 1670 | mmc_reg = mmc_reg / 2; |
| 1671 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 1672 | |
| 1673 | /* Write the total size of the transfer data to MCI_DATA_LENGTH |
| 1674 | register. For block xfer it must be multiple of the block |
| 1675 | size. */ |
| 1676 | writel(data_len, MMC_BOOT_MCI_DATA_LENGTH); |
| 1677 | |
| 1678 | /* For MMCHC/SDHC data address is specified in unit of 512B */ |
| 1679 | addr = ((card->type != MMC_BOOT_TYPE_MMCHC) |
| 1680 | && (card->type != |
| 1681 | MMC_BOOT_TYPE_SDHC)) ? (unsigned int)data_addr : (unsigned |
| 1682 | int) |
| 1683 | (data_addr / 512); |
| 1684 | |
| 1685 | /* Set appropriate fields and write the MCI_DATA_CTL register. */ |
| 1686 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 1687 | mmc_reg = 0; |
| 1688 | mmc_reg |= MMC_BOOT_MCI_DATA_ENABLE; |
| 1689 | /* Clear DIRECTION bit to 1 to enable transfer from card to host */ |
| 1690 | mmc_reg |= MMC_BOOT_MCI_DATA_DIR; |
| 1691 | /* Clear MODE bit to 0 to enable block oriented data transfer. For |
| 1692 | MMC cards only, if stream data transfer mode is desired, set |
| 1693 | MODE bit to 1. */ |
| 1694 | |
| 1695 | /* If DMA is to be used, Set DM_ENABLE bit to 1 */ |
| 1696 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1697 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1698 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 1699 | #endif |
| 1700 | |
| 1701 | /* Write size of block to be used during the data transfer to |
| 1702 | BLOCKSIZE field */ |
| 1703 | mmc_reg |= (card->rd_block_len << MMC_BOOT_MCI_BLKSIZE_POS); |
| 1704 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 1705 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1706 | #if MMC_BOOT_BAM |
| 1707 | /* Setup SDCC FIFO descriptors for Read operation. */ |
| 1708 | mmc_ret = mmc_boot_bam_setup_desc(out, data_len, MMC_BOOT_DATA_READ); |
| 1709 | #endif |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1710 | /* Send command to the card/device in order to start the read data |
| 1711 | transfer. Possible commands: CMD17/18/53/60/61. */ |
| 1712 | mmc_ret = mmc_boot_send_read_command(card, xfer_type, addr); |
| 1713 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1714 | dprintf(CRITICAL, |
| 1715 | "Error No.%d: Failure sending read command to the Card(RCA:%x)\n", |
| 1716 | mmc_ret, card->rca); |
| 1717 | return mmc_ret; |
| 1718 | } |
| 1719 | |
| 1720 | /* Read the transfer data from SDCC FIFO. */ |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1721 | mmc_ret = mmc_boot_data_transfer(out, data_len, MMC_BOOT_DATA_READ); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1722 | |
| 1723 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1724 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \ |
| 1725 | Card(RCA:%x)\n", mmc_ret, |
| 1726 | card->rca); |
| 1727 | return mmc_ret; |
| 1728 | } |
| 1729 | |
| 1730 | /* In case a multiple block transfer was performed, send CMD12 to the |
| 1731 | card/device in order to indicate the end of read data transfer */ |
| 1732 | if ((xfer_type == MMC_BOOT_XFER_MULTI_BLOCK) && open_ended_read) { |
| 1733 | mmc_ret = mmc_boot_send_stop_transmission(card, 0); |
| 1734 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1735 | dprintf(CRITICAL, "Error No.%d: Failure sending Stop Transmission \ |
| 1736 | command to the Card(RCA:%x)\n", mmc_ret, |
| 1737 | card->rca); |
| 1738 | return mmc_ret; |
| 1739 | } |
| 1740 | } |
| 1741 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 1742 | /* Reset DPSM */ |
| 1743 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
| 1744 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 1745 | return MMC_BOOT_E_SUCCESS; |
| 1746 | } |
| 1747 | |
| 1748 | /* |
| 1749 | * Initialize host structure, set and enable clock-rate and power mode. |
| 1750 | */ |
| 1751 | unsigned int mmc_boot_init(struct mmc_boot_host *host) |
| 1752 | { |
| 1753 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1754 | unsigned int mmc_pwr = 0; |
| 1755 | |
| 1756 | host->ocr = MMC_BOOT_OCR_27_36 | MMC_BOOT_OCR_SEC_MODE; |
| 1757 | host->cmd_retry = MMC_BOOT_MAX_COMMAND_RETRY; |
| 1758 | |
| 1759 | /* Initialize any clocks needed for SDC controller */ |
| 1760 | clock_init_mmc(mmc_slot); |
| 1761 | |
| 1762 | /* Setup initial freq to 400KHz */ |
| 1763 | clock_config_mmc(mmc_slot, MMC_CLK_400KHZ); |
| 1764 | |
| 1765 | host->mclk_rate = MMC_CLK_400KHZ; |
| 1766 | |
| 1767 | /* set power mode */ |
| 1768 | /* give some time to reach minimum voltate */ |
| 1769 | mdelay(2); |
| 1770 | mmc_pwr &= ~MMC_BOOT_MCI_PWR_UP; |
| 1771 | mmc_pwr |= MMC_BOOT_MCI_PWR_ON; |
| 1772 | mmc_pwr |= MMC_BOOT_MCI_PWR_UP; |
| 1773 | writel(mmc_pwr, MMC_BOOT_MCI_POWER); |
| 1774 | /* some more time to stabilize voltage */ |
| 1775 | mdelay(2); |
| 1776 | |
| 1777 | return MMC_BOOT_E_SUCCESS; |
| 1778 | } |
| 1779 | |
| 1780 | /* |
| 1781 | * Performs card identification process: |
| 1782 | * - get card's unique identification number (CID) |
| 1783 | * - get(for sd)/set (for mmc) relative card address (RCA) |
| 1784 | * - get CSD |
| 1785 | * - select the card, thus transitioning it to Transfer State |
| 1786 | * - get Extended CSD (for mmc) |
| 1787 | */ |
| 1788 | static unsigned int |
| 1789 | mmc_boot_identify_card(struct mmc_boot_host *host, struct mmc_boot_card *card) |
| 1790 | { |
| 1791 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 1792 | unsigned int raw_csd[4]; |
| 1793 | |
| 1794 | /* basic check */ |
| 1795 | if ((host == NULL) || (card == NULL)) { |
| 1796 | return MMC_BOOT_E_INVAL; |
| 1797 | } |
| 1798 | |
| 1799 | /* Ask card to send its unique card identification (CID) number (CMD2) */ |
| 1800 | mmc_return = mmc_boot_all_send_cid(card); |
| 1801 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1802 | dprintf(CRITICAL, |
| 1803 | "Error No. %d: Failure getting card's CID number!\n", |
| 1804 | mmc_return); |
| 1805 | return mmc_return; |
| 1806 | } |
| 1807 | |
| 1808 | /* Ask card to send a relative card address (RCA) (CMD3) */ |
| 1809 | mmc_return = mmc_boot_send_relative_address(card); |
| 1810 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1811 | dprintf(CRITICAL, "Error No. %d: Failure getting card's RCA!\n", |
| 1812 | mmc_return); |
| 1813 | return mmc_return; |
| 1814 | } |
| 1815 | |
| 1816 | /* Get card's CSD register (CMD9) */ |
| 1817 | mmc_return = mmc_boot_send_csd(card, raw_csd); |
| 1818 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1819 | dprintf(CRITICAL, |
| 1820 | "Error No.%d: Failure getting card's CSD information!\n", |
| 1821 | mmc_return); |
| 1822 | return mmc_return; |
| 1823 | } |
| 1824 | |
| 1825 | /* Select the card (CMD7) */ |
| 1826 | mmc_return = mmc_boot_select_card(card, card->rca); |
| 1827 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1828 | dprintf(CRITICAL, |
| 1829 | "Error No.%d: Failure selecting the Card with RCA: %x\n", |
| 1830 | mmc_return, card->rca); |
| 1831 | return mmc_return; |
| 1832 | } |
| 1833 | |
| 1834 | /* Set the card status as active */ |
| 1835 | card->status = MMC_BOOT_STATUS_ACTIVE; |
| 1836 | |
| 1837 | if ((card->type == MMC_BOOT_TYPE_STD_MMC) |
| 1838 | || (card->type == MMC_BOOT_TYPE_MMCHC)) { |
| 1839 | /* For MMC cards, also get the extended csd */ |
| 1840 | mmc_return = mmc_boot_send_ext_cmd(card, ext_csd_buf); |
| 1841 | |
| 1842 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1843 | dprintf(CRITICAL, |
| 1844 | "Error No.%d: Failure getting card's ExtCSD information!\n", |
| 1845 | mmc_return); |
| 1846 | |
| 1847 | return mmc_return; |
| 1848 | } |
| 1849 | |
| 1850 | } |
| 1851 | |
| 1852 | /* Decode and save the CSD register */ |
| 1853 | mmc_return = mmc_boot_decode_and_save_csd(card, raw_csd); |
| 1854 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1855 | dprintf(CRITICAL, |
| 1856 | "Error No.%d: Failure decoding card's CSD information!\n", |
| 1857 | mmc_return); |
| 1858 | return mmc_return; |
| 1859 | } |
| 1860 | |
| 1861 | /* Once CSD is received, set read and write timeout value now itself */ |
| 1862 | mmc_return = mmc_boot_set_read_timeout(host, card); |
| 1863 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1864 | dprintf(CRITICAL, |
| 1865 | "Error No.%d: Failure setting Read Timeout value!\n", |
| 1866 | mmc_return); |
| 1867 | return mmc_return; |
| 1868 | } |
| 1869 | |
| 1870 | mmc_return = mmc_boot_set_write_timeout(host, card); |
| 1871 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1872 | dprintf(CRITICAL, |
| 1873 | "Error No.%d: Failure setting Write Timeout value!\n", |
| 1874 | mmc_return); |
| 1875 | return mmc_return; |
| 1876 | } |
| 1877 | |
| 1878 | return MMC_BOOT_E_SUCCESS; |
| 1879 | } |
| 1880 | |
| 1881 | static unsigned int mmc_boot_send_app_cmd(unsigned int rca) |
| 1882 | { |
| 1883 | struct mmc_boot_command cmd; |
| 1884 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 1885 | |
| 1886 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1887 | sizeof(struct mmc_boot_command)); |
| 1888 | |
| 1889 | cmd.cmd_index = CMD55_APP_CMD; |
| 1890 | cmd.argument = (rca << 16); |
| 1891 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 1892 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 1893 | |
| 1894 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1895 | |
| 1896 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1897 | return mmc_ret; |
| 1898 | } |
| 1899 | |
| 1900 | return MMC_BOOT_E_SUCCESS; |
| 1901 | } |
| 1902 | |
| 1903 | static unsigned int mmc_boot_sd_init_card(struct mmc_boot_card *card) |
| 1904 | { |
| 1905 | unsigned int i, mmc_ret; |
| 1906 | unsigned int ocr_cmd_arg; |
| 1907 | struct mmc_boot_command cmd; |
| 1908 | |
| 1909 | memset((struct mmc_boot_command *)&cmd, 0, |
| 1910 | sizeof(struct mmc_boot_command)); |
| 1911 | |
| 1912 | /* Send CMD8 to set interface condition */ |
| 1913 | for (i = 0; i < 3; i++) { |
| 1914 | cmd.cmd_index = CMD8_SEND_IF_COND; |
| 1915 | cmd.argument = MMC_BOOT_SD_HC_VOLT_SUPPLIED; |
| 1916 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 1917 | cmd.resp_type = MMC_BOOT_RESP_R7; |
| 1918 | |
| 1919 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1920 | if (mmc_ret == MMC_BOOT_E_SUCCESS) { |
| 1921 | if (cmd.resp[0] != MMC_BOOT_SD_HC_VOLT_SUPPLIED) |
| 1922 | return MMC_BOOT_E_FAILURE; |
| 1923 | /* Set argument for ACMD41 */ |
| 1924 | ocr_cmd_arg = MMC_BOOT_SD_NEG_OCR | MMC_BOOT_SD_HC_HCS; |
| 1925 | break; |
| 1926 | } |
| 1927 | mdelay(1); |
| 1928 | } |
| 1929 | |
| 1930 | /* Send ACMD41 to set operating condition */ |
| 1931 | /* Try for a max of 1 sec as per spec */ |
| 1932 | for (i = 0; i < 20; i++) { |
| 1933 | mmc_ret = mmc_boot_send_app_cmd(0); |
| 1934 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1935 | return mmc_ret; |
| 1936 | } |
| 1937 | |
| 1938 | cmd.cmd_index = ACMD41_SEND_OP_COND; |
| 1939 | cmd.argument = ocr_cmd_arg; |
| 1940 | cmd.cmd_type = MMC_BOOT_CMD_BCAST_W_RESP; |
| 1941 | cmd.resp_type = MMC_BOOT_RESP_R3; |
| 1942 | |
| 1943 | mmc_ret = mmc_boot_send_command(&cmd); |
| 1944 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 1945 | return mmc_ret; |
| 1946 | } else if (cmd.resp[0] & MMC_BOOT_SD_DEV_READY) { |
| 1947 | /* Check for HC */ |
| 1948 | if (cmd.resp[0] & (1 << 30)) { |
| 1949 | card->type = MMC_BOOT_TYPE_SDHC; |
| 1950 | } else { |
| 1951 | card->type = MMC_BOOT_TYPE_STD_SD; |
| 1952 | } |
| 1953 | break; |
| 1954 | } |
| 1955 | mdelay(50); |
| 1956 | } |
| 1957 | return MMC_BOOT_E_SUCCESS; |
| 1958 | } |
| 1959 | |
| 1960 | /* |
| 1961 | * Routine to initialize MMC card. It resets a card to idle state, verify operating |
| 1962 | * voltage and set the card inready state. |
| 1963 | */ |
| 1964 | static unsigned int |
| 1965 | mmc_boot_init_card(struct mmc_boot_host *host, struct mmc_boot_card *card) |
| 1966 | { |
| 1967 | unsigned int mmc_retry = 0; |
| 1968 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 1969 | |
| 1970 | /* basic check */ |
| 1971 | if ((host == NULL) || (card == NULL)) { |
| 1972 | return MMC_BOOT_E_INVAL; |
| 1973 | } |
| 1974 | |
| 1975 | /* 1. Card Reset - CMD0 */ |
| 1976 | mmc_return = mmc_boot_reset_cards(); |
| 1977 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 1978 | dprintf(CRITICAL, |
| 1979 | "Error No.:%d: Failure resetting MMC cards!\n", |
| 1980 | mmc_return); |
| 1981 | return mmc_return; |
| 1982 | } |
| 1983 | |
| 1984 | /* 2. Card Initialization process */ |
| 1985 | |
| 1986 | /* Send CMD1 to identify and reject cards that do not match host's VDD range |
| 1987 | profile. Cards sends its OCR register in response. |
| 1988 | */ |
| 1989 | mmc_retry = 0; |
| 1990 | do { |
| 1991 | mmc_return = mmc_boot_send_op_cond(host, card); |
| 1992 | /* Card returns busy status. We'll retry again! */ |
| 1993 | if (mmc_return == MMC_BOOT_E_CARD_BUSY) { |
| 1994 | mmc_retry++; |
| 1995 | mdelay(1); |
| 1996 | continue; |
| 1997 | } else if (mmc_return == MMC_BOOT_E_SUCCESS) { |
| 1998 | break; |
| 1999 | } else { |
| 2000 | dprintf(CRITICAL, |
| 2001 | "Error No. %d: Failure Initializing MMC Card!\n", |
| 2002 | mmc_return); |
| 2003 | |
| 2004 | /* Check for sD card */ |
| 2005 | mmc_return = mmc_boot_sd_init_card(card); |
| 2006 | return mmc_return; |
| 2007 | } |
| 2008 | } |
| 2009 | while (mmc_retry < host->cmd_retry); |
| 2010 | |
| 2011 | /* If card still returned busy status we are out of luck. |
| 2012 | * Card cannot be initialized */ |
| 2013 | if (mmc_return == MMC_BOOT_E_CARD_BUSY) { |
| 2014 | dprintf(CRITICAL, "Error No. %d: Card has busy status set. \ |
| 2015 | Initialization not completed\n", mmc_return); |
| 2016 | return MMC_BOOT_E_CARD_BUSY; |
| 2017 | } |
| 2018 | return MMC_BOOT_E_SUCCESS; |
| 2019 | } |
| 2020 | |
| 2021 | static unsigned int |
| 2022 | mmc_boot_set_sd_bus_width(struct mmc_boot_card *card, unsigned int width) |
| 2023 | { |
| 2024 | struct mmc_boot_command cmd; |
| 2025 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2026 | unsigned int sd_reg; |
| 2027 | |
| 2028 | mmc_ret = mmc_boot_send_app_cmd(card->rca); |
| 2029 | |
| 2030 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2031 | return mmc_ret; |
| 2032 | } |
| 2033 | |
| 2034 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2035 | sizeof(struct mmc_boot_command)); |
| 2036 | |
| 2037 | /* Send ACMD6 to set bus width */ |
| 2038 | cmd.cmd_index = ACMD6_SET_BUS_WIDTH; |
| 2039 | /* 10 => 4 bit wide */ |
| 2040 | if (width == MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 2041 | cmd.argument = 0; |
| 2042 | } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) { |
| 2043 | cmd.argument = (1 << 1); |
| 2044 | } |
| 2045 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2046 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2047 | |
| 2048 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2049 | |
| 2050 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2051 | return mmc_ret; |
| 2052 | } |
| 2053 | |
| 2054 | /* set MCI_CLK accordingly */ |
| 2055 | sd_reg = readl(MMC_BOOT_MCI_CLK); |
| 2056 | sd_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE; |
| 2057 | if (width == MMC_BOOT_BUS_WIDTH_1_BIT) { |
| 2058 | sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT; |
| 2059 | } else if (width == MMC_BOOT_BUS_WIDTH_4_BIT) { |
| 2060 | sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT; |
| 2061 | } else if (width == MMC_BOOT_BUS_WIDTH_8_BIT) { |
| 2062 | sd_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT; |
| 2063 | } |
| 2064 | writel(sd_reg, MMC_BOOT_MCI_CLK); |
| 2065 | |
| 2066 | mdelay(10); // Giving some time to card to stabilize. |
| 2067 | |
| 2068 | return MMC_BOOT_E_SUCCESS; |
| 2069 | } |
| 2070 | |
| 2071 | static unsigned int |
| 2072 | mmc_boot_set_sd_hs(struct mmc_boot_host *host, struct mmc_boot_card *card) |
| 2073 | { |
| 2074 | unsigned char sw_buf[64]; |
| 2075 | unsigned int mmc_ret; |
| 2076 | |
| 2077 | /* CMD6 is a data transfer command. sD card returns 512 bits of data */ |
| 2078 | /* Refer 4.3.10 of sD card specification 3.0 */ |
| 2079 | mmc_ret = |
| 2080 | mmc_boot_read_reg(card, 64, CMD6_SWITCH_FUNC, MMC_BOOT_SD_SWITCH_HS, |
| 2081 | (unsigned int *)&sw_buf); |
| 2082 | |
| 2083 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2084 | return mmc_ret; |
| 2085 | } |
| 2086 | |
| 2087 | mdelay(1); |
| 2088 | |
| 2089 | clock_config_mmc(mmc_slot, MMC_CLK_50MHZ); |
| 2090 | |
| 2091 | host->mclk_rate = MMC_CLK_50MHZ; |
| 2092 | |
| 2093 | return MMC_BOOT_E_SUCCESS; |
| 2094 | } |
| 2095 | |
| 2096 | /* |
| 2097 | * Performs initialization and identification of all the MMC cards connected |
| 2098 | * to the host. |
| 2099 | */ |
| 2100 | |
| 2101 | static unsigned int |
| 2102 | mmc_boot_init_and_identify_cards(struct mmc_boot_host *host, |
| 2103 | struct mmc_boot_card *card) |
| 2104 | { |
| 2105 | unsigned int mmc_return = MMC_BOOT_E_SUCCESS; |
| 2106 | unsigned int status; |
| 2107 | |
| 2108 | /* Basic check */ |
| 2109 | if (host == NULL) { |
| 2110 | return MMC_BOOT_E_INVAL; |
| 2111 | } |
| 2112 | |
| 2113 | /* Initialize MMC card structure */ |
| 2114 | card->status = MMC_BOOT_STATUS_INACTIVE; |
| 2115 | card->rd_block_len = MMC_BOOT_RD_BLOCK_LEN; |
| 2116 | card->wr_block_len = MMC_BOOT_WR_BLOCK_LEN; |
| 2117 | |
| 2118 | /* Start initialization process (CMD0 & CMD1) */ |
| 2119 | mmc_return = mmc_boot_init_card(host, card); |
| 2120 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2121 | return mmc_return; |
| 2122 | } |
| 2123 | |
| 2124 | /* Identify (CMD2, CMD3 & CMD9) and select the card (CMD7) */ |
| 2125 | mmc_return = mmc_boot_identify_card(host, card); |
| 2126 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2127 | return mmc_return; |
| 2128 | } |
| 2129 | |
| 2130 | if (card->type == MMC_BOOT_TYPE_SDHC |
| 2131 | || card->type == MMC_BOOT_TYPE_STD_SD) { |
| 2132 | /* Setting sD card to high speed without checking card's capability. |
| 2133 | Cards that do not support high speed may fail to boot */ |
| 2134 | mmc_return = mmc_boot_set_sd_hs(host, card); |
| 2135 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2136 | return mmc_return; |
| 2137 | } |
| 2138 | |
| 2139 | mmc_return = |
| 2140 | mmc_boot_set_sd_bus_width(card, MMC_BOOT_BUS_WIDTH_4_BIT); |
| 2141 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2142 | dprintf(CRITICAL, |
| 2143 | "Couldn't set 4bit mode for sD card\n"); |
| 2144 | mmc_return = |
| 2145 | mmc_boot_set_sd_bus_width(card, |
| 2146 | MMC_BOOT_BUS_WIDTH_1_BIT); |
| 2147 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2148 | dprintf(CRITICAL, |
| 2149 | "Error No.%d: Failed in setting bus width!\n", |
| 2150 | mmc_return); |
| 2151 | return mmc_return; |
| 2152 | } |
| 2153 | } |
| 2154 | } else { |
| 2155 | /* set interface speed */ |
| 2156 | mmc_return = mmc_boot_adjust_interface_speed(host, card); |
| 2157 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2158 | dprintf(CRITICAL, |
| 2159 | "Error No.%d: Error adjusting interface speed!\n", |
| 2160 | mmc_return); |
| 2161 | return mmc_return; |
| 2162 | } |
| 2163 | |
| 2164 | /* enable wide bus */ |
| 2165 | mmc_return = |
| 2166 | mmc_boot_set_bus_width(card, MMC_BOOT_BUS_WIDTH_4_BIT); |
| 2167 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2168 | dprintf(CRITICAL, |
| 2169 | "Error No.%d: Failure to set wide bus for Card(RCA:%x)\n", |
| 2170 | mmc_return, card->rca); |
| 2171 | return mmc_return; |
| 2172 | } |
| 2173 | } |
| 2174 | |
| 2175 | /* Just checking whether we're in TRAN state after changing speed and bus width */ |
| 2176 | mmc_return = mmc_boot_get_card_status(card, 0, &status); |
| 2177 | if (mmc_return != MMC_BOOT_E_SUCCESS) { |
| 2178 | return mmc_return; |
| 2179 | } |
| 2180 | |
| 2181 | if (MMC_BOOT_CARD_STATUS(status) != MMC_BOOT_TRAN_STATE) |
| 2182 | return MMC_BOOT_E_FAILURE; |
| 2183 | |
| 2184 | return MMC_BOOT_E_SUCCESS; |
| 2185 | } |
| 2186 | |
| 2187 | void mmc_display_ext_csd(void) |
| 2188 | { |
| 2189 | dprintf(SPEW, "part_config: %x\n", ext_csd_buf[179]); |
| 2190 | dprintf(SPEW, "erase_group_def: %x\n", ext_csd_buf[175]); |
| 2191 | dprintf(SPEW, "user_wp: %x\n", ext_csd_buf[171]); |
| 2192 | } |
| 2193 | |
| 2194 | void mmc_display_csd(void) |
| 2195 | { |
| 2196 | dprintf(SPEW, "erase_grpsize: %d\n", mmc_card.csd.erase_grp_size); |
| 2197 | dprintf(SPEW, "erase_grpmult: %d\n", mmc_card.csd.erase_grp_mult); |
| 2198 | dprintf(SPEW, "wp_grpsize: %d\n", mmc_card.csd.wp_grp_size); |
| 2199 | dprintf(SPEW, "wp_grpen: %d\n", mmc_card.csd.wp_grp_enable); |
| 2200 | dprintf(SPEW, "perm_wp: %d\n", mmc_card.csd.perm_wp); |
| 2201 | dprintf(SPEW, "temp_wp: %d\n", mmc_card.csd.temp_wp); |
| 2202 | } |
| 2203 | |
| 2204 | /* |
| 2205 | * Entry point to MMC boot process |
| 2206 | */ |
| 2207 | unsigned int mmc_boot_main(unsigned char slot, unsigned int base) |
| 2208 | { |
| 2209 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2210 | |
| 2211 | memset((struct mmc_boot_host *)&mmc_host, 0, |
| 2212 | sizeof(struct mmc_boot_host)); |
| 2213 | memset((struct mmc_boot_card *)&mmc_card, 0, |
| 2214 | sizeof(struct mmc_boot_card)); |
| 2215 | |
| 2216 | mmc_slot = slot; |
| 2217 | mmc_boot_mci_base = base; |
| 2218 | |
| 2219 | /* Initialize necessary data structure and enable/set clock and power */ |
| 2220 | dprintf(SPEW, " Initializing MMC host data structure and clock!\n"); |
| 2221 | mmc_ret = mmc_boot_init(&mmc_host); |
| 2222 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2223 | dprintf(CRITICAL, "MMC Boot: Error Initializing MMC Card!!!\n"); |
| 2224 | return MMC_BOOT_E_FAILURE; |
| 2225 | } |
| 2226 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 2227 | #if MMC_BOOT_BAM |
| 2228 | |
| 2229 | mmc_ret = mmc_bam_init(mmc_sdc_bam_base[slot - 1]); |
| 2230 | dml_base = mmc_sdc_dml_base[slot - 1]; |
| 2231 | #endif |
| 2232 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2233 | /* Initialize and identify cards connected to host */ |
| 2234 | mmc_ret = mmc_boot_init_and_identify_cards(&mmc_host, &mmc_card); |
| 2235 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2236 | dprintf(CRITICAL, |
| 2237 | "MMC Boot: Failed detecting MMC/SDC @ slot%d\n", slot); |
| 2238 | return MMC_BOOT_E_FAILURE; |
| 2239 | } |
| 2240 | |
| 2241 | mmc_display_csd(); |
| 2242 | mmc_display_ext_csd(); |
| 2243 | |
| 2244 | mmc_ret = partition_read_table(&mmc_host, &mmc_card); |
| 2245 | return mmc_ret; |
| 2246 | } |
| 2247 | |
| 2248 | /* |
| 2249 | * MMC write function |
| 2250 | */ |
| 2251 | unsigned int |
| 2252 | mmc_write(unsigned long long data_addr, unsigned int data_len, unsigned int *in) |
| 2253 | { |
| 2254 | int val = 0; |
| 2255 | unsigned int write_size = ((unsigned)(0xFFFFFF / 512)) * 512; |
| 2256 | unsigned offset = 0; |
| 2257 | unsigned int *sptr = in; |
| 2258 | |
| 2259 | if (data_len % 512) |
| 2260 | data_len = ROUND_TO_PAGE(data_len, 511); |
| 2261 | |
| 2262 | while (data_len > write_size) { |
| 2263 | val = mmc_boot_write_to_card(&mmc_host, &mmc_card, |
| 2264 | data_addr + offset, write_size, |
| 2265 | sptr); |
| 2266 | if (val) { |
| 2267 | return val; |
| 2268 | } |
| 2269 | |
| 2270 | sptr += (write_size / sizeof(unsigned)); |
| 2271 | offset += write_size; |
| 2272 | data_len -= write_size; |
| 2273 | } |
| 2274 | if (data_len) { |
| 2275 | val = mmc_boot_write_to_card(&mmc_host, &mmc_card, |
| 2276 | data_addr + offset, data_len, |
| 2277 | sptr); |
| 2278 | } |
| 2279 | return val; |
| 2280 | } |
| 2281 | |
| 2282 | /* |
| 2283 | * MMC read function |
| 2284 | */ |
| 2285 | |
| 2286 | unsigned int |
| 2287 | mmc_read(unsigned long long data_addr, unsigned int *out, unsigned int data_len) |
| 2288 | { |
| 2289 | int val = 0; |
| 2290 | val = |
| 2291 | mmc_boot_read_from_card(&mmc_host, &mmc_card, data_addr, data_len, |
| 2292 | out); |
| 2293 | return val; |
| 2294 | } |
| 2295 | |
| 2296 | /* |
| 2297 | * Function to read registers from MMC or SD card |
| 2298 | */ |
| 2299 | static unsigned int |
| 2300 | mmc_boot_read_reg(struct mmc_boot_card *card, |
| 2301 | unsigned int data_len, |
| 2302 | unsigned int command, unsigned int addr, unsigned int *out) |
| 2303 | { |
| 2304 | struct mmc_boot_command cmd; |
| 2305 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2306 | unsigned int mmc_reg = 0; |
| 2307 | |
| 2308 | /* Set the FLOW_ENA bit of MCI_CLK register to 1 */ |
| 2309 | mmc_reg = readl(MMC_BOOT_MCI_CLK); |
| 2310 | mmc_reg |= MMC_BOOT_MCI_CLK_ENA_FLOW; |
| 2311 | writel(mmc_reg, MMC_BOOT_MCI_CLK); |
| 2312 | |
| 2313 | /* Write data timeout period to MCI_DATA_TIMER register. */ |
| 2314 | /* Data timeout period should be in card bus clock periods */ |
| 2315 | mmc_reg = 0xFFFFFFFF; |
| 2316 | writel(mmc_reg, MMC_BOOT_MCI_DATA_TIMER); |
| 2317 | writel(data_len, MMC_BOOT_MCI_DATA_LENGTH); |
| 2318 | |
| 2319 | /* Set appropriate fields and write the MCI_DATA_CTL register. */ |
| 2320 | /* Set ENABLE bit to 1 to enable the data transfer. */ |
| 2321 | mmc_reg = |
| 2322 | MMC_BOOT_MCI_DATA_ENABLE | MMC_BOOT_MCI_DATA_DIR | (data_len << |
| 2323 | MMC_BOOT_MCI_BLKSIZE_POS); |
| 2324 | |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 2325 | #if MMC_BOOT_ADM || MMC_BOOT_BAM |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2326 | mmc_reg |= MMC_BOOT_MCI_DATA_DM_ENABLE; |
| 2327 | #endif |
| 2328 | |
| 2329 | writel(mmc_reg, MMC_BOOT_MCI_DATA_CTL); |
| 2330 | |
| 2331 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2332 | sizeof(struct mmc_boot_command)); |
| 2333 | |
| 2334 | cmd.cmd_index = command; |
| 2335 | cmd.argument = addr; |
| 2336 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2337 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2338 | |
| 2339 | /* send command */ |
| 2340 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2341 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2342 | return mmc_ret; |
| 2343 | } |
| 2344 | |
| 2345 | /* Read the transfer data from SDCC FIFO. */ |
| 2346 | mmc_ret = |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 2347 | mmc_boot_data_transfer(out, data_len, MMC_BOOT_DATA_READ); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2348 | |
| 2349 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2350 | dprintf(CRITICAL, "Error No.%d: Failure on data transfer from the \ |
| 2351 | Card(RCA:%x)\n", mmc_ret, |
| 2352 | card->rca); |
| 2353 | return mmc_ret; |
| 2354 | } |
| 2355 | |
| 2356 | return MMC_BOOT_E_SUCCESS; |
| 2357 | } |
| 2358 | |
| 2359 | /* |
| 2360 | * Function to set/clear power-on write protection for the user area partitions |
| 2361 | */ |
| 2362 | static unsigned int |
| 2363 | mmc_boot_set_clr_power_on_wp_user(struct mmc_boot_card *card, |
| 2364 | unsigned int addr, |
| 2365 | unsigned int size, unsigned char set_clear_wp) |
| 2366 | { |
| 2367 | struct mmc_boot_command cmd; |
| 2368 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2369 | unsigned int wp_group_size, loop_count; |
| 2370 | unsigned int status; |
| 2371 | |
| 2372 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2373 | sizeof(struct mmc_boot_command)); |
| 2374 | |
| 2375 | /* Disabling PERM_WP for USER AREA (CMD6) */ |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2376 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2377 | MMC_BOOT_EXT_USER_WP, |
| 2378 | MMC_BOOT_US_PERM_WP_DIS); |
| 2379 | |
| 2380 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2381 | return mmc_ret; |
| 2382 | } |
| 2383 | |
| 2384 | /* Sending CMD13 to check card status */ |
| 2385 | do { |
| 2386 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2387 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2388 | break; |
| 2389 | } |
| 2390 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2391 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2392 | |
| 2393 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2394 | return mmc_ret; |
| 2395 | } |
| 2396 | |
| 2397 | mmc_ret = mmc_boot_send_ext_cmd(card, ext_csd_buf); |
| 2398 | |
| 2399 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2400 | return mmc_ret; |
| 2401 | } |
| 2402 | |
| 2403 | /* Make sure power-on write protection for user area is not disabled |
| 2404 | and permanent write protection for user area is not enabled */ |
| 2405 | |
| 2406 | if ((IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PERM_WP_EN)) |
| 2407 | || |
| 2408 | (IS_BIT_SET_EXT_CSD(MMC_BOOT_EXT_USER_WP, MMC_BOOT_US_PWR_WP_DIS))) |
| 2409 | { |
| 2410 | return MMC_BOOT_E_FAILURE; |
| 2411 | } |
| 2412 | |
| 2413 | if (ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF]) { |
| 2414 | /* wp_group_size = 512KB * HC_WP_GRP_SIZE * HC_ERASE_GRP_SIZE. |
| 2415 | Getting write protect group size in sectors here. */ |
| 2416 | |
| 2417 | wp_group_size = |
| 2418 | (512 * 1024) * ext_csd_buf[MMC_BOOT_EXT_HC_WP_GRP_SIZE] * |
| 2419 | ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] / |
| 2420 | MMC_BOOT_WR_BLOCK_LEN; |
| 2421 | } else { |
| 2422 | /* wp_group_size = (WP_GRP_SIZE + 1) * (ERASE_GRP_SIZE + 1) |
| 2423 | * (ERASE_GRP_MULT + 1). |
| 2424 | This is defined as the number of write blocks directly */ |
| 2425 | |
| 2426 | wp_group_size = (card->csd.erase_grp_size + 1) * |
| 2427 | (card->csd.erase_grp_mult + 1) * (card->csd.wp_grp_size + |
| 2428 | 1); |
| 2429 | } |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2430 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2431 | if (wp_group_size == 0) { |
| 2432 | return MMC_BOOT_E_FAILURE; |
| 2433 | } |
| 2434 | |
| 2435 | /* Setting POWER_ON_WP for USER AREA (CMD6) */ |
| 2436 | |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2437 | mmc_ret = mmc_boot_switch_cmd(card, MMC_BOOT_ACCESS_WRITE, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2438 | MMC_BOOT_EXT_USER_WP, |
| 2439 | MMC_BOOT_US_PWR_WP_EN); |
| 2440 | |
| 2441 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2442 | return mmc_ret; |
| 2443 | } |
| 2444 | |
| 2445 | /* Sending CMD13 to check card status */ |
| 2446 | do { |
| 2447 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2448 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2449 | break; |
| 2450 | } |
| 2451 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2452 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2453 | |
| 2454 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2455 | return mmc_ret; |
| 2456 | } |
| 2457 | |
| 2458 | /* Calculating the loop count for sending SET_WRITE_PROTECT (CMD28) |
| 2459 | or CLEAR_WRITE_PROTECT (CMD29). |
| 2460 | We are write protecting the partitions in blocks of write protect |
| 2461 | group sizes only */ |
| 2462 | |
| 2463 | if (size % wp_group_size) { |
| 2464 | loop_count = (size / wp_group_size) + 1; |
| 2465 | } else { |
| 2466 | loop_count = (size / wp_group_size); |
| 2467 | } |
| 2468 | |
| 2469 | if (set_clear_wp) |
| 2470 | cmd.cmd_index = CMD28_SET_WRITE_PROTECT; |
| 2471 | else |
| 2472 | cmd.cmd_index = CMD29_CLEAR_WRITE_PROTECT; |
| 2473 | |
| 2474 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2475 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 2476 | |
| 2477 | for (unsigned int i = 0; i < loop_count; i++) { |
| 2478 | /* Sending CMD28 for each WP group size |
| 2479 | address is in sectors already */ |
| 2480 | cmd.argument = (addr + (i * wp_group_size)); |
| 2481 | |
| 2482 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2483 | |
| 2484 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2485 | return mmc_ret; |
| 2486 | } |
| 2487 | |
| 2488 | /* Checking ADDR_OUT_OF_RANGE error in CMD28 response */ |
| 2489 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 2490 | return MMC_BOOT_E_FAILURE; |
| 2491 | } |
| 2492 | |
| 2493 | /* Sending CMD13 to check card status */ |
| 2494 | do { |
| 2495 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2496 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2497 | break; |
| 2498 | } |
| 2499 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2500 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2501 | |
| 2502 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2503 | return mmc_ret; |
| 2504 | } |
| 2505 | } |
| 2506 | |
| 2507 | return MMC_BOOT_E_SUCCESS; |
| 2508 | } |
| 2509 | |
| 2510 | /* |
| 2511 | * Function to get Write Protect status of the given sector |
| 2512 | */ |
| 2513 | static unsigned int |
| 2514 | mmc_boot_get_wp_status(struct mmc_boot_card *card, unsigned int sector) |
| 2515 | { |
| 2516 | unsigned int rc = MMC_BOOT_E_SUCCESS; |
| 2517 | memset(wp_status_buf, 0, 8); |
| 2518 | |
| 2519 | rc = mmc_boot_read_reg(card, 8, CMD31_SEND_WRITE_PROT_TYPE, sector, |
| 2520 | (unsigned int *)wp_status_buf); |
| 2521 | return rc; |
| 2522 | } |
| 2523 | |
| 2524 | /* |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2525 | * Test Function for setting Write protect for given sector |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2526 | */ |
Shashank Mittal | ac23fa1 | 2012-02-13 17:38:15 -0800 | [diff] [blame] | 2527 | static unsigned int |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2528 | mmc_wp(unsigned int sector, unsigned int size, unsigned char set_clear_wp) |
| 2529 | { |
| 2530 | unsigned int rc = MMC_BOOT_E_SUCCESS; |
| 2531 | |
| 2532 | /* Checking whether group write protection feature is available */ |
| 2533 | if (mmc_card.csd.wp_grp_enable) { |
| 2534 | rc = mmc_boot_get_wp_status(&mmc_card, sector); |
| 2535 | rc = mmc_boot_set_clr_power_on_wp_user(&mmc_card, sector, size, |
| 2536 | set_clear_wp); |
| 2537 | rc = mmc_boot_get_wp_status(&mmc_card, sector); |
| 2538 | return rc; |
| 2539 | } else |
| 2540 | return MMC_BOOT_E_FAILURE; |
| 2541 | } |
| 2542 | |
| 2543 | void mmc_wp_test(void) |
| 2544 | { |
| 2545 | unsigned int mmc_ret = 0; |
| 2546 | mmc_ret = mmc_wp(0xE06000, 0x5000, 1); |
| 2547 | } |
| 2548 | |
| 2549 | unsigned mmc_get_psn(void) |
| 2550 | { |
| 2551 | return mmc_card.cid.psn; |
| 2552 | } |
| 2553 | |
| 2554 | /* |
| 2555 | * Read/write data from/to SDC FIFO. |
| 2556 | */ |
| 2557 | static unsigned int |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 2558 | mmc_boot_data_transfer(unsigned int *data_ptr, |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2559 | unsigned int data_len, unsigned char direction) |
| 2560 | { |
| 2561 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2562 | |
| 2563 | #if MMC_BOOT_ADM |
| 2564 | adm_result_t ret; |
| 2565 | adm_dir_t adm_dir; |
| 2566 | |
| 2567 | if (direction == MMC_BOOT_DATA_READ) { |
| 2568 | adm_dir = ADM_MMC_READ; |
| 2569 | } else { |
| 2570 | adm_dir = ADM_MMC_WRITE; |
| 2571 | } |
| 2572 | |
| 2573 | ret = adm_transfer_mmc_data(mmc_slot, |
| 2574 | (unsigned char *)data_ptr, data_len, |
| 2575 | adm_dir); |
| 2576 | |
| 2577 | if (ret != ADM_RESULT_SUCCESS) { |
| 2578 | dprintf(CRITICAL, "MMC ADM transfer error: %d\n", ret); |
| 2579 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 2580 | } |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 2581 | |
| 2582 | #elif MMC_BOOT_BAM |
| 2583 | mmc_ret = mmc_bam_transfer_data(data_ptr, data_len, direction); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2584 | #else |
| 2585 | |
| 2586 | if (direction == MMC_BOOT_DATA_READ) { |
| 2587 | mmc_ret = mmc_boot_fifo_read(data_ptr, data_len); |
| 2588 | } else { |
| 2589 | mmc_ret = mmc_boot_fifo_write(data_ptr, data_len); |
| 2590 | } |
| 2591 | #endif |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 2592 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2593 | return mmc_ret; |
| 2594 | } |
| 2595 | |
| 2596 | /* |
| 2597 | * Read data to SDC FIFO. |
| 2598 | */ |
| 2599 | static unsigned int |
| 2600 | mmc_boot_fifo_read(unsigned int *mmc_ptr, unsigned int data_len) |
| 2601 | { |
| 2602 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2603 | unsigned int mmc_status = 0; |
| 2604 | unsigned int mmc_count = 0; |
| 2605 | unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | |
| 2606 | MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_RX_OVRRUN; |
| 2607 | |
| 2608 | /* Read the data from the MCI_FIFO register as long as RXDATA_AVLBL |
| 2609 | bit of MCI_STATUS register is set to 1 and bits DATA_CRC_FAIL, |
| 2610 | DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS register are cleared to 0. |
| 2611 | Continue the reads until the whole transfer data is received */ |
| 2612 | |
| 2613 | do { |
| 2614 | mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2615 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 2616 | |
| 2617 | if (mmc_status & read_error) { |
| 2618 | mmc_ret = mmc_boot_status_error(mmc_status); |
| 2619 | break; |
| 2620 | } |
| 2621 | |
| 2622 | if (mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL) { |
| 2623 | unsigned read_count = 1; |
| 2624 | if (mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL) { |
| 2625 | read_count = MMC_BOOT_MCI_HFIFO_COUNT; |
| 2626 | } |
| 2627 | |
| 2628 | for (unsigned int i = 0; i < read_count; i++) { |
| 2629 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */ |
| 2630 | *mmc_ptr = readl(MMC_BOOT_MCI_FIFO + |
| 2631 | (mmc_count % |
| 2632 | MMC_BOOT_MCI_FIFO_SIZE)); |
| 2633 | mmc_ptr++; |
| 2634 | /* increase mmc_count by word size */ |
| 2635 | mmc_count += sizeof(unsigned int); |
| 2636 | } |
| 2637 | /* quit if we have read enough of data */ |
| 2638 | if (mmc_count == data_len) |
| 2639 | break; |
| 2640 | } else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_END) { |
| 2641 | break; |
| 2642 | } |
| 2643 | } |
| 2644 | while (1); |
| 2645 | |
| 2646 | return mmc_ret; |
| 2647 | } |
| 2648 | |
| 2649 | /* |
| 2650 | * Write data to SDC FIFO. |
| 2651 | */ |
| 2652 | static unsigned int |
| 2653 | mmc_boot_fifo_write(unsigned int *mmc_ptr, unsigned int data_len) |
| 2654 | { |
| 2655 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2656 | unsigned int mmc_status = 0; |
| 2657 | unsigned int mmc_count = 0; |
| 2658 | unsigned int write_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | |
| 2659 | MMC_BOOT_MCI_STAT_DATA_TIMEOUT | MMC_BOOT_MCI_STAT_TX_UNDRUN; |
| 2660 | |
| 2661 | /* Write the transfer data to SDCC3 FIFO */ |
| 2662 | do { |
| 2663 | mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2664 | mmc_status = readl(MMC_BOOT_MCI_STATUS); |
| 2665 | |
| 2666 | if (mmc_status & write_error) { |
| 2667 | mmc_ret = mmc_boot_status_error(mmc_status); |
| 2668 | break; |
| 2669 | } |
| 2670 | |
| 2671 | /* Write the data in MCI_FIFO register as long as TXFIFO_FULL bit of |
| 2672 | MCI_STATUS register is 0. Continue the writes until the whole |
| 2673 | transfer data is written. */ |
| 2674 | if (((data_len - mmc_count) >= MMC_BOOT_MCI_FIFO_SIZE / 2) && |
| 2675 | (mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_HFULL)) { |
| 2676 | for (int i = 0; i < MMC_BOOT_MCI_HFIFO_COUNT; i++) { |
| 2677 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */ |
| 2678 | writel(*mmc_ptr, MMC_BOOT_MCI_FIFO + |
| 2679 | (mmc_count % MMC_BOOT_MCI_FIFO_SIZE)); |
| 2680 | mmc_ptr++; |
| 2681 | /* increase mmc_count by word size */ |
| 2682 | mmc_count += sizeof(unsigned int); |
| 2683 | } |
| 2684 | |
| 2685 | } else if (!(mmc_status & MMC_BOOT_MCI_STAT_TX_FIFO_FULL) |
| 2686 | && (mmc_count != data_len)) { |
| 2687 | /* FIFO contains 16 32-bit data buffer on 16 sequential addresses */ |
| 2688 | writel(*mmc_ptr, MMC_BOOT_MCI_FIFO + |
| 2689 | (mmc_count % MMC_BOOT_MCI_FIFO_SIZE)); |
| 2690 | mmc_ptr++; |
| 2691 | /* increase mmc_count by word size */ |
| 2692 | mmc_count += sizeof(unsigned int); |
| 2693 | } else if ((mmc_status & MMC_BOOT_MCI_STAT_DATA_END)) { |
| 2694 | break; //success |
| 2695 | } |
| 2696 | |
| 2697 | } |
| 2698 | while (1); |
| 2699 | return mmc_ret; |
| 2700 | } |
| 2701 | |
| 2702 | /* |
| 2703 | * CMD35_ERASE_GROUP_START |
| 2704 | */ |
| 2705 | |
| 2706 | static unsigned int |
| 2707 | mmc_boot_send_erase_group_start(struct mmc_boot_card *card, |
| 2708 | unsigned long long data_addr) |
| 2709 | { |
| 2710 | struct mmc_boot_command cmd; |
| 2711 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2712 | |
| 2713 | if (card == NULL) |
| 2714 | return MMC_BOOT_E_INVAL; |
| 2715 | |
| 2716 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2717 | sizeof(struct mmc_boot_command)); |
| 2718 | |
| 2719 | cmd.cmd_index = CMD35_ERASE_GROUP_START; |
| 2720 | cmd.argument = data_addr; |
| 2721 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2722 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2723 | |
| 2724 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2725 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2726 | return mmc_ret; |
| 2727 | } |
| 2728 | |
| 2729 | /* Checking for address error */ |
| 2730 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 2731 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 2732 | } |
| 2733 | |
| 2734 | return MMC_BOOT_E_SUCCESS; |
| 2735 | |
| 2736 | } |
| 2737 | |
| 2738 | /* |
| 2739 | * CMD36 ERASE GROUP END |
| 2740 | */ |
| 2741 | static unsigned int |
| 2742 | mmc_boot_send_erase_group_end(struct mmc_boot_card *card, |
| 2743 | unsigned long long data_addr) |
| 2744 | { |
| 2745 | struct mmc_boot_command cmd; |
| 2746 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2747 | |
| 2748 | if (card == NULL) |
| 2749 | return MMC_BOOT_E_INVAL; |
| 2750 | |
| 2751 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2752 | sizeof(struct mmc_boot_command)); |
| 2753 | |
| 2754 | cmd.cmd_index = CMD36_ERASE_GROUP_END; |
| 2755 | cmd.argument = data_addr; |
| 2756 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2757 | cmd.resp_type = MMC_BOOT_RESP_R1; |
| 2758 | |
| 2759 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2760 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2761 | return mmc_ret; |
| 2762 | } |
| 2763 | |
| 2764 | /* Checking for address error */ |
| 2765 | if (IS_ADDR_OUT_OF_RANGE(cmd.resp[0])) { |
| 2766 | return MMC_BOOT_E_BLOCKLEN_ERR; |
| 2767 | } |
| 2768 | |
| 2769 | return MMC_BOOT_E_SUCCESS; |
| 2770 | } |
| 2771 | |
| 2772 | /* |
| 2773 | * CMD38 ERASE |
| 2774 | */ |
| 2775 | static unsigned int mmc_boot_send_erase(struct mmc_boot_card *card) |
| 2776 | { |
| 2777 | |
| 2778 | struct mmc_boot_command cmd; |
| 2779 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2780 | unsigned int status; |
| 2781 | |
| 2782 | if (card == NULL) |
| 2783 | return MMC_BOOT_E_INVAL; |
| 2784 | |
| 2785 | memset((struct mmc_boot_command *)&cmd, 0, |
| 2786 | sizeof(struct mmc_boot_command)); |
| 2787 | |
| 2788 | cmd.cmd_index = CMD38_ERASE; |
| 2789 | cmd.argument = 0x00000000; |
| 2790 | cmd.cmd_type = MMC_BOOT_CMD_ADDRESS; |
| 2791 | cmd.resp_type = MMC_BOOT_RESP_R1B; |
| 2792 | |
| 2793 | /* Checking if the card is in the transfer state */ |
| 2794 | do { |
| 2795 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2796 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2797 | break; |
| 2798 | } |
| 2799 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2800 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2801 | |
| 2802 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2803 | return mmc_ret; |
| 2804 | } |
| 2805 | mmc_ret = mmc_boot_send_command(&cmd); |
| 2806 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2807 | return mmc_ret; |
| 2808 | } |
| 2809 | |
| 2810 | /* Checking for write protect */ |
| 2811 | if (cmd.resp[0] & MMC_BOOT_R1_WP_ERASE_SKIP) { |
| 2812 | dprintf(CRITICAL, "Write protect enabled for sector \n"); |
| 2813 | return; |
| 2814 | } |
| 2815 | |
| 2816 | /* Checking if the erase operation for the card is compelete */ |
| 2817 | do { |
| 2818 | mmc_ret = mmc_boot_get_card_status(card, 0, &status); |
| 2819 | if (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_TRAN_STATE) |
| 2820 | break; |
| 2821 | } |
| 2822 | while ((mmc_ret == MMC_BOOT_E_SUCCESS) && |
| 2823 | (MMC_BOOT_CARD_STATUS(status) == MMC_BOOT_PROG_STATE)); |
| 2824 | |
| 2825 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2826 | return mmc_ret; |
| 2827 | } |
| 2828 | |
| 2829 | return MMC_BOOT_E_SUCCESS; |
| 2830 | } |
| 2831 | |
| 2832 | /* |
| 2833 | * Function to erase data on the eMMC card |
| 2834 | */ |
| 2835 | unsigned int |
| 2836 | mmc_erase_card(unsigned long long data_addr, unsigned long long size) |
| 2837 | { |
| 2838 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 2839 | unsigned long long erase_grp_size; |
| 2840 | unsigned long long data_end = 0x00000000; |
| 2841 | unsigned long long loop_count; |
| 2842 | unsigned int out[512] = { 0 }; |
| 2843 | |
| 2844 | /* Converting size to sectors */ |
| 2845 | size = size / 512; |
| 2846 | |
| 2847 | if (ext_csd_buf[MMC_BOOT_EXT_ERASE_GROUP_DEF]) { |
| 2848 | erase_grp_size = |
| 2849 | (512 * ext_csd_buf[MMC_BOOT_EXT_HC_ERASE_GRP_SIZE] * 1024); |
| 2850 | erase_grp_size = erase_grp_size / 512; |
| 2851 | } else { |
| 2852 | erase_grp_size = (mmc_card.csd.erase_grp_size + 1) * |
| 2853 | (mmc_card.csd.erase_grp_mult + 1); |
| 2854 | } |
| 2855 | |
| 2856 | if (erase_grp_size == 0) { |
| 2857 | return MMC_BOOT_E_FAILURE; |
| 2858 | } |
| 2859 | |
| 2860 | if (size % erase_grp_size) { |
| 2861 | dprintf(CRITICAL, "Overflow beyond ERASE_GROUP_SIZE:%llu\n", |
| 2862 | (size % erase_grp_size)); |
| 2863 | |
| 2864 | } |
| 2865 | loop_count = (size / erase_grp_size); |
| 2866 | /* |
| 2867 | *In case the partition size is less than the erase_grp_size |
| 2868 | 0 is written to the first block of the partition. |
| 2869 | */ |
| 2870 | if (loop_count < 1) { |
| 2871 | mmc_ret = mmc_write(data_addr, 512, (unsigned int *)out); |
| 2872 | if (mmc_ret != MMC_BOOT_E_SUCCESS) |
| 2873 | return mmc_ret; |
| 2874 | else |
| 2875 | return MMC_BOOT_E_SUCCESS; |
| 2876 | } else { |
| 2877 | data_addr = ((mmc_card.type != MMC_BOOT_TYPE_MMCHC) && |
| 2878 | (mmc_card.type != MMC_BOOT_TYPE_SDHC)) |
| 2879 | ? (unsigned int)data_addr : (unsigned int)(data_addr / 512); |
| 2880 | data_end = data_addr + erase_grp_size * (loop_count - 1); |
| 2881 | } |
| 2882 | |
| 2883 | /* Sending CMD35 */ |
| 2884 | mmc_ret = mmc_boot_send_erase_group_start(&mmc_card, data_addr); |
| 2885 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2886 | dprintf(CRITICAL, "Error %d: Failure sending erase group start " |
| 2887 | "command to the card (RCA:%x)\n", mmc_ret, |
| 2888 | mmc_card.rca); |
| 2889 | return mmc_ret; |
| 2890 | } |
| 2891 | |
| 2892 | /* Sending CMD36 */ |
Neeti Desai | e8bd43d | 2012-04-11 17:12:31 -0700 | [diff] [blame] | 2893 | mmc_ret = mmc_boot_send_erase_group_end(&mmc_card, data_end); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2894 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2895 | dprintf(CRITICAL, "Error %d: Failure sending erase group end " |
| 2896 | "command to the card (RCA:%x)\n", mmc_ret, |
| 2897 | mmc_card.rca); |
| 2898 | return mmc_ret; |
| 2899 | } |
| 2900 | |
Neeti Desai | e8bd43d | 2012-04-11 17:12:31 -0700 | [diff] [blame] | 2901 | /* Sending CMD38 */ |
| 2902 | mmc_ret = mmc_boot_send_erase(&mmc_card); |
| 2903 | if (mmc_ret != MMC_BOOT_E_SUCCESS) { |
| 2904 | dprintf(CRITICAL, |
| 2905 | "Error %d: Failure sending erase command " |
| 2906 | "to the card (RCA:%x)\n", mmc_ret, mmc_card.rca); |
| 2907 | return mmc_ret; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2908 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2909 | } |
Neeti Desai | e8bd43d | 2012-04-11 17:12:31 -0700 | [diff] [blame] | 2910 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 2911 | dprintf(CRITICAL, "ERASE SUCCESSFULLY COMPLETED\n"); |
| 2912 | return MMC_BOOT_E_SUCCESS; |
| 2913 | } |
| 2914 | |
| 2915 | struct mmc_boot_host *get_mmc_host(void) |
| 2916 | { |
| 2917 | return &mmc_host; |
| 2918 | } |
| 2919 | |
| 2920 | struct mmc_boot_card *get_mmc_card(void) |
| 2921 | { |
| 2922 | return &mmc_card; |
| 2923 | } |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame^] | 2924 | |
| 2925 | #if MMC_BOOT_BAM |
| 2926 | |
| 2927 | void mmc_boot_dml_init() |
| 2928 | { |
| 2929 | uint32_t val = 0; |
| 2930 | |
| 2931 | /* Initialize s/w reset for DML core */ |
| 2932 | mmc_boot_dml_reset(); |
| 2933 | |
| 2934 | /* Program DML config: |
| 2935 | * 1. Disable producer and consumer CRCI. |
| 2936 | * 2. Set Bypass mode for the DML for Direct access. |
| 2937 | */ |
| 2938 | val = 0; |
| 2939 | val |= 1 >> SDCC_BYPASS_SHIFT; |
| 2940 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 2941 | |
| 2942 | /* Program consumer logic size: |
| 2943 | * This is for handshaking between the BAM and the DML blocks. |
| 2944 | */ |
| 2945 | writel(4096, SDCC_DML_CONSUMER_PIPE_LOGICAL_SIZE(dml_base)); |
| 2946 | |
| 2947 | /* Program producer logic size |
| 2948 | * This is for handshaking between the BAM and the DML blocks. |
| 2949 | */ |
| 2950 | writel(4096, SDCC_DML_PRODUCER_PIPE_LOGICAL_SIZE(dml_base)); |
| 2951 | |
| 2952 | |
| 2953 | /* Write the pipe id numbers. */ |
| 2954 | val = 0; |
| 2955 | val |= bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].pipe_num << SDCC_PRODUCER_PIPE_ID_SHIFT; |
| 2956 | val |= bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].pipe_num << SDCC_CONSUMER_PIPE_ID_SHIFT; |
| 2957 | |
| 2958 | writel(val, SDCC_DML_PIPE_ID(dml_base)); |
| 2959 | |
| 2960 | } |
| 2961 | |
| 2962 | /* Function to set up SDCC dml for System producer transaction. */ |
| 2963 | static void mmc_boot_dml_consumer_trans_init() |
| 2964 | { |
| 2965 | uint32_t val = 0; |
| 2966 | |
| 2967 | val = 0 << SDCC_PRODUCER_CRCI_SEL_SHIFT; |
| 2968 | val |= 1 << SDCC_CONSUMER_CRCI_SEL_SHIFT; |
| 2969 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 2970 | |
| 2971 | |
| 2972 | /* Start the consumer transaction */ |
| 2973 | writel(1, SDCC_DML_CONSUMER_START(dml_base)); |
| 2974 | |
| 2975 | } |
| 2976 | |
| 2977 | /* Function to set up SDCC dml for System consumer transaction. |
| 2978 | * trans_end: 1: Assert DML trasaction signal |
| 2979 | * at the end of transaction. |
| 2980 | * 0: Do not assert DML transaction signal. |
| 2981 | * size: Transaction size |
| 2982 | */ |
| 2983 | static void mmc_boot_dml_producer_trans_init(unsigned trans_end, |
| 2984 | unsigned size) |
| 2985 | { |
| 2986 | uint32_t val = 0; |
| 2987 | |
| 2988 | val = 1 << SDCC_PRODUCER_CRCI_SEL_SHIFT; |
| 2989 | val |= 0 << SDCC_CONSUMER_CRCI_SEL_SHIFT; |
| 2990 | val |= trans_end << SDCC_PRODUCER_TRANS_END_EN_SHIFT; |
| 2991 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 2992 | |
| 2993 | /* Set block size */ |
| 2994 | writel(BLOCK_SIZE, SDCC_DML_PRODUCER_BAM_BLOCK_SIZE(dml_base)); |
| 2995 | |
| 2996 | /* Write transaction size */ |
| 2997 | writel(size, SDCC_DML_PRODUCER_BAM_TRANS_SIZE(dml_base)); |
| 2998 | |
| 2999 | /* Start the producer transaction */ |
| 3000 | writel(1, SDCC_DML_PRODUCER_START(dml_base)); |
| 3001 | } |
| 3002 | |
| 3003 | /* Function to check producer idle status of the DML. |
| 3004 | * return value: 1: Producer is idle |
| 3005 | * 0: Producer is busy |
| 3006 | */ |
| 3007 | static uint32_t mmc_boot_dml_chk_producer_idle() |
| 3008 | { |
| 3009 | uint32_t val = 0; |
| 3010 | |
| 3011 | val = readl(SDCC_DML_STATUS(dml_base)); |
| 3012 | |
| 3013 | /* Read only the producer idle status */ |
| 3014 | val &= (1 << SDCC_DML_PRODUCER_IDLE_SHIFT); |
| 3015 | |
| 3016 | return val; |
| 3017 | } |
| 3018 | |
| 3019 | /* Function to clear transaction complete flag */ |
| 3020 | static void mmc_boot_dml_clr_trans_complete() |
| 3021 | { |
| 3022 | uint32_t val; |
| 3023 | |
| 3024 | val = readl(SDCC_DML_CONFIG(dml_base)); |
| 3025 | |
| 3026 | val &= ~(1 << SDCC_PRODUCER_TRANS_END_EN_SHIFT); |
| 3027 | writel(val, SDCC_DML_CONFIG(dml_base)); |
| 3028 | } |
| 3029 | |
| 3030 | /* Blocking function to wait until DML is idle. */ |
| 3031 | static void mmc_boot_dml_wait_producer_idle() |
| 3032 | { |
| 3033 | while(!(readl(SDCC_DML_STATUS(dml_base)) & 1)); |
| 3034 | } |
| 3035 | |
| 3036 | /* Blocking function to wait until DML is idle. */ |
| 3037 | static void mmc_boot_dml_wait_consumer_idle() |
| 3038 | { |
| 3039 | while(!(readl(SDCC_DML_STATUS(dml_base)) & (1 << SDCC_DML_CONSUMER_IDLE_SHIFT))); |
| 3040 | } |
| 3041 | |
| 3042 | /* Initialize S/W reset */ |
| 3043 | static void mmc_boot_dml_reset() |
| 3044 | { |
| 3045 | /* Initialize s/w reset for DML core */ |
| 3046 | writel(1, SDCC_DML_SW_RESET(dml_base)); |
| 3047 | |
| 3048 | } |
| 3049 | |
| 3050 | static int mmc_bam_init(uint32_t bam_base) |
| 3051 | { |
| 3052 | |
| 3053 | uint32_t mmc_ret = MMC_BOOT_E_SUCCESS; |
| 3054 | |
| 3055 | bam.base = bam_base; |
| 3056 | /* Read pipe parameter initializations. */ |
| 3057 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].pipe_num = MMC_BOOT_BAM_READ_PIPE; |
| 3058 | /* System consumer */ |
| 3059 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].trans_type = BAM2SYS; |
| 3060 | /* Set the descriptor FIFO start ptr */ |
| 3061 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].fifo.head = desc_fifo; |
| 3062 | /* Set the descriptor FIFO lengths */ |
| 3063 | bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].fifo.size = MMC_BOOT_BAM_FIFO_SIZE; |
| 3064 | |
| 3065 | /* Write pipe parameter initializations.*/ |
| 3066 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].pipe_num = MMC_BOOT_BAM_WRITE_PIPE; |
| 3067 | /* System producer */ |
| 3068 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].trans_type = SYS2BAM; |
| 3069 | /* Write fifo uses the same fifo as read */ |
| 3070 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].fifo.head = desc_fifo; |
| 3071 | /* Set the descriptor FIFO lengths */ |
| 3072 | bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].fifo.size = MMC_BOOT_BAM_FIFO_SIZE; |
| 3073 | |
| 3074 | /* Programs the minimum threshold for BAM transfer*/ |
| 3075 | bam.threshold = BLOCK_SIZE; |
| 3076 | |
| 3077 | /* Initialize MMC BAM */ |
| 3078 | bam_init(&bam); |
| 3079 | |
| 3080 | /* Initialize BAM MMC read pipe */ |
| 3081 | bam_sys_pipe_init(&bam, MMC_BOOT_BAM_READ_PIPE_INDEX); |
| 3082 | |
| 3083 | mmc_ret = bam_pipe_fifo_init(&bam, bam.pipe[MMC_BOOT_BAM_READ_PIPE_INDEX].pipe_num); |
| 3084 | |
| 3085 | if (mmc_ret) |
| 3086 | { |
| 3087 | dprintf(CRITICAL, "MMC: BAM Read pipe fifo init error\n"); |
| 3088 | goto mmc_bam_init_error; |
| 3089 | } |
| 3090 | |
| 3091 | /* Initialize BAM MMC write pipe */ |
| 3092 | bam_sys_pipe_init(&bam, MMC_BOOT_BAM_WRITE_PIPE_INDEX); |
| 3093 | |
| 3094 | mmc_ret = bam_pipe_fifo_init(&bam, bam.pipe[MMC_BOOT_BAM_WRITE_PIPE_INDEX].pipe_num); |
| 3095 | |
| 3096 | if (mmc_ret) |
| 3097 | { |
| 3098 | dprintf(CRITICAL, "MMC: BAM Write pipe fifo init error\n"); |
| 3099 | goto mmc_bam_init_error; |
| 3100 | } |
| 3101 | |
| 3102 | mmc_boot_dml_init(); |
| 3103 | |
| 3104 | mmc_bam_init_error: |
| 3105 | |
| 3106 | return mmc_ret; |
| 3107 | } |
| 3108 | |
| 3109 | static int mmc_bam_transfer_data(unsigned int *data_ptr, |
| 3110 | unsigned int data_len, |
| 3111 | unsigned int dir) |
| 3112 | { |
| 3113 | uint32_t mmc_ret; |
| 3114 | uint32_t offset; |
| 3115 | |
| 3116 | mmc_ret = MMC_BOOT_E_SUCCESS; |
| 3117 | |
| 3118 | if(dir == MMC_BOOT_DATA_READ) |
| 3119 | { |
| 3120 | /* Check BAM IRQ status reg to verify the desc has been processed */ |
| 3121 | mmc_ret = bam_wait_for_interrupt(&bam, |
| 3122 | MMC_BOOT_BAM_READ_PIPE_INDEX, P_PRCSD_DESC_EN_MASK); |
| 3123 | |
| 3124 | if (mmc_ret != BAM_RESULT_SUCCESS) |
| 3125 | { |
| 3126 | dprintf(CRITICAL, "BAM transfer error \n"); |
| 3127 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 3128 | goto mmc_bam_transfer_err; |
| 3129 | } |
| 3130 | |
| 3131 | mmc_boot_dml_wait_producer_idle(); |
| 3132 | |
| 3133 | /* Update BAM pipe fifo offsets */ |
| 3134 | offset = bam_read_offset_update(&bam, MMC_BOOT_BAM_READ_PIPE_INDEX); |
| 3135 | |
| 3136 | /* Reset DPSM */ |
| 3137 | writel(0, MMC_BOOT_MCI_DATA_CTL); |
| 3138 | |
| 3139 | dprintf(SPEW, "Offset value is %d \n", offset); |
| 3140 | } |
| 3141 | else |
| 3142 | { |
| 3143 | /* Check BAM IRQ status reg to verify the desc has been processed */ |
| 3144 | mmc_ret = bam_wait_for_interrupt(&bam, |
| 3145 | MMC_BOOT_BAM_WRITE_PIPE_INDEX, P_TRNSFR_END_EN_MASK); |
| 3146 | |
| 3147 | if (mmc_ret != BAM_RESULT_SUCCESS) |
| 3148 | { |
| 3149 | dprintf(CRITICAL, "BAM transfer error \n"); |
| 3150 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 3151 | goto mmc_bam_transfer_err; |
| 3152 | } |
| 3153 | |
| 3154 | /* Update BAM pipe fifo offsets */ |
| 3155 | offset = bam_read_offset_update(&bam, MMC_BOOT_BAM_WRITE_PIPE_INDEX); |
| 3156 | |
| 3157 | dprintf(SPEW, "Offset value is %d \n", offset); |
| 3158 | } |
| 3159 | |
| 3160 | mmc_bam_transfer_err: |
| 3161 | |
| 3162 | return mmc_ret; |
| 3163 | } |
| 3164 | |
| 3165 | static unsigned int |
| 3166 | mmc_boot_bam_setup_desc(unsigned int *data_ptr, |
| 3167 | unsigned int data_len, |
| 3168 | unsigned char direction) |
| 3169 | { |
| 3170 | unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; |
| 3171 | |
| 3172 | if (direction == MMC_BOOT_DATA_READ) |
| 3173 | { |
| 3174 | mmc_boot_dml_producer_trans_init(1, data_len); |
| 3175 | mmc_ret = bam_add_desc(&bam, MMC_BOOT_BAM_READ_PIPE_INDEX, |
| 3176 | (unsigned char *)data_ptr, data_len); |
| 3177 | } |
| 3178 | else |
| 3179 | { |
| 3180 | mmc_boot_dml_consumer_trans_init(); |
| 3181 | mmc_ret = bam_add_desc(&bam, MMC_BOOT_BAM_WRITE_PIPE_INDEX, |
| 3182 | (unsigned char *)data_ptr, data_len); |
| 3183 | } |
| 3184 | |
| 3185 | /* Update return value enums */ |
| 3186 | if (mmc_ret != BAM_RESULT_SUCCESS) |
| 3187 | { |
| 3188 | dprintf(CRITICAL, "MMC BAM transfer error: %d\n", mmc_ret); |
| 3189 | mmc_ret = MMC_BOOT_E_FAILURE; |
| 3190 | } |
| 3191 | } |
| 3192 | |
| 3193 | #endif |