blob: 01fd07f9ba21bafbc2e70cea1cce0636b06e374f [file] [log] [blame]
Channagoud Kadabi0e60b7d2012-11-01 22:56:08 +05301/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
Deepa Dinamani22799652012-07-21 12:26:22 -07002
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
Channagoud Kadabi0e60b7d2012-11-01 22:56:08 +053012 * * Neither the name of The Linux Foundation, Inc. nor the names of its
Deepa Dinamani22799652012-07-21 12:26:22 -070013 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _PM8x41_HW_H_
30#define _PM8x41_HW_H_
31
Deepa Dinamani9a612932012-08-14 16:15:03 -070032/* SMBB Registers */
33#define SMBB_MISC_BOOT_DONE 0x1642
Deepa Dinamani22799652012-07-21 12:26:22 -070034
Deepa Dinamani9a612932012-08-14 16:15:03 -070035/* SMBB bit values */
36#define BOOT_DONE_BIT 7
37
38
39/* GPIO Registers */
40#define GPIO_PERIPHERAL_BASE 0xC000
41/* Peripheral base address for GPIO_X */
42#define GPIO_N_PERIPHERAL_BASE(x) (GPIO_PERIPHERAL_BASE + ((x) - 1) * 0x100)
43
44/* Register offsets within GPIO */
45#define GPIO_STATUS 0x08
46#define GPIO_MODE_CTL 0x40
47#define GPIO_DIG_VIN_CTL 0x41
48#define GPIO_DIG_PULL_CTL 0x42
49#define GPIO_DIG_OUT_CTL 0x45
50#define GPIO_EN_CTL 0x46
51
52/* GPIO bit values */
53#define PERPH_EN_BIT 7
54#define GPIO_STATUS_VAL_BIT 0
55
56
57/* PON Peripheral registers */
58#define PON_INT_RT_STS 0x810
59#define PON_INT_SET_TYPE 0x811
60#define PON_INT_POLARITY_HIGH 0x812
61#define PON_INT_POLARITY_LOW 0x813
62#define PON_INT_LATCHED_CLR 0x814
63#define PON_INT_EN_SET 0x815
64#define PON_INT_LATCHED_STS 0x818
65#define PON_INT_PENDING_STS 0x819
66#define PON_RESIN_N_RESET_S1_TIMER 0x844 /* bits 0:3 : S1_TIMER */
67#define PON_RESIN_N_RESET_S2_TIMER 0x845 /* bits 0:2 : S2_TIMER */
68#define PON_RESIN_N_RESET_S2_CTL 0x846 /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
Neeti Desai120b55d2012-08-20 17:15:56 -070069#define PON_PS_HOLD_RESET_CTL 0x85A /* bit 7: S2_RESET_EN, bit 0:3 : RESET_TYPE */
Deepa Dinamani9a612932012-08-14 16:15:03 -070070
71/* PON Peripheral register bit values */
72#define RESIN_BARK_INT_BIT 4
73#define S2_RESET_EN_BIT 7
74
75#define S2_RESET_TYPE_WARM 0x1
76#define PON_RESIN_N_RESET_S2_TIMER_MAX_VALUE 0x7
Deepa Dinamani22799652012-07-21 12:26:22 -070077
Channagoud Kadabi0e60b7d2012-11-01 22:56:08 +053078/* LDO voltage ranges */
79#define NLDO_UV_MIN 375000
80#define NLDO_UV_MAX 1537500
81#define NLDO_UV_STEP 12500
82#define NLDO_UV_VMIN_LOW 750000
83
84#define PLDO_UV_VMIN_LOW 750000
85#define PLDO_UV_VMIN_MID 1500000
86#define PLDO_UV_VMIN_HIGH 1750000
87
88#define PLDO_UV_MIN 1537500
89#define PDLO_UV_MID 3075000
90#define PLDO_UV_MAX 4900000
91#define PLDO_UV_STEP_LOW 12500
92#define PLDO_UV_STEP_MID 25000
93#define PLDO_UV_STEP_HIGH 50000
94
95#define LDO_RANGE_SEL_BIT 0
96#define LDO_VSET_SEL_BIT 0
97#define LDO_VREG_ENABLE_BIT 7
98#define LDO_NORMAL_PWR_BIT 7
99
100#define LDO_RANGE_CTRL 0x40
101#define LDO_STEP_CTRL 0x41
102#define LDO_POWER_MODE 0x45
103#define LDO_EN_CTL_REG 0x46
104
105#define PLDO_TYPE 0
106#define NLDO_TYPE 1
107
108#define LDO(_name, _type, _base, _range, _step, _enable) \
109{ \
110 .name = _name, \
111 .type = _type, \
112 .base = _base, \
113 .range_reg = _range, \
114 .step_reg = _step, \
115 .enable_reg = _enable, \
116}
117
Deepa Dinamani22799652012-07-21 12:26:22 -0700118#endif