Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 43 | #define MDP_MIN_FETCH 9 |
| 44 | #define MDSS_MDP_MAX_FETCH 12 |
| 45 | |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 46 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 47 | |
| 48 | static int mdp_rev; |
| 49 | |
| 50 | void mdp_set_revision(int rev) |
| 51 | { |
| 52 | mdp_rev = rev; |
| 53 | } |
| 54 | |
| 55 | int mdp_get_revision() |
| 56 | { |
| 57 | return mdp_rev; |
| 58 | } |
| 59 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 60 | uint32_t mdss_mdp_intf_offset() |
| 61 | { |
| 62 | uint32_t mdss_mdp_intf_off; |
| 63 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 64 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 65 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 66 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 67 | mdss_mdp_intf_off = 0x59100; |
| 68 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 69 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 70 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 71 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 72 | |
| 73 | return mdss_mdp_intf_off; |
| 74 | } |
| 75 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 76 | void mdp_clk_gating_ctrl(void) |
| 77 | { |
| 78 | writel(0x40000000, MDP_CLK_CTRL0); |
| 79 | udelay(20); |
| 80 | writel(0x40000040, MDP_CLK_CTRL0); |
| 81 | writel(0x40000000, MDP_CLK_CTRL1); |
| 82 | writel(0x00400000, MDP_CLK_CTRL3); |
| 83 | udelay(20); |
| 84 | writel(0x00404000, MDP_CLK_CTRL3); |
| 85 | writel(0x40000000, MDP_CLK_CTRL4); |
| 86 | } |
| 87 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 88 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 89 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 90 | { |
| 91 | switch (pinfo->pipe_type) { |
| 92 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 93 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 94 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 95 | break; |
| 96 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 97 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 98 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 99 | break; |
| 100 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 101 | default: |
| 102 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 103 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 104 | break; |
| 105 | } |
| 106 | } |
| 107 | |
| 108 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 109 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 110 | { |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 111 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 112 | switch (pinfo->pipe_type) { |
| 113 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 114 | *ctl0_reg_val = 0x22048; |
| 115 | *ctl1_reg_val = 0x24090; |
| 116 | break; |
| 117 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 118 | *ctl0_reg_val = 0x22840; |
| 119 | *ctl1_reg_val = 0x25080; |
| 120 | break; |
| 121 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 122 | default: |
| 123 | *ctl0_reg_val = 0x22041; |
| 124 | *ctl1_reg_val = 0x24082; |
| 125 | break; |
| 126 | } |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 127 | /* For targets from MDP v1.5, MDP INTF registers are double buffered */ |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 128 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 129 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) { |
| 130 | *ctl0_reg_val |= BIT(30); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 131 | *ctl1_reg_val |= BIT(31); |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame^] | 132 | } else if ((mdss_mdp_rev == MDSS_MDP_HW_REV_105) || |
| 133 | (mdss_mdp_rev == MDSS_MDP_HW_REV_109)) { |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 134 | *ctl0_reg_val |= BIT(30); |
| 135 | *ctl1_reg_val |= BIT(29); |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 136 | } |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 137 | } |
| 138 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 139 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 140 | *pinfo, uint32_t pipe_base) |
| 141 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 142 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 143 | uint32_t fb_off = 0; |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 144 | uint32_t flip_bits = 0; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 145 | |
| 146 | /* write active region size*/ |
| 147 | src_size = (fb->height << 16) + fb->width; |
| 148 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 149 | if (pinfo->lcdc.dual_pipe) { |
| 150 | out_size = (fb->height << 16) + (fb->width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 151 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 152 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 153 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 154 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | stride = (fb->stride * fb->bpp/8); |
| 158 | |
| 159 | writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
| 160 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 161 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 162 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 163 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 164 | writel(fb_off, pipe_base + PIPE_SSPP_SRC_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 165 | writel(0x00, pipe_base + PIPE_SSPP_OUT_XY); |
| 166 | |
| 167 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 168 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 169 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
Prashant Nukala | 64eeff9 | 2014-07-11 07:35:34 +0530 | [diff] [blame] | 170 | |
| 171 | /* bit(0) is set if hflip is required. |
| 172 | * bit(1) is set if vflip is required. |
| 173 | */ |
| 174 | if (pinfo->orientation & 0x1) |
| 175 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_LR; |
| 176 | if (pinfo->orientation & 0x2) |
| 177 | flip_bits |= MDSS_MDP_OP_MODE_FLIP_UD; |
| 178 | writel(flip_bits, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 179 | } |
| 180 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 181 | static void mdss_vbif_setup() |
| 182 | { |
| 183 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 184 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 185 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 186 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 187 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 188 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 189 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 190 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 191 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 192 | |
| 193 | /* |
| 194 | * Following configuration is needed because on some versions, |
| 195 | * recommended reset values are not stored. |
| 196 | */ |
| 197 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 198 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 199 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 200 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 201 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 202 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 203 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 204 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 205 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 206 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 207 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 208 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 209 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 210 | } |
| 211 | } |
| 212 | } |
| 213 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 214 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 215 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 216 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 217 | uint32_t i, j; |
| 218 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 219 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 220 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 221 | /* max 3 MMB per register */ |
| 222 | reg_val |= client_id << (((j++) % 3) * 8); |
| 223 | if ((j % 3) == 0) { |
| 224 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 225 | free_smp_offset); |
| 226 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 227 | free_smp_offset); |
| 228 | reg_val = 0; |
| 229 | free_smp_offset += 4; |
| 230 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 231 | } |
| 232 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 233 | if (j % 3) { |
| 234 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 235 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 236 | free_smp_offset += 4; |
| 237 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 238 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 239 | return free_smp_offset; |
| 240 | } |
| 241 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 242 | static void mdp_select_pipe_client_id(struct msm_panel_info *pinfo, |
| 243 | uint32_t *left_sspp_client_id, uint32_t *right_sspp_client_id) |
| 244 | { |
| 245 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 246 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
| 247 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
| 248 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108)) { |
| 249 | switch (pinfo->pipe_type) { |
| 250 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 251 | *left_sspp_client_id = 0x7; /* 7 */ |
| 252 | *right_sspp_client_id = 0x11; /* 17 */ |
| 253 | break; |
| 254 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 255 | *left_sspp_client_id = 0x4; /* 4 */ |
| 256 | *right_sspp_client_id = 0xD; /* 13 */ |
| 257 | break; |
| 258 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 259 | default: |
| 260 | *left_sspp_client_id = 0x1; /* 1 */ |
| 261 | *right_sspp_client_id = 0x4; /* 4 */ |
| 262 | break; |
| 263 | } |
| 264 | } else { |
| 265 | switch (pinfo->pipe_type) { |
| 266 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 267 | *left_sspp_client_id = 0x10; /* 16 */ |
| 268 | *right_sspp_client_id = 0x11; /* 17 */ |
| 269 | break; |
| 270 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 271 | *left_sspp_client_id = 0xA; /* 10 */ |
| 272 | *right_sspp_client_id = 0xD; /* 13 */ |
| 273 | break; |
| 274 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 275 | default: |
| 276 | *left_sspp_client_id = 0x1; /* 1 */ |
| 277 | *right_sspp_client_id = 0x4; /* 4 */ |
| 278 | break; |
| 279 | } |
| 280 | } |
| 281 | } |
| 282 | |
| 283 | static void mdp_select_pipe_xin_id(struct msm_panel_info *pinfo, |
| 284 | uint32_t *left_pipe_xin_id, uint32_t *right_pipe_xin_id) |
| 285 | { |
| 286 | switch (pinfo->pipe_type) { |
| 287 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 288 | *left_pipe_xin_id = 0x1; /* 1 */ |
| 289 | *right_pipe_xin_id = 0x5; /* 5 */ |
| 290 | break; |
| 291 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 292 | *left_pipe_xin_id = 0x2; /* 2 */ |
| 293 | *right_pipe_xin_id = 0xA; /* 10 */ |
| 294 | break; |
| 295 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 296 | default: |
| 297 | *left_pipe_xin_id = 0x0; /* 0 */ |
| 298 | *right_pipe_xin_id = 0x4; /* 4 */ |
| 299 | break; |
| 300 | } |
| 301 | } |
| 302 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 303 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 304 | uint32_t right_pipe) |
| 305 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 306 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 307 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 308 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 309 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 310 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 311 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 312 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) { |
| 313 | /* 8Kb per SMP on 8916 */ |
| 314 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 315 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 316 | /* 10Kb per SMP on 8939 */ |
| 317 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 318 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 319 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 320 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 321 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 322 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 323 | fixed_smp_cnt = 2; |
| 324 | else |
| 325 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 326 | } |
| 327 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 328 | mdp_select_pipe_client_id(pinfo, |
| 329 | &left_sspp_client_id, &right_sspp_client_id); |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 330 | |
| 331 | /* Each pipe driving half the screen */ |
| 332 | if (pinfo->lcdc.dual_pipe) |
| 333 | xres /= 2; |
| 334 | |
| 335 | /* bpp = bytes per pixel of input image */ |
| 336 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 337 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 338 | |
| 339 | if (smp_cnt > 4) { |
| 340 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 341 | smp_cnt); |
| 342 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 343 | } |
| 344 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 345 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 346 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 347 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 348 | |
| 349 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 350 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 351 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 352 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 353 | } |
| 354 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 355 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 356 | fixed_smp_cnt, free_smp_offset); |
| 357 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 358 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 359 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 360 | } |
| 361 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 362 | void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 363 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 364 | uint32_t hsync_period, vsync_period; |
| 365 | uint32_t hsync_start_x, hsync_end_x; |
| 366 | uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 367 | uint32_t mdss_mdp_intf_off; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 368 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 369 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 370 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 371 | |
| 372 | if (pinfo == NULL) |
| 373 | return ERR_INVALID_ARGS; |
| 374 | |
| 375 | lcdc = &(pinfo->lcdc); |
| 376 | if (lcdc == NULL) |
| 377 | return ERR_INVALID_ARGS; |
| 378 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 379 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 380 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 381 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 382 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 383 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 384 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 385 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 386 | } |
| 387 | } |
| 388 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 389 | if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) { |
| 390 | writel(BIT(16), MDP_REG_PPB0_CONFIG); |
| 391 | writel(BIT(5), MDP_REG_PPB0_CNTL); |
| 392 | } |
| 393 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 394 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 395 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 396 | hsync_period = lcdc->h_pulse_width + |
| 397 | lcdc->h_back_porch + |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 398 | adjust_xres + lcdc->xres_pad + lcdc->h_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 399 | vsync_period = (lcdc->v_pulse_width + |
| 400 | lcdc->v_back_porch + |
| 401 | pinfo->yres + lcdc->yres_pad + |
| 402 | lcdc->v_front_porch); |
| 403 | |
| 404 | hsync_start_x = |
| 405 | lcdc->h_pulse_width + |
| 406 | lcdc->h_back_porch; |
| 407 | hsync_end_x = |
| 408 | hsync_period - lcdc->h_front_porch - 1; |
| 409 | |
| 410 | display_vstart = (lcdc->v_pulse_width + |
| 411 | lcdc->v_back_porch) |
| 412 | * hsync_period + lcdc->hsync_skew; |
| 413 | display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period) |
| 414 | +lcdc->hsync_skew - 1; |
| 415 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 416 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
| 417 | display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch; |
| 418 | display_vend -= lcdc->h_front_porch; |
| 419 | } |
| 420 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 421 | hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width; |
| 422 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 423 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 424 | writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off); |
| 425 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
| 426 | mdss_mdp_intf_off); |
| 427 | writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off); |
| 428 | writel(lcdc->v_pulse_width*hsync_period, |
| 429 | MDP_VSYNC_PULSE_WIDTH_F0 + |
| 430 | mdss_mdp_intf_off); |
| 431 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off); |
| 432 | writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off); |
| 433 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
| 434 | mdss_mdp_intf_off); |
| 435 | writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off); |
| 436 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
| 437 | mdss_mdp_intf_off); |
| 438 | writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off); |
| 439 | writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off); |
| 440 | writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off); |
| 441 | writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off); |
| 442 | writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off); |
| 443 | writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off); |
| 444 | writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off); |
| 445 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 446 | if (intf_base == MDP_INTF_0_BASE) /* eDP */ |
| 447 | writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
| 448 | else |
| 449 | writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 450 | } |
| 451 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 452 | void mdss_intf_fetch_start_config(struct msm_panel_info *pinfo, |
| 453 | uint32_t intf_base) |
| 454 | { |
| 455 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 456 | uint32_t mdss_mdp_intf_off; |
| 457 | uint32_t v_total, h_total, fetch_start, vfp_start, fetch_lines; |
| 458 | uint32_t adjust_xres = 0; |
| 459 | |
| 460 | struct lcdc_panel_info *lcdc = NULL; |
| 461 | |
| 462 | if (pinfo == NULL) |
| 463 | return; |
| 464 | |
| 465 | lcdc = &(pinfo->lcdc); |
| 466 | if (lcdc == NULL) |
| 467 | return; |
| 468 | |
| 469 | /* |
| 470 | * MDP programmable fetch is for MDP with rev >= 1.05. |
| 471 | * Programmable fetch is not needed if vertical back porch |
| 472 | * is >= 9. |
| 473 | */ |
| 474 | if (mdp_hw_rev < MDSS_MDP_HW_REV_105 || |
| 475 | lcdc->v_back_porch >= MDP_MIN_FETCH) |
| 476 | return; |
| 477 | |
| 478 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 479 | |
| 480 | adjust_xres = pinfo->xres; |
| 481 | if (pinfo->lcdc.split_display) |
| 482 | adjust_xres /= 2; |
| 483 | |
| 484 | /* |
| 485 | * Fetch should always be outside the active lines. If the fetching |
| 486 | * is programmed within active region, hardware behavior is unknown. |
| 487 | */ |
| 488 | v_total = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres + |
| 489 | lcdc->v_front_porch; |
| 490 | h_total = lcdc->h_pulse_width + lcdc->h_back_porch + adjust_xres + |
| 491 | lcdc->h_front_porch; |
| 492 | vfp_start = lcdc->v_pulse_width + lcdc->v_back_porch + pinfo->yres; |
| 493 | |
| 494 | fetch_lines = v_total - vfp_start; |
| 495 | |
| 496 | /* |
| 497 | * In some cases, vertical front porch is too high. In such cases limit |
| 498 | * the mdp fetch lines as the last 12 lines of vertical front porch. |
| 499 | */ |
| 500 | if (fetch_lines > MDSS_MDP_MAX_FETCH) |
| 501 | fetch_lines = MDSS_MDP_MAX_FETCH; |
| 502 | |
| 503 | fetch_start = (v_total - fetch_lines) * h_total + 1; |
| 504 | |
| 505 | writel(fetch_start, MDP_PROG_FETCH_START + mdss_mdp_intf_off); |
| 506 | writel(BIT(31), MDP_INTF_CONFIG + mdss_mdp_intf_off); |
| 507 | } |
| 508 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 509 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 510 | *pinfo) |
| 511 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 512 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 513 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 514 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 515 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 516 | width = fb->width; |
| 517 | |
| 518 | if (pinfo->lcdc.dual_pipe) |
| 519 | width /= 2; |
| 520 | |
| 521 | /* write active region size*/ |
| 522 | mdp_rgb_size = (height << 16) | width; |
| 523 | |
| 524 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 525 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 526 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 527 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 528 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 529 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 530 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 531 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 532 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 533 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 534 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 535 | switch (pinfo->pipe_type) { |
| 536 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 537 | left_staging_level = 0x0000200; |
| 538 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 539 | break; |
| 540 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 541 | left_staging_level = 0x0040000; |
| 542 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 543 | break; |
| 544 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 545 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 546 | left_staging_level = 0x1; |
| 547 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 548 | break; |
| 549 | } |
| 550 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 551 | /* Base layer for layer mixer 0 */ |
| 552 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 553 | |
| 554 | if (pinfo->lcdc.dual_pipe) { |
| 555 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 556 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 557 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 558 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 559 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 560 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 561 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 562 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 563 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 564 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 565 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 566 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 567 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 568 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 569 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 570 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 571 | } |
| 572 | } |
| 573 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 574 | void mdss_qos_remapper_setup(void) |
| 575 | { |
| 576 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 577 | uint32_t map; |
| 578 | |
| 579 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 580 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 581 | MDSS_MDP_HW_REV_102)) |
| 582 | map = 0xE9; |
| 583 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 584 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 585 | map = 0xA5; |
| 586 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 587 | MDSS_MDP_HW_REV_106) || |
| 588 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 589 | MDSS_MDP_HW_REV_108)) |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 590 | map = 0xE4; |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 591 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame^] | 592 | MDSS_MDP_HW_REV_105) || |
| 593 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 594 | MDSS_MDP_HW_REV_109)) |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 595 | map = 0xA4; |
| 596 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 597 | MDSS_MDP_HW_REV_103)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 598 | map = 0xFA; |
| 599 | else |
| 600 | return; |
| 601 | |
| 602 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 603 | } |
| 604 | |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 605 | void mdss_vbif_qos_remapper_setup(struct msm_panel_info *pinfo) |
| 606 | { |
| 607 | uint32_t mask, reg_val, i; |
| 608 | uint32_t left_pipe_xin_id, right_pipe_xin_id; |
| 609 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 610 | uint32_t vbif_qos[4] = {0, 0, 0, 0}; |
| 611 | |
| 612 | mdp_select_pipe_xin_id(pinfo, |
| 613 | &left_pipe_xin_id, &right_pipe_xin_id); |
| 614 | |
| 615 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106) || |
| 616 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_108)) { |
| 617 | vbif_qos[0] = 2; |
| 618 | vbif_qos[1] = 2; |
| 619 | vbif_qos[2] = 2; |
| 620 | vbif_qos[3] = 2; |
Chandan Uddaraju | 18a5037 | 2014-10-01 18:45:30 -0700 | [diff] [blame^] | 621 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_105) || |
| 622 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_109)) { |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 623 | vbif_qos[0] = 1; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 624 | vbif_qos[1] = 2; |
| 625 | vbif_qos[2] = 2; |
Ingrid Gallardo | 998ea44 | 2014-09-10 17:22:08 -0700 | [diff] [blame] | 626 | vbif_qos[3] = 2; |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 627 | } else { |
| 628 | return; |
| 629 | } |
| 630 | |
| 631 | for (i = 0; i < 4; i++) { |
| 632 | reg_val = readl(VBIF_VBIF_QOS_REMAP_00 + i*4); |
| 633 | mask = 0x3 << (left_pipe_xin_id * 2); |
| 634 | reg_val &= ~(mask); |
| 635 | reg_val |= vbif_qos[i] << (left_pipe_xin_id * 2); |
| 636 | |
| 637 | if (pinfo->lcdc.dual_pipe) { |
| 638 | mask = 0x3 << (right_pipe_xin_id * 2); |
| 639 | reg_val &= ~(mask); |
| 640 | reg_val |= vbif_qos[i] << (right_pipe_xin_id * 2); |
| 641 | } |
| 642 | writel(reg_val, VBIF_VBIF_QOS_REMAP_00 + i*4); |
| 643 | } |
| 644 | } |
| 645 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 646 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 647 | int is_main_ctl) |
| 648 | { |
| 649 | if (pinfo->lcdc.pipe_swap) { |
| 650 | if (is_main_ctl) |
| 651 | return BIT(4) | BIT(5); /* Interface 2 */ |
| 652 | else |
| 653 | return BIT(5); /* Interface 1 */ |
| 654 | } else { |
| 655 | if (is_main_ctl) |
| 656 | return BIT(5); /* Interface 1 */ |
| 657 | else |
| 658 | return BIT(4) | BIT(5); /* Interface 2 */ |
| 659 | } |
| 660 | } |
| 661 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 662 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 663 | struct fbcon_config *fb) |
| 664 | { |
| 665 | int ret = NO_ERROR; |
| 666 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 667 | uint32_t intf_sel = 0x100; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 668 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 669 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 670 | |
| 671 | mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 672 | mdss_intf_fetch_start_config(pinfo, MDP_INTF_1_BASE); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 673 | |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 674 | if (pinfo->mipi.dual_dsi) { |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 675 | mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); |
Padmanabhan Komanduru | 9f546ab | 2014-09-10 19:56:30 +0530 | [diff] [blame] | 676 | mdss_intf_fetch_start_config(pinfo, MDP_INTF_2_BASE); |
| 677 | } |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 678 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 679 | mdp_clk_gating_ctrl(); |
| 680 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 681 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 682 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 683 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 684 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 685 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 686 | mdss_vbif_qos_remapper_setup(pinfo); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 687 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 688 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 689 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 690 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 691 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 692 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 693 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 694 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 695 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 696 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 697 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 698 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 699 | CTL_1 path should not be set since CTL_0 itself is going |
| 700 | to split after DSPP block*/ |
| 701 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 702 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 703 | if (!pinfo->lcdc.dst_split) { |
| 704 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 705 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 706 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 707 | intf_sel |= BIT(16); /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 708 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 709 | |
| 710 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 711 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 712 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 713 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 714 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 715 | |
| 716 | return 0; |
| 717 | } |
| 718 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 719 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 720 | { |
| 721 | int ret = NO_ERROR; |
| 722 | struct lcdc_panel_info *lcdc = NULL; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 723 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 724 | |
| 725 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 726 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 727 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 728 | mdp_clk_gating_ctrl(); |
| 729 | |
| 730 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 731 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 732 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 733 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 734 | mdss_vbif_qos_remapper_setup(pinfo); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 735 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 736 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 737 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 738 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 739 | |
| 740 | mdss_layer_mixer_setup(fb, pinfo); |
| 741 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 742 | if (pinfo->lcdc.dual_pipe) |
| 743 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 744 | else |
| 745 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 746 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 747 | writel(0x9, MDP_DISP_INTF_SEL); |
| 748 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 749 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 750 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 751 | |
| 752 | return 0; |
| 753 | } |
| 754 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 755 | int mdss_hdmi_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 756 | { |
| 757 | int ret = NO_ERROR; |
| 758 | struct lcdc_panel_info *lcdc = NULL; |
| 759 | uint32_t left_pipe, right_pipe; |
| 760 | |
| 761 | mdss_intf_tg_setup(pinfo, MDP_INTF_3_BASE); |
| 762 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
| 763 | |
| 764 | mdp_clk_gating_ctrl(); |
| 765 | mdss_vbif_setup(); |
| 766 | |
| 767 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
| 768 | |
| 769 | mdss_qos_remapper_setup(); |
| 770 | |
| 771 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 772 | if (pinfo->lcdc.dual_pipe) |
| 773 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
| 774 | |
| 775 | mdss_layer_mixer_setup(fb, pinfo); |
| 776 | |
| 777 | if (pinfo->lcdc.dual_pipe) |
| 778 | writel(0x181F40, MDP_CTL_0_BASE + CTL_TOP); |
| 779 | else |
| 780 | writel(0x40, MDP_CTL_0_BASE + CTL_TOP); |
| 781 | |
| 782 | writel(BIT(24) | BIT(25), MDP_DISP_INTF_SEL); |
| 783 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 784 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 785 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 786 | |
| 787 | return 0; |
| 788 | } |
| 789 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 790 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 791 | struct fbcon_config *fb) |
| 792 | { |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 793 | uint32_t intf_sel = BIT(8); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 794 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 795 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 796 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 797 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 798 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 799 | uint32_t mdss_mdp_intf_off = 0; |
| 800 | |
| 801 | if (pinfo == NULL) |
| 802 | return ERR_INVALID_ARGS; |
| 803 | |
| 804 | lcdc = &(pinfo->lcdc); |
| 805 | if (lcdc == NULL) |
| 806 | return ERR_INVALID_ARGS; |
| 807 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 808 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 809 | reg = BIT(1); /* Command mode */ |
| 810 | if (pinfo->lcdc.pipe_swap) |
| 811 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 812 | else |
| 813 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 814 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 815 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 816 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 817 | } |
| 818 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 819 | mdss_mdp_intf_off = mdss_mdp_intf_offset(); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 820 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 821 | mdp_clk_gating_ctrl(); |
| 822 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 823 | if (pinfo->mipi.dual_dsi) |
| 824 | intf_sel |= BIT(16); /* INTF 2 enable */ |
| 825 | |
| 826 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 827 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 828 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 829 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 830 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 831 | mdss_qos_remapper_setup(); |
Jayant Shekhar | 2db7dc5 | 2014-08-21 10:43:30 +0530 | [diff] [blame] | 832 | mdss_vbif_qos_remapper_setup(pinfo); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 833 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 834 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 835 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 836 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 837 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 838 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 839 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 840 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 841 | writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 842 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 843 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 844 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 845 | if (pinfo->mipi.dual_dsi) { |
| 846 | writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 847 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 848 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 849 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 850 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 851 | return ret; |
| 852 | } |
| 853 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 854 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 855 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 856 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 857 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 858 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 859 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 860 | writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 861 | |
| 862 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 863 | } |
| 864 | |
| 865 | int mdp_dsi_video_off() |
| 866 | { |
| 867 | if(!target_cont_splash_screen()) |
| 868 | { |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 869 | writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN + |
| 870 | mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 871 | mdelay(60); |
| 872 | /* Ping-Pong done Tear Check Read/Write */ |
| 873 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 874 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 875 | } |
| 876 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 877 | writel(0x00000000, MDP_INTR_EN); |
| 878 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 879 | return NO_ERROR; |
| 880 | } |
| 881 | |
| 882 | int mdp_dsi_cmd_off() |
| 883 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 884 | if(!target_cont_splash_screen()) |
| 885 | { |
| 886 | /* Ping-Pong done Tear Check Read/Write */ |
| 887 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 888 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 889 | } |
| 890 | writel(0x00000000, MDP_INTR_EN); |
| 891 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 892 | return NO_ERROR; |
| 893 | } |
| 894 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 895 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 896 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 897 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 898 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 899 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 900 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 901 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 902 | return NO_ERROR; |
| 903 | } |
| 904 | |
| 905 | void mdp_disable(void) |
| 906 | { |
| 907 | |
| 908 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 909 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 910 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 911 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 912 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 913 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 914 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 915 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 916 | return NO_ERROR; |
| 917 | } |
| 918 | |
Ajay Singh Parmar | 243d82b | 2014-07-23 23:01:44 -0700 | [diff] [blame] | 919 | int mdss_hdmi_on(struct msm_panel_info *pinfo) |
Ajay Singh Parmar | 63c1850 | 2014-07-23 23:37:19 -0700 | [diff] [blame] | 920 | { |
| 921 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 922 | |
| 923 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
| 924 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 925 | |
| 926 | writel(0x01, MDP_INTF_3_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 927 | |
| 928 | return NO_ERROR; |
| 929 | } |
| 930 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 931 | int mdp_edp_off(void) |
| 932 | { |
| 933 | if (!target_cont_splash_screen()) { |
| 934 | |
| 935 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 936 | mdss_mdp_intf_offset()); |
| 937 | mdelay(60); |
| 938 | /* Ping-Pong done Tear Check Read/Write */ |
| 939 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 940 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 941 | writel(0x00000000, MDP_INTR_EN); |
| 942 | } |
| 943 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 944 | writel(0x00000000, MDP_INTR_EN); |
| 945 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 946 | return NO_ERROR; |
| 947 | } |