Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2014, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <assert.h> |
| 30 | #include <reg.h> |
| 31 | #include <err.h> |
| 32 | #include <clock.h> |
| 33 | #include <clock_pll.h> |
| 34 | #include <clock_lib2.h> |
| 35 | #include <platform/clock.h> |
| 36 | #include <platform/iomap.h> |
| 37 | |
| 38 | |
| 39 | /* Mux source select values */ |
| 40 | #define cxo_source_val 0 |
| 41 | #define gpll0_source_val 1 |
| 42 | #define usb30_pipe_source_val 2 |
| 43 | |
| 44 | struct clk_freq_tbl rcg_dummy_freq = F_END; |
| 45 | |
| 46 | |
| 47 | /* Clock Operations */ |
| 48 | static struct clk_ops clk_ops_reset = |
| 49 | { |
| 50 | .reset = clock_lib2_reset_clk_reset, |
| 51 | }; |
| 52 | |
| 53 | static struct clk_ops clk_ops_branch = |
| 54 | { |
| 55 | .enable = clock_lib2_branch_clk_enable, |
| 56 | .disable = clock_lib2_branch_clk_disable, |
| 57 | .set_rate = clock_lib2_branch_set_rate, |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 58 | .reset = clock_lib2_branch_clk_reset, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
| 61 | static struct clk_ops clk_ops_rcg_mnd = |
| 62 | { |
| 63 | .enable = clock_lib2_rcg_enable, |
| 64 | .set_rate = clock_lib2_rcg_set_rate, |
| 65 | }; |
| 66 | |
| 67 | static struct clk_ops clk_ops_rcg = |
| 68 | { |
| 69 | .enable = clock_lib2_rcg_enable, |
| 70 | .set_rate = clock_lib2_rcg_set_rate, |
| 71 | }; |
| 72 | |
| 73 | static struct clk_ops clk_ops_cxo = |
| 74 | { |
| 75 | .enable = cxo_clk_enable, |
| 76 | .disable = cxo_clk_disable, |
| 77 | }; |
| 78 | |
| 79 | static struct clk_ops clk_ops_pll_vote = |
| 80 | { |
| 81 | .enable = pll_vote_clk_enable, |
| 82 | .disable = pll_vote_clk_disable, |
| 83 | .auto_off = pll_vote_clk_disable, |
| 84 | .is_enabled = pll_vote_clk_is_enabled, |
| 85 | }; |
| 86 | |
| 87 | static struct clk_ops clk_ops_vote = |
| 88 | { |
| 89 | .enable = clock_lib2_vote_clk_enable, |
| 90 | .disable = clock_lib2_vote_clk_disable, |
| 91 | }; |
| 92 | |
| 93 | /* Clock Sources */ |
| 94 | static struct fixed_clk cxo_clk_src = |
| 95 | { |
| 96 | .c = { |
| 97 | .rate = 19200000, |
| 98 | .dbg_name = "cxo_clk_src", |
| 99 | .ops = &clk_ops_cxo, |
| 100 | }, |
| 101 | }; |
| 102 | |
| 103 | static struct pll_vote_clk gpll0_clk_src = |
| 104 | { |
| 105 | .en_reg = (void *) APCS_GPLL_ENA_VOTE, |
| 106 | .en_mask = BIT(0), |
| 107 | .status_reg = (void *) GPLL0_STATUS, |
| 108 | .status_mask = BIT(30), |
| 109 | .parent = &cxo_clk_src.c, |
| 110 | |
| 111 | .c = { |
| 112 | .rate = 800000000, |
| 113 | .dbg_name = "gpll0_clk_src", |
| 114 | .ops = &clk_ops_pll_vote, |
| 115 | }, |
| 116 | }; |
| 117 | |
| 118 | /* SDCC Clocks */ |
| 119 | static struct clk_freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = |
| 120 | { |
| 121 | F( 144000, cxo, 16, 3, 25), |
| 122 | F( 400000, cxo, 12, 1, 4), |
Joonwoo Park | 095007a | 2014-06-27 17:57:45 -0700 | [diff] [blame] | 123 | F( 20000000, gpll0, 15, 1, 2), |
| 124 | F( 25000000, gpll0, 12, 1, 2), |
| 125 | F( 50000000, gpll0, 12, 0, 0), |
| 126 | F(100000000, gpll0, 6, 0, 0), |
| 127 | F(200000000, gpll0, 3, 0, 0), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 128 | F_END |
| 129 | }; |
| 130 | |
| 131 | static struct rcg_clk sdcc1_apps_clk_src = |
| 132 | { |
| 133 | .cmd_reg = (uint32_t *) SDCC1_CMD_RCGR, |
| 134 | .cfg_reg = (uint32_t *) SDCC1_CFG_RCGR, |
| 135 | .m_reg = (uint32_t *) SDCC1_M, |
| 136 | .n_reg = (uint32_t *) SDCC1_N, |
| 137 | .d_reg = (uint32_t *) SDCC1_D, |
| 138 | |
| 139 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 140 | .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, |
| 141 | .current_freq = &rcg_dummy_freq, |
| 142 | |
| 143 | .c = { |
| 144 | .dbg_name = "sdc1_clk", |
| 145 | .ops = &clk_ops_rcg_mnd, |
| 146 | }, |
| 147 | }; |
| 148 | |
| 149 | static struct branch_clk gcc_sdcc1_apps_clk = |
| 150 | { |
| 151 | .cbcr_reg = (uint32_t *) SDCC1_APPS_CBCR, |
| 152 | .parent = &sdcc1_apps_clk_src.c, |
| 153 | |
| 154 | .c = { |
| 155 | .dbg_name = "gcc_sdcc1_apps_clk", |
| 156 | .ops = &clk_ops_branch, |
| 157 | }, |
| 158 | }; |
| 159 | |
| 160 | static struct branch_clk gcc_sdcc1_ahb_clk = |
| 161 | { |
| 162 | .cbcr_reg = (uint32_t *) SDCC1_AHB_CBCR, |
| 163 | .has_sibling = 1, |
| 164 | |
| 165 | .c = { |
| 166 | .dbg_name = "gcc_sdcc1_ahb_clk", |
| 167 | .ops = &clk_ops_branch, |
| 168 | }, |
| 169 | }; |
| 170 | |
| 171 | /* UART Clocks */ |
| 172 | static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_6_apps_clk[] = |
| 173 | { |
Joonwoo Park | 095007a | 2014-06-27 17:57:45 -0700 | [diff] [blame] | 174 | F( 3686400, gpll0, 1, 96, 15625), |
| 175 | F( 7372800, gpll0, 1, 192, 15625), |
| 176 | F(14745600, gpll0, 1, 384, 15625), |
| 177 | F(16000000, gpll0, 5, 2, 15), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 178 | F(19200000, cxo, 1, 0, 0), |
Joonwoo Park | 095007a | 2014-06-27 17:57:45 -0700 | [diff] [blame] | 179 | F(24000000, gpll0, 5, 1, 5), |
| 180 | F(32000000, gpll0, 1, 4, 75), |
| 181 | F(40000000, gpll0, 15, 0, 0), |
| 182 | F(46400000, gpll0, 1, 29, 375), |
| 183 | F(48000000, gpll0, 12.5, 0, 0), |
| 184 | F(51200000, gpll0, 1, 32, 375), |
| 185 | F(56000000, gpll0, 1, 7, 75), |
| 186 | F(58982400, gpll0, 1, 1536, 15625), |
| 187 | F(60000000, gpll0, 10, 0, 0), |
| 188 | F(63160000, gpll0, 9.5, 0, 0), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 189 | F_END |
| 190 | }; |
| 191 | |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 192 | static struct rcg_clk blsp1_uart3_apps_clk_src = |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 193 | { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 194 | .cmd_reg = (uint32_t *) BLSP1_UART3_APPS_CMD_RCGR, |
| 195 | .cfg_reg = (uint32_t *) BLSP1_UART3_APPS_CFG_RCGR, |
| 196 | .m_reg = (uint32_t *) BLSP1_UART3_APPS_M, |
| 197 | .n_reg = (uint32_t *) BLSP1_UART3_APPS_N, |
| 198 | .d_reg = (uint32_t *) BLSP1_UART3_APPS_D, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 199 | |
| 200 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 201 | .freq_tbl = ftbl_gcc_blsp1_2_uart1_6_apps_clk, |
| 202 | .current_freq = &rcg_dummy_freq, |
| 203 | |
| 204 | .c = { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 205 | .dbg_name = "blsp1_uart3_apps_clk", |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 206 | .ops = &clk_ops_rcg_mnd, |
| 207 | }, |
| 208 | }; |
| 209 | |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 210 | static struct branch_clk gcc_blsp1_uart3_apps_clk = |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 211 | { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 212 | .cbcr_reg = (uint32_t *) BLSP1_UART3_APPS_CBCR, |
| 213 | .parent = &blsp1_uart3_apps_clk_src.c, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 214 | |
| 215 | .c = { |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 216 | .dbg_name = "gcc_blsp1_uart3_apps_clk", |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 217 | .ops = &clk_ops_branch, |
| 218 | }, |
| 219 | }; |
| 220 | |
| 221 | static struct vote_clk gcc_blsp1_ahb_clk = { |
| 222 | .cbcr_reg = (uint32_t *) BLSP1_AHB_CBCR, |
| 223 | .vote_reg = (uint32_t *) APCS_CLOCK_BRANCH_ENA_VOTE, |
| 224 | .en_mask = BIT(10), |
| 225 | |
| 226 | .c = { |
| 227 | .dbg_name = "gcc_blsp1_ahb_clk", |
| 228 | .ops = &clk_ops_vote, |
| 229 | }, |
| 230 | }; |
| 231 | |
| 232 | /* USB Clocks */ |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 233 | static struct branch_clk gcc_sys_noc_usb30_axi_clk = |
| 234 | { |
| 235 | .cbcr_reg = (uint32_t *) SYS_NOC_USB3_AXI_CBCR, |
| 236 | .has_sibling = 1, |
| 237 | |
| 238 | .c = { |
| 239 | .dbg_name = "gcc_sys_noc_usb3_axi_clk", |
| 240 | .ops = &clk_ops_branch, |
| 241 | }, |
| 242 | }; |
| 243 | |
| 244 | static struct branch_clk gcc_usb_phy_cfg_ahb_clk = { |
| 245 | .cbcr_reg = (uint32_t *) USB_PHY_CFG_AHB_CBCR, |
| 246 | .has_sibling = 1, |
| 247 | |
| 248 | .c = { |
| 249 | .dbg_name = "gcc_usb_phy_cfg_ahb_clk", |
| 250 | .ops = &clk_ops_branch, |
| 251 | }, |
| 252 | }; |
| 253 | |
| 254 | static struct clk_freq_tbl ftbl_gcc_usb30_master_clk[] = |
| 255 | { |
| 256 | F(125000000, gpll0, 1, 5, 24), |
| 257 | F_END |
| 258 | }; |
| 259 | |
| 260 | static struct rcg_clk usb30_master_clk_src = |
| 261 | { |
| 262 | .cmd_reg = (uint32_t *) GCC_USB30_MASTER_CMD_RCGR, |
| 263 | .cfg_reg = (uint32_t *) GCC_USB30_MASTER_CFG_RCGR, |
| 264 | .m_reg = (uint32_t *) GCC_USB30_MASTER_M, |
| 265 | .n_reg = (uint32_t *) GCC_USB30_MASTER_N, |
| 266 | .d_reg = (uint32_t *) GCC_USB30_MASTER_D, |
| 267 | |
| 268 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 269 | .freq_tbl = ftbl_gcc_usb30_master_clk, |
| 270 | .current_freq = &rcg_dummy_freq, |
| 271 | |
| 272 | .c = { |
| 273 | .dbg_name = "usb30_master_clk_src", |
| 274 | .ops = &clk_ops_rcg, |
| 275 | }, |
| 276 | }; |
| 277 | |
| 278 | |
| 279 | static struct branch_clk gcc_usb30_master_clk = |
| 280 | { |
| 281 | .cbcr_reg = (uint32_t *) GCC_USB30_MASTER_CBCR, |
| 282 | .parent = &usb30_master_clk_src.c, |
| 283 | |
| 284 | .c = { |
| 285 | .dbg_name = "gcc_usb30_master_clk", |
| 286 | .ops = &clk_ops_branch, |
| 287 | }, |
| 288 | }; |
| 289 | |
| 290 | static struct clk_freq_tbl ftbl_gcc_usb30_pipe_clk[] = { |
| 291 | F( 19200000, cxo, 1, 0, 0), |
| 292 | F_EXT_SRC( 125000000, usb30_pipe, 1, 0, 0), |
| 293 | F_END |
| 294 | }; |
| 295 | |
| 296 | static struct rcg_clk usb30_pipe_clk_src = { |
| 297 | .cmd_reg = (uint32_t *) USB3_PIPE_CMD_RCGR, |
| 298 | .cfg_reg = (uint32_t *) USB3_PIPE_CFG_RCGR, |
| 299 | .set_rate = clock_lib2_rcg_set_rate_hid, |
| 300 | .freq_tbl = ftbl_gcc_usb30_pipe_clk, |
| 301 | .current_freq = &rcg_dummy_freq, |
| 302 | |
| 303 | .c = { |
| 304 | .dbg_name = "usb30_pipe_clk_src", |
| 305 | .ops = &clk_ops_rcg, |
| 306 | }, |
| 307 | }; |
| 308 | |
| 309 | static struct branch_clk gcc_usb30_pipe_clk = { |
| 310 | .cbcr_reg = (uint32_t *) USB3_PIPE_CBCR, |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 311 | .bcr_reg = (uint32_t *) USB3_PIPE_BCR, |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 312 | .parent = &usb30_pipe_clk_src.c, |
| 313 | .has_sibling = 0, |
| 314 | |
| 315 | .c = { |
| 316 | .dbg_name = "gcc_usb30_pipe_clk", |
| 317 | .ops = &clk_ops_branch, |
| 318 | }, |
| 319 | }; |
| 320 | |
| 321 | static struct clk_freq_tbl ftbl_gcc_usb30_aux_clk[] = { |
| 322 | F( 1000000, cxo, 1, 5, 96), |
| 323 | F_END |
| 324 | }; |
| 325 | |
| 326 | static struct rcg_clk usb30_aux_clk_src = { |
| 327 | .cmd_reg = (uint32_t *) USB3_AUX_CMD_RCGR, |
| 328 | .cfg_reg = (uint32_t *) USB3_AUX_CFG_RCGR, |
| 329 | .m_reg = (uint32_t *) USB3_AUX_M, |
| 330 | .n_reg = (uint32_t *) USB3_AUX_N, |
| 331 | .d_reg = (uint32_t *) USB3_AUX_D, |
| 332 | |
| 333 | .set_rate = clock_lib2_rcg_set_rate_mnd, |
| 334 | .freq_tbl = ftbl_gcc_usb30_aux_clk, |
| 335 | .current_freq = &rcg_dummy_freq, |
| 336 | |
| 337 | .c = { |
| 338 | .dbg_name = "usb30_aux_clk_src", |
| 339 | .ops = &clk_ops_rcg_mnd, |
| 340 | }, |
| 341 | }; |
| 342 | |
| 343 | static struct branch_clk gcc_usb30_aux_clk = { |
| 344 | .cbcr_reg = (uint32_t *) USB3_AUX_CBCR, |
| 345 | .parent = &usb30_aux_clk_src.c, |
| 346 | |
| 347 | .c = { |
| 348 | .dbg_name = "gcc_usb30_aux_clk", |
| 349 | .ops = &clk_ops_branch, |
| 350 | }, |
| 351 | }; |
| 352 | |
| 353 | static struct reset_clk gcc_usb30_phy_reset = { |
| 354 | .bcr_reg = (uint32_t *) USB3_PHY_BCR, |
| 355 | |
| 356 | .c = { |
| 357 | .dbg_name = "usb30_phy_reset", |
| 358 | .ops = &clk_ops_reset, |
| 359 | }, |
| 360 | }; |
| 361 | |
Joonwoo Park | 76641c7 | 2014-05-22 16:37:10 -0700 | [diff] [blame] | 362 | static struct reset_clk gcc_usb2a_phy_sleep_clk = { |
| 363 | .bcr_reg = (uint32_t *) QUSB2A_PHY_BCR, |
| 364 | |
| 365 | .c = { |
| 366 | .dbg_name = "usb2b_phy_sleep_clk", |
| 367 | .ops = &clk_ops_reset, |
| 368 | }, |
| 369 | }; |
| 370 | |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 371 | static struct clk_lookup msm_clocks_zirc[] = |
| 372 | { |
| 373 | CLK_LOOKUP("sdc1_iface_clk", gcc_sdcc1_ahb_clk.c), |
| 374 | CLK_LOOKUP("sdc1_core_clk", gcc_sdcc1_apps_clk.c), |
| 375 | |
Channagoud Kadabi | 1b69e48 | 2014-09-23 15:20:22 -0700 | [diff] [blame^] | 376 | CLK_LOOKUP("uart3_iface_clk", gcc_blsp1_ahb_clk.c), |
| 377 | CLK_LOOKUP("uart3_core_clk", gcc_blsp1_uart3_apps_clk.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 378 | |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 379 | CLK_LOOKUP("usb30_iface_clk", gcc_sys_noc_usb30_axi_clk.c), |
| 380 | CLK_LOOKUP("usb30_master_clk", gcc_usb30_master_clk.c), |
| 381 | CLK_LOOKUP("usb30_pipe_clk", gcc_usb30_pipe_clk.c), |
| 382 | CLK_LOOKUP("usb30_aux_clk", gcc_usb30_aux_clk.c), |
| 383 | |
Joonwoo Park | 76641c7 | 2014-05-22 16:37:10 -0700 | [diff] [blame] | 384 | CLK_LOOKUP("usb2b_phy_sleep_clk", gcc_usb2a_phy_sleep_clk.c), |
Joonwoo Park | 451dca3 | 2014-04-02 11:47:03 -0700 | [diff] [blame] | 385 | CLK_LOOKUP("usb30_phy_reset", gcc_usb30_phy_reset.c), |
| 386 | |
| 387 | CLK_LOOKUP("usb_phy_cfg_ahb_clk", gcc_usb_phy_cfg_ahb_clk.c), |
| 388 | }; |
| 389 | |
| 390 | void platform_clock_init(void) |
| 391 | { |
| 392 | clk_init(msm_clocks_zirc, ARRAY_SIZE(msm_clocks_zirc)); |
| 393 | } |