blob: c6a5bab85b18b1250abd630e3cdcdd1aebd7dcf2 [file] [log] [blame]
Ajay Singh Parmar243d82b2014-07-23 23:01:44 -07001/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 */
29#include <err.h>
30#include <debug.h>
31#include <reg.h>
32#include <msm_panel.h>
33#include <platform/timer.h>
34#include <platform/clock.h>
35#include <platform/iomap.h>
36
37static struct msm_fb_panel_data panel;
38
39/* AVI INFOFRAME DATA */
40#define NUM_MODES_AVI 20
41#define AVI_MAX_DATA_BYTES 13
42
43enum {
44 DATA_BYTE_1,
45 DATA_BYTE_2,
46 DATA_BYTE_3,
47 DATA_BYTE_4,
48 DATA_BYTE_5,
49 DATA_BYTE_6,
50 DATA_BYTE_7,
51 DATA_BYTE_8,
52 DATA_BYTE_9,
53 DATA_BYTE_10,
54 DATA_BYTE_11,
55 DATA_BYTE_12,
56 DATA_BYTE_13,
57};
58
59#define IFRAME_PACKET_OFFSET 0x80
60/*
61 * InfoFrame Type Code:
62 * 0x0 - Reserved
63 * 0x1 - Vendor Specific
64 * 0x2 - Auxiliary Video Information
65 * 0x3 - Source Product Description
66 * 0x4 - AUDIO
67 * 0x5 - MPEG Source
68 * 0x6 - NTSC VBI
69 * 0x7 - 0xFF - Reserved
70 */
71#define AVI_IFRAME_TYPE 0x2
72#define AVI_IFRAME_VERSION 0x2
73#define LEFT_SHIFT_BYTE(x) ((x) << 8)
74#define LEFT_SHIFT_WORD(x) ((x) << 16)
75#define LEFT_SHIFT_24BITS(x) ((x) << 24)
76
77struct mdss_hdmi_timing_info {
78 uint32_t video_format;
79 uint32_t active_h;
80 uint32_t front_porch_h;
81 uint32_t pulse_width_h;
82 uint32_t back_porch_h;
83 uint32_t active_low_h;
84 uint32_t active_v;
85 uint32_t front_porch_v;
86 uint32_t pulse_width_v;
87 uint32_t back_porch_v;
88 uint32_t active_low_v;
89 /* Must divide by 1000 to get the actual frequency in MHZ */
90 uint32_t pixel_freq;
91 /* Must divide by 1000 to get the actual frequency in HZ */
92 uint32_t refresh_rate;
93 uint32_t interlaced;
94 uint32_t supported;
95};
96
97#define HDMI_VFRMT_1280x720p60_16_9 4
98#define HDMI_RESOLUTION_DATA HDMI_VFRMT_1280x720p60_16_9##_TIMING
99
100#define HDMI_VFRMT_1280x720p60_16_9_TIMING \
101 {HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \
102 720, 5, 5, 20, false, 74250, 60000, false, true}
103
104uint32_t mdss_hdmi_avi_info_db[] = {
105 0x10, 0x28, 0x00, 0x04, 0x00, 0x00, 0x00,
106 0xD1, 0x02, 0x00, 0x00, 0x01, 0x05};
107
108static int mdss_hdmi_panel_clock(uint8_t enable, struct msm_panel_info *pinfo)
109{
110 return target_hdmi_panel_clock(enable, pinfo);
111}
112
113static int mdss_hdmi_enable_power(uint8_t enable)
114{
115 int ret = NO_ERROR;
116
117 ret = target_ldo_ctrl(enable);
118 if (ret) {
119 dprintf(CRITICAL, "LDO control enable failed\n");
120 return ret;
121 }
122
123 ret = target_hdmi_regulator_ctrl(enable);
124 if (ret) {
125 dprintf(CRITICAL, "hdmi regulator control enable failed\n");
126 return ret;
127 }
128
129 dprintf(SPEW, "HDMI Panel power %s done\n", enable ? "on" : "off");
130
131 return ret;
132}
133
134static void mdss_hdmi_set_mode(bool on)
135{
136 uint32_t val = 0;
137
138 if (on) {
139 val = 0x3;
140 writel(val, HDMI_CTRL);
141 } else {
142 writel(val, HDMI_CTRL);
143 }
144}
145
146static void mdss_hdmi_panel_init(struct msm_panel_info *pinfo)
147{
148 struct mdss_hdmi_timing_info tinfo = HDMI_RESOLUTION_DATA;
149
150 if (!pinfo)
151 return;
152
153 pinfo->xres = tinfo.active_h;
154 pinfo->yres = tinfo.active_v;
155 pinfo->bpp = 24;
156 pinfo->type = HDMI_PANEL;
157
158 pinfo->lcdc.h_back_porch = tinfo.back_porch_h;
159 pinfo->lcdc.h_front_porch = tinfo.front_porch_h;
160 pinfo->lcdc.h_pulse_width = tinfo.pulse_width_h;
161 pinfo->lcdc.v_back_porch = tinfo.back_porch_v;
162 pinfo->lcdc.v_front_porch = tinfo.front_porch_v;
163 pinfo->lcdc.v_pulse_width = tinfo.pulse_width_v;
164
165 pinfo->lcdc.hsync_skew = 0;
166 pinfo->lcdc.xres_pad = 0;
167 pinfo->lcdc.yres_pad = 0;
168 pinfo->lcdc.dual_pipe = 0;
169}
170
171void mdss_hdmi_display_init(uint32_t rev, void *base)
172{
173 mdss_hdmi_panel_init(&(panel.panel_info));
174
175 panel.clk_func = mdss_hdmi_panel_clock;
176 panel.power_func = mdss_hdmi_enable_power;
177
178 panel.fb.width = panel.panel_info.xres;
179 panel.fb.height = panel.panel_info.yres;
180 panel.fb.stride = panel.panel_info.xres;
181 panel.fb.bpp = panel.panel_info.bpp;
182 panel.fb.format = FB_FORMAT_RGB888;
183
184 panel.fb.base = base;
185 panel.mdp_rev = rev;
186
187 msm_display_init(&panel);
188}
189
190static int mdss_hdmi_video_setup(void)
191{
192 uint32_t total_v = 0;
193 uint32_t total_h = 0;
194 uint32_t start_h = 0;
195 uint32_t end_h = 0;
196 uint32_t start_v = 0;
197 uint32_t end_v = 0;
198
199 struct mdss_hdmi_timing_info tinfo = HDMI_RESOLUTION_DATA;
200
201 total_h = tinfo.active_h + tinfo.front_porch_h +
202 tinfo.back_porch_h + tinfo.pulse_width_h - 1;
203 total_v = tinfo.active_v + tinfo.front_porch_v +
204 tinfo.back_porch_v + tinfo.pulse_width_v - 1;
205 if (((total_v << 16) & 0xE0000000) || (total_h & 0xFFFFE000)) {
206 dprintf(CRITICAL,
207 "%s: total v=%d or h=%d is larger than supported\n",
208 __func__, total_v, total_h);
209 return ERROR;
210 }
211 writel((total_v << 16) | (total_h << 0), HDMI_TOTAL);
212
213 start_h = tinfo.back_porch_h + tinfo.pulse_width_h;
214 end_h = (total_h + 1) - tinfo.front_porch_h;
215 if (((end_h << 16) & 0xE0000000) || (start_h & 0xFFFFE000)) {
216 dprintf(CRITICAL,
217 "%s: end_h=%d or start_h=%d is larger than supported\n",
218 __func__, end_h, start_h);
219 return ERROR;
220 }
221 writel((end_h << 16) | (start_h << 0), HDMI_ACTIVE_H);
222
223 start_v = tinfo.back_porch_v + tinfo.pulse_width_v - 1;
224 end_v = total_v - tinfo.front_porch_v;
225 if (((end_v << 16) & 0xE0000000) || (start_v & 0xFFFFE000)) {
226 dprintf(CRITICAL,
227 "%s: end_v=%d or start_v=%d is larger than supported\n",
228 __func__, end_v, start_v);
229 return ERROR;
230 }
231 writel((end_v << 16) | (start_v << 0), HDMI_ACTIVE_V);
232
233 if (tinfo.interlaced) {
234 writel((total_v + 1) << 0, HDMI_V_TOTAL_F2);
235 writel(((end_v + 1) << 16) | ((start_v + 1) << 0),
236 HDMI_ACTIVE_V_F2);
237 } else {
238 writel(0, HDMI_V_TOTAL_F2);
239 writel(0, HDMI_ACTIVE_V_F2);
240 }
241
242 writel(((tinfo.interlaced << 31) & 0x80000000) |
243 ((tinfo.active_low_h << 29) & 0x20000000) |
244 ((tinfo.active_low_v << 28) & 0x10000000), HDMI_FRAME_CTRL);
245
246 return 0;
247}
248
249void mdss_hdmi_avi_info_frame(void)
250{
251 uint32_t sum;
252 uint32_t reg_val;
253 uint8_t checksum;
254 uint32_t i;
255
256 sum = IFRAME_PACKET_OFFSET + AVI_IFRAME_TYPE +
257 AVI_IFRAME_VERSION + AVI_MAX_DATA_BYTES;
258
259 for (i = 0; i < AVI_MAX_DATA_BYTES; i++)
260 sum += mdss_hdmi_avi_info_db[i];
261
262 sum &= 0xFF;
263 sum = 256 - sum;
264 checksum = (uint8_t) sum;
265
266 reg_val = checksum |
267 LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_1]) |
268 LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_2]) |
269 LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_3]);
270 writel(reg_val, HDMI_AVI_INFO0);
271
272 reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_4] |
273 LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_5]) |
274 LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_6]) |
275 LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_7]);
276 writel(reg_val, HDMI_AVI_INFO1);
277
278 reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_8] |
279 LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_9]) |
280 LEFT_SHIFT_WORD(mdss_hdmi_avi_info_db[DATA_BYTE_10]) |
281 LEFT_SHIFT_24BITS(mdss_hdmi_avi_info_db[DATA_BYTE_11]);
282 writel(reg_val, HDMI_AVI_INFO2);
283
284 reg_val = mdss_hdmi_avi_info_db[DATA_BYTE_12] |
285 LEFT_SHIFT_BYTE(mdss_hdmi_avi_info_db[DATA_BYTE_13]) |
286 LEFT_SHIFT_24BITS(AVI_IFRAME_VERSION);
287 writel(reg_val, HDMI_AVI_INFO3);
288
289 /* AVI InfFrame enable (every frame) */
290 writel(readl(HDMI_INFOFRAME_CTRL0) | BIT(1) | BIT(0),
291 HDMI_INFOFRAME_CTRL0);
292}
293
294int mdss_hdmi_init(void)
295{
296 uint32_t hotplug_control;
297
298 mdss_hdmi_set_mode(false);
299
300 hdmi_phy_init();
301
302 // Enable USEC REF timer
303 writel(0x0001001B, HDMI_USEC_REFTIMER);
304
305 // Video setup for HDMI
306 mdss_hdmi_video_setup();
307
308 // AVI info setup
309 mdss_hdmi_avi_info_frame();
310
311 // Write 1 to HDMI_CTRL to enable HDMI
312 mdss_hdmi_set_mode(true);
313
314 return 0;
315}