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gerrit-public.fairphone.software / kernel / lk / 2a8fd54c3ba1648a835f18430de307a17c01d403 / . / platform / msm7x30 / panel.c
blob: f7239c1e2a09f39480cdd9238e102474abe8889e [file] [log] [blame]
Chandan Uddarajuc009e4d2010-09-08 17:06:45 -0700[diff] [blame]1/*
2 * Copyright (c) 2007, Google Inc.
3 * All rights reserved.
4 *
5 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
15 * distribution.
16 * * Neither the name of Code Aurora nor
17 * the names of its contributors may be used to endorse or promote
18 * products derived from this software without specific prior written
19 * permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
28 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#include <debug.h>
36#include <dev/gpio.h>
37#include <kernel/thread.h>
Subbaraman Narayanamurthy2a8fd542010-10-27 15:45:18 -0700[diff] [blame^]38#include "gpio_hw.h"
Chandan Uddarajuc009e4d2010-09-08 17:06:45 -0700[diff] [blame]39
40#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
41static int display_common_power(int);
42
43#if DISPLAY_TYPE_MDDI
44#include <mddi.h>
45
46#define MDDI_CLIENT_CORE_BASE 0x108000
47#define LCD_CONTROL_BLOCK_BASE 0x110000
48#define SPI_BLOCK_BASE 0x120000
49#define I2C_BLOCK_BASE 0x130000
50#define PWM_BLOCK_BASE 0x140000
51#define GPIO_BLOCK_BASE 0x150000
52#define SYSTEM_BLOCK1_BASE 0x160000
53#define SYSTEM_BLOCK2_BASE 0x170000
54
55
56#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00)
57#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04)
58#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08)
59#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C)
60#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10)
61#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14)
62#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18)
63#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C)
64#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20)
65#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24)
66#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28)
67#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C)
68#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30)
69#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34)
70#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38)
71#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C)
72#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40)
73#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44)
74#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48)
75#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C)
76#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50)
77#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54)
78
79
80#define SRST (LCD_CONTROL_BLOCK_BASE|0x00)
81#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04)
82#define START (LCD_CONTROL_BLOCK_BASE|0x08)
83#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C)
84#define CMN (LCD_CONTROL_BLOCK_BASE|0x10)
85#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14)
86#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18)
87#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C)
88#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20)
89#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24)
90#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28)
91
92#define PXL (LCD_CONTROL_BLOCK_BASE|0x30)
93#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34)
94#define HSW (LCD_CONTROL_BLOCK_BASE|0x38)
95#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C)
96#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40)
97#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44)
98#define VSW (LCD_CONTROL_BLOCK_BASE|0x48)
99#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C)
100#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50)
101#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54)
102#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58)
103#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C)
104#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60)
105#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64)
106#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68)
107#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C)
108#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70)
109#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74)
110#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78)
111#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C)
112#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80)
113#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84)
114#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88)
115#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C)
116
117#define MONI (LCD_CONTROL_BLOCK_BASE|0xB0)
118
119#define Current (LCD_CONTROL_BLOCK_BASE|0xC0)
120#define LCD (LCD_CONTROL_BLOCK_BASE|0xC4)
121#define COMMAND (LCD_CONTROL_BLOCK_BASE|0xC8)
122
123
124#define SSICTL (SPI_BLOCK_BASE|0x00)
125#define SSITIME (SPI_BLOCK_BASE|0x04)
126#define SSITX (SPI_BLOCK_BASE|0x08)
127#define SSIRX (SPI_BLOCK_BASE|0x0C)
128#define SSIINTC (SPI_BLOCK_BASE|0x10)
129#define SSIINTS (SPI_BLOCK_BASE|0x14)
130#define SSIDBG1 (SPI_BLOCK_BASE|0x18)
131#define SSIDBG2 (SPI_BLOCK_BASE|0x1C)
132#define SSIID (SPI_BLOCK_BASE|0x20)
133
134
135#define I2CSETUP (I2C_BLOCK_BASE|0x00)
136#define I2CCTRL (I2C_BLOCK_BASE|0x04)
137
138
139#define TIMER0LOAD (PWM_BLOCK_BASE|0x00)
140#define TIMER0VALUE (PWM_BLOCK_BASE|0x04)
141#define TIMER0CONTROL (PWM_BLOCK_BASE|0x08)
142#define TIMER0INTCLR (PWM_BLOCK_BASE|0x0C)
143#define TIMER0RIS (PWM_BLOCK_BASE|0x10)
144#define TIMER0MIS (PWM_BLOCK_BASE|0x14)
145#define TIMER0BGLOAD (PWM_BLOCK_BASE|0x18)
146#define PWM0OFF (PWM_BLOCK_BASE|0x1C)
147#define TIMER1LOAD (PWM_BLOCK_BASE|0x20)
148#define TIMER1VALUE (PWM_BLOCK_BASE|0x24)
149#define TIMER1CONTROL (PWM_BLOCK_BASE|0x28)
150#define TIMER1INTCLR (PWM_BLOCK_BASE|0x2C)
151#define TIMER1RIS (PWM_BLOCK_BASE|0x30)
152#define TIMER1MIS (PWM_BLOCK_BASE|0x34)
153#define TIMER1BGLOAD (PWM_BLOCK_BASE|0x38)
154#define PWM1OFF (PWM_BLOCK_BASE|0x3C)
155#define TIMERITCR (PWM_BLOCK_BASE|0x60)
156#define TIMERITOP (PWM_BLOCK_BASE|0x64)
157#define PWMCR (PWM_BLOCK_BASE|0x68)
158#define PWMID (PWM_BLOCK_BASE|0x6C)
159#define PWMMON (PWM_BLOCK_BASE|0x70)
160
161
162#define GPIODATA (GPIO_BLOCK_BASE|0x00)
163#define GPIODIR (GPIO_BLOCK_BASE|0x04)
164#define GPIOIS (GPIO_BLOCK_BASE|0x08)
165#define GPIOIBE (GPIO_BLOCK_BASE|0x0C)
166#define GPIOIEV (GPIO_BLOCK_BASE|0x10)
167#define GPIOIE (GPIO_BLOCK_BASE|0x14)
168#define GPIORIS (GPIO_BLOCK_BASE|0x18)
169#define GPIOMIS (GPIO_BLOCK_BASE|0x1C)
170#define GPIOIC (GPIO_BLOCK_BASE|0x20)
171#define GPIOOMS (GPIO_BLOCK_BASE|0x24)
172#define GPIOPC (GPIO_BLOCK_BASE|0x28)
173
174#define GPIOID (GPIO_BLOCK_BASE|0x30)
175
176
177#define WKREQ (SYSTEM_BLOCK1_BASE|0x00)
178#define CLKENB (SYSTEM_BLOCK1_BASE|0x04)
179#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08)
180#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C)
181#define CNT_DIS (SYSTEM_BLOCK1_BASE|0x10)
182#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00)
183
184struct init_table {
185 unsigned int reg;
186 unsigned int val;
187};
188
189static struct init_table toshiba_480x800_init_table[] = {
190 { DPSET0, 0x4BEC0066 }, // # MDC.DPSET0 # Setup DPLL parameters
191 { DPSET1, 0x00000113 }, // # MDC.DPSET1
192 { DPSUS, 0x00000000 }, // # MDC.DPSUS # Set DPLL oscillation enable
193 { DPRUN, 0x00000001 }, // # MDC.DPRUN # Release reset signal for DPLL
194 { 0, 15 }, // wait_ms(15);
195 { SYSCKENA, 0x00000001 }, // # MDC.SYSCKENA # Enable system clock output
196 { CLKENB, 0x000000E9 }, // # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK)
197
198 { GPIO_BLOCK_BASE, 0x03FF0000 }, // # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0
199 { GPIODIR, 0x0000024D }, // # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output)
200 { SYSTEM_BLOCK2_BASE, 0x00000173 }, // # SYS.GPIOSEL # GPIO port multiplexing control
201 { GPIOPC, 0x03C300C0 }, // # GPI .GPIOPC # GPIO2,3 PD cut
202 { SYSTEM_BLOCK1_BASE, 0x00000000 }, // # SYS.WKREQ # Wake-up request event is VSYNC alignment
203 { GPIOIS, 0x00000000 }, // # GPI .GPIOIS # Set interrupt sense of GPIO
204 { GPIOIEV, 0x00000001 }, // # GPI .GPIOIEV # Set interrupt event of GPIO
205 { GPIOIC, 0x000003FF }, // # GPI .GPIOIC # GPIO interrupt clear
206 { GPIO_BLOCK_BASE, 0x00040004 }, // # GPI .GPIODATA # Release LCDD reset
207
208 { GPIO_BLOCK_BASE, 0x00080008 }, // # GPI .GPIODATA # eDRAM VD supply
209 { DRAMPWR, 0x00000001 }, // # SYS.DRAMPWR # eDRAM power up
210 { CLKENB, 0x000000EB }, // # enable eDRAM clock
211
212 { PWMCR, 0x00000000 }, // # PWM.PWMCR # PWM output enable
213 { 0, 1 }, // wait_ms(1);
214 { SPI_BLOCK_BASE, 0x00060399}, // # SPI .SSICTL # SPI operation mode setting
215 { SSITIME, 0x00000100 }, // # SPI .SSITIME # SPI serial interface timing setting
216 { CNT_DIS, 0x00000002 }, // # SPI .SSITIME # SPI serial interface timing setting
217 { SPI_BLOCK_BASE, 0x0006039B }, // # SPI .SSICTL # Set SPI active mode
218
219 { SSITX, 0x00000000 }, // # SPI.SSITX # Release from Deep Stanby mode
220 { 0, 7 }, // wait_ms(2);
221 { SSITX, 0x00000000 }, // # SPI.SSITX
222 { 0, 7 }, // wait_ms(2);
223 { SSITX, 0x00000000 }, // # SPI.SSITX
224 { 0, 7 }, // wait_ms(2);
225
226 { SSITX, 0x000800BA }, // # SPI.SSITX *NOTE 1 # Command setting of SPI block
227 { SSITX, 0x00000111 }, // # Display mode setup(1) : Normaly Black
228 { SSITX, 0x00080036 }, // # Command setting of SPI block
229 { SSITX, 0x00000100 }, // # Memory access control
230 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
231 { SSITX, 0x0008003A }, // # Command setting of SPI block
232 { SSITX, 0x00000160 }, // # Display mode setup(2)
233 { SSITX, 0x000800B1 }, // # Command setting of SPI block
234 { SSITX, 0x0000015D }, // # RGB Interface data format
235 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
236 { SSITX, 0x000800B2 }, // # Command setting of SPI block
237 { SSITX, 0x00000133 }, // # Drivnig method
238 { SSITX, 0x000800B3 }, // # Command setting of SPI block
239 { SSITX, 0x00000122 }, // # Booster operation setup
240 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
241 { SSITX, 0x000800B4 }, // # Command setting of SPI block
242 { SSITX, 0x00000102 }, // # OP-amp capability/System clock freq. division setup
243 { SSITX, 0x000800B5 }, // # Command setting of SPI block
244 { SSITX, 0x0000011E }, // # VCS Voltage adjustment (1C->1F for Rev 2)
245 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
246 { SSITX, 0x000800B6 }, // # Command setting of SPI block
247 { SSITX, 0x00000127 }, // # VCOM Voltage adjustment
248 { SSITX, 0x000800B7 }, // # Command setting of SPI block
249 { SSITX, 0x00000103 }, // # Configure an external display signal
250 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
251 { SSITX, 0x000800B9 }, // # Command setting of SPI block
252 { SSITX, 0x00000124 }, // # DCCK/DCEV timing setup
253 { SSITX, 0x000800BD }, // # Command setting of SPI block
254 { SSITX, 0x000001A1 }, // # ASW signal control
255 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
256 { SSITX, 0x000800BB }, // # Command setting of SPI block
257 { SSITX, 0x00000100 }, // # Dummy display (white/black) count setup for QUAD Data operation
258 { SSITX, 0x000800BF }, // # Command setting of SPI block
259 { SSITX, 0x00000101 }, // # Dummy display (white/black) count setup for QUAD Data operation
260 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
261 { SSITX, 0x000800BE }, // # Command setting of SPI block
262 { SSITX, 0x00000100 }, // # wait_ms(-out FR count setup (A)
263 { SSITX, 0x000800C0 }, // # Command setting of SPI block
264 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (A)
265 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
266 { SSITX, 0x000800C1 }, // # Command setting of SPI block
267 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (B)
268 { SSITX, 0x000800C2 }, // # Command setting of SPI block
269 { SSITX, 0x00000111 }, // # wait_ms(-out FR count setup (C)
270 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
271 { SSITX, 0x000800C3 }, // # Command setting of SPI block
272 { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (D)
273 { SSITX, 0x00000132 }, //
274 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
275 { SSITX, 0x000800C4 }, // # Command setting of SPI block
276 { SSITX, 0x00080132 }, // # Seep-in line clock count setup (E)
277 { SSITX, 0x00000132 }, //
278 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
279 { SSITX, 0x000800C5 }, // # Command setting of SPI block
280 { SSITX, 0x00080132 }, // # wait_ms(-in line clock count setup (F)
281 { SSITX, 0x00000132 }, //
282 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
283 { SSITX, 0x000800C6 }, // # Command setting of SPI block
284 { SSITX, 0x00080132 }, // # wait_ms(-in line clock setup (G)
285 { SSITX, 0x00000132 }, //
286 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
287 { SSITX, 0x000800C7 }, // # Command setting of SPI block
288 { SSITX, 0x00080164 }, // # Gamma 1 fine tuning (1)
289 { SSITX, 0x00000145 }, //
290 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
291 { SSITX, 0x000800C8 }, // # Command setting of SPI block
292 { SSITX, 0x00000144 }, // # Gamma 1 fine tuning (2)
293 { SSITX, 0x000800C9 }, // # Command setting of SPI block
294 { SSITX, 0x00000152 }, // # Gamma 1 inclination adjustment
295 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
296 { SSITX, 0x000800CA }, // # Command setting of SPI block
297 { SSITX, 0x00000100 }, // # Gamma 1 blue offset adjustment
298 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
299 { SSITX, 0x000800EC }, // # Command setting of SPI block
300 { SSITX, 0x00080102 }, // # Total number of horizontal clock cycles (1) [PCLK Sync. VGA setting]
301 { SSITX, 0x00000118 }, //
302 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
303 { SSITX, 0x000800CF }, // # Command setting of SPI block
304 { SSITX, 0x00000101 }, // # Blanking period control (1) [PCLK Sync. Table1 for VGA]
305 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
306 { SSITX, 0x000800D0 }, // # Command setting of SPI block
307 { SSITX, 0x00080110 }, // # Blanking period control (2) [PCLK Sync. Table1 for VGA]
308 { SSITX, 0x00000104 }, //
309 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
310 { SSITX, 0x000800D1 }, // # Command setting of SPI block
311 { SSITX, 0x00000101 }, // # CKV timing control on/off [PCLK Sync. Table1 for VGA]
312 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
313 { SSITX, 0x000800D2 }, // # Command setting of SPI block
314 { SSITX, 0x00080100 }, // # CKV1,2 timing control [PCLK Sync. Table1 for VGA]
315 { SSITX, 0x00000128 }, //
316 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
317 { SSITX, 0x000800D3 }, // # Command setting of SPI block
318 { SSITX, 0x00080100 }, // # OEV timing control [PCLK Sync. Table1 for VGA]
319 { SSITX, 0x00000128 }, //
320 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
321 { SSITX, 0x000800D4 }, // # Command setting of SPI block
322 { SSITX, 0x00080126 }, // # ASW timing control (1) [PCLK Sync. Table1 for VGA]
323 { SSITX, 0x000001A4 }, //
324 { 0, 1 }, // wait_ms(1); // # Wait SPI fifo empty
325 { SSITX, 0x000800D5 }, // # Command setting of SPI block
326 { SSITX, 0x00000120 }, // # ASW timing control (2) [PCLK Sync. Table1 for VGA]
327 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
328 { SSITX, 0x000800EF }, // # Command setting of SPI block
329 { SSITX, 0x00080132 }, // # Total number of horizontal clock cycles (2) [PCLK Sync. Table1 for QVGA ]
330 { SSITX, 0x00000100 }, //
331 { 0, 2 }, // wait_ms(2); // # Wait SPI fifo empty
332
333 { BITMAP0, 0x032001E0 }, // MDC.BITMAP0 ); // Setup of PITCH size to Frame buffer1
334 { BITMAP1, 0x032001E0 }, // MDC.BITMAP1 ); // Setup of PITCH size to Frame buffer1
335 { BITMAP2, 0x014000F0 }, // MDC.BITMAP3 ); // Setup of PITCH size to Frame buffer2
336 { BITMAP3, 0x014000F0 }, // MDC.BITMAP4 ); // Setup of PITCH size to Frame buffer3
337 { BITMAP4, 0x014000F0 }, // MDC.BITMAP5 ); // Setup of PITCH size to Frame buffer4
338 { CLKENB, 0x000001EB }, // SYS.CLKENB ); // DCLK supply
339 { PORT_ENB, 0x00000001 }, // LCD.PORT_ENB ); // Synchronous port enable
340 { PORT, 0x00000004 }, // LCD.PORT ); // Polarity of DE is set to high active
341 { PXL, 0x00000002 }, // LCD.PXL ); // ACTMODE 2 set (1st frame black data output)
342 { MPLFBUF, 0x00000000 }, // LCD.MPLFBUF ); // Select the reading buffer
343 { HCYCLE, 0x0000010B }, // LCD.HCYCLE ); // Setup to VGA size
344 { HSW, 0x00000003 }, // LCD.HSW
345 { HDE_START, 0x00000007 }, // LCD.HDE_START
346 { HDE_SIZE, 0x000000EF }, // LCD.HDE_SIZE
347 { VCYCLE, 0x00000325 }, // LCD.VCYCLE
348 { VSW, 0x00000001 }, // LCD.VSW
349 { VDE_START, 0x00000003 }, // LCD.VDE_START
350 { VDE_SIZE, 0x0000031F }, // LCD.VDE_SIZE
351
352 { START, 0x00000001 }, // LCD.START ); // LCDC - Pixel data transfer start
353
354 { 0, 10 }, // wait_ms( 10 );
355 { SSITX, 0x000800BC }, // SPI.SSITX ); // Command setting of SPI block
356 { SSITX, 0x00000180 }, // Display data setup
357 { SSITX, 0x0008003B }, // Command setting of SPI block
358 { SSITX, 0x00000100 }, // Quad Data configuration - VGA
359 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
360 { SSITX, 0x000800B0 }, // Command setting of SPI block
361 { SSITX, 0x00000116 }, // Power supply ON/OFF control
362 { 0, 1 }, // wait_ms( 1 ); // Wait SPI fifo empty
363 { SSITX, 0x000800B8 }, // Command setting of SPI block
364 { SSITX, 0x000801FF }, // Output control
365 { SSITX, 0x000001F5 },
366 { 0, 1 }, // wait_ms( 1); // Wait SPI fifo empty
367 { SSITX, 0x00000011 }, // wait_ms(-out (Command only)
368 { 0, 5 }, // wait_ms( 1); // Wait SPI fifo empty
369 { SSITX, 0x00000029 }, // Display on (Command only)
370
371 //{ SYSTEM_BLOCK1_BASE, 0x00000002 }, // # wakeREQ -> GPIO
372
373 { 0, 0 }
374};
375
376void mddi_panel_poweron(void)
377{
378 display_common_power(1);
379}
380
381static void _panel_init(struct init_table *init_table)
382{
383 unsigned n;
384
385 dprintf(INFO, "panel_init()\n");
386
387 n = 0;
388 while (init_table[n].reg != 0 || init_table[n].val != 0) {
389 if (init_table[n].reg != 0)
390 mddi_remote_write(init_table[n].val, init_table[n].reg);
391 else
392 mdelay(init_table[n].val);
393 n++;
394 }
395
396 dprintf(INFO, "panel_init() done\n");
397}
398
399void panel_init(struct mddi_client_caps *client_caps)
400{
401 switch(client_caps->manufacturer_name) {
402 case 0xd263: // Toshiba
403 dprintf(INFO, "Found Toshiba panel\n");
404 _panel_init(toshiba_480x800_init_table);
405 break;
406 case 0x4474: //??
407 if (client_caps->product_code == 0xc065)
408 dprintf(INFO, "Found WVGA panel\n");
409 break;
410 }
411}
412#endif //mddi
413
414void panel_poweron(void)
415{
416#if DISPLAY_TYPE_LCDC
417 panel_backlight(1);
418 lcdc_on();
419#endif
420}
421
422void panel_backlight(int on)
423{
424 unsigned char reg_data = 0xA0;
425 if(on)
426 pmic_write(0x132, reg_data);
427 else
428 pmic_write(0x132, 0);
429}
430
431static unsigned wega_reset_gpio =
432GPIO_CFG(180, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA);
433
434#define LDO12_CNTRL 0x015
435#define LDO15_CNTRL 0x089
436#define LDO16_CNTRL 0x08A
437#define LDO20_CNTRL 0x11F // PM8058 only
438#define LDO_LOCAL_EN_BMSK 0x80
439
440static int display_common_power(int on)
441{
442 int rc = 0, flag_on = !!on;
443 static int display_common_power_save_on;
444 unsigned int vreg_ldo12, vreg_ldo15, vreg_ldo20, vreg_ldo16, vreg_ldo8;
445 if (display_common_power_save_on == flag_on)
446 return 0;
447
448 display_common_power_save_on = flag_on;
449
450 if (on) {
451 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
452 rc = gpio_tlmm_config(wega_reset_gpio, GPIO_ENABLE);
453 if (rc) {
454 return rc;
455 }
456
457 gpio_set(180, 0); /* bring reset line low to hold reset*/
458 }
459
460 // Set power for WEGA chip.
461 // Set LD020 to 1.5V
462 pmic_write(LDO20_CNTRL, 0x00 | LDO_LOCAL_EN_BMSK);
463 mdelay(5);
464
465 // Set LD012 to 1.8V
466 pmic_write(LDO12_CNTRL, 0x06 | LDO_LOCAL_EN_BMSK);
467 mdelay(5);
468
469 // Set LD016 to 2.6V
470 pmic_write(LDO16_CNTRL, 0x16 | LDO_LOCAL_EN_BMSK);
471 mdelay(5);
472
473 // Set LD015 to 3.0V
474 pmic_write(LDO15_CNTRL, 0x1E | LDO_LOCAL_EN_BMSK);
475 mdelay(5);
476
477 gpio_set(180, 1); /* bring reset line high */
478 mdelay(10); /* 10 msec before IO can be accessed */
479 if (rc) {
480 return rc;
481 }
482
483 return rc;
484}
485
486#if DISPLAY_TYPE_LCDC
487static struct msm_gpio lcd_panel_gpios[] = {
488 { GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk" },
489 { GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0" },
490 { GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi" },
491 { GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso" }
492};
493
494int lcdc_toshiba_panel_power(int on)
495{
496 int rc, i;
497 struct msm_gpio *gp;
498
499 rc = display_common_power(on);
500 if (rc < 0) {
501 return rc;
502 }
503
504 if (on) {
505 rc = platform_gpios_enable(lcd_panel_gpios,
506 ARRAY_SIZE(lcd_panel_gpios));
507 if(rc)
508 {
509 return rc;
510 }
511 } else { /* off */
512 gp = lcd_panel_gpios;
513 for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
514 /* ouput low */
515 gpio_set(GPIO_PIN(gp->gpio_cfg), 0);
516 gp++;
517 }
518 }
519
520 return rc;
521}
522
523#define SPI_SCLK 45
524#define SPI_CS 46
525#define SPI_MOSI 47
526#define SPI_MISO 48
527
528static void toshiba_spi_write_byte(char dc, unsigned char data)
529{
530 unsigned bit;
531 int bnum;
532
533 gpio_set(SPI_SCLK, 0); /* clk low */
534 /* dc: 0 for command, 1 for parameter */
535 gpio_set(SPI_MOSI, dc);
536 mdelay(1); /* at least 20 ns */
537 gpio_set(SPI_SCLK, 1); /* clk high */
538 mdelay(1); /* at least 20 ns */
539 bnum = 8; /* 8 data bits */
540 bit = 0x80;
541 while (bnum) {
542 gpio_set(SPI_SCLK, 0); /* clk low */
543 if (data & bit)
544 gpio_set(SPI_MOSI, 1);
545 else
546 gpio_set(SPI_MOSI, 0);
547 mdelay(1);
548 gpio_set(SPI_SCLK, 1); /* clk high */
549 mdelay(1);
550 bit >>= 1;
551 bnum--;
552 }
553}
554
555static int toshiba_spi_write (char cmd, unsigned data, int num)
556{
557 char *bp;
558 gpio_set(SPI_CS, 1); /* cs high */
559
560 /* command byte first */
561 toshiba_spi_write_byte(0, cmd);
562
563 /* followed by parameter bytes */
564 if (num) {
565 bp = (char *)&data;;
566 bp += (num - 1);
567 while (num) {
568 toshiba_spi_write_byte(1, *bp);
569 num--;
570 bp--;
571 }
572 }
573 gpio_set(SPI_CS, 0); /* cs low */
574 mdelay(1);
575 return 0;
576}
577
578
579void lcdc_disp_on (void)
580{
581 gpio_set(SPI_CS, 0); /* low */
582 gpio_set(SPI_SCLK, 1); /* high */
583 gpio_set(SPI_MOSI, 0);
584 gpio_set(SPI_MISO, 0);
585
586 if (1) {
587 toshiba_spi_write(0, 0, 0);
588 mdelay(7);
589 toshiba_spi_write(0, 0, 0);
590 mdelay(7);
591 toshiba_spi_write(0, 0, 0);
592 mdelay(7);
593 toshiba_spi_write(0xba, 0x11, 1);
594 toshiba_spi_write(0x36, 0x00, 1);
595 mdelay(1);
596 toshiba_spi_write(0x3a, 0x60, 1);
597 toshiba_spi_write(0xb1, 0x5d, 1);
598 mdelay(1);
599 toshiba_spi_write(0xb2, 0x33, 1);
600 toshiba_spi_write(0xb3, 0x22, 1);
601 mdelay(1);
602 toshiba_spi_write(0xb4, 0x02, 1);
603 toshiba_spi_write(0xb5, 0x1e, 1); /* vcs -- adjust brightness */
604 mdelay(1);
605 toshiba_spi_write(0xb6, 0x27, 1);
606 toshiba_spi_write(0xb7, 0x03, 1);
607 mdelay(1);
608 toshiba_spi_write(0xb9, 0x24, 1);
609 toshiba_spi_write(0xbd, 0xa1, 1);
610 mdelay(1);
611 toshiba_spi_write(0xbb, 0x00, 1);
612 toshiba_spi_write(0xbf, 0x01, 1);
613 mdelay(1);
614 toshiba_spi_write(0xbe, 0x00, 1);
615 toshiba_spi_write(0xc0, 0x11, 1);
616 mdelay(1);
617 toshiba_spi_write(0xc1, 0x11, 1);
618 toshiba_spi_write(0xc2, 0x11, 1);
619 mdelay(1);
620 toshiba_spi_write(0xc3, 0x3232, 2);
621 mdelay(1);
622 toshiba_spi_write(0xc4, 0x3232, 2);
623 mdelay(1);
624 toshiba_spi_write(0xc5, 0x3232, 2);
625 mdelay(1);
626 toshiba_spi_write(0xc6, 0x3232, 2);
627 mdelay(1);
628 toshiba_spi_write(0xc7, 0x6445, 2);
629 mdelay(1);
630 toshiba_spi_write(0xc8, 0x44, 1);
631 toshiba_spi_write(0xc9, 0x52, 1);
632 mdelay(1);
633 toshiba_spi_write(0xca, 0x00, 1);
634 mdelay(1);
635 toshiba_spi_write(0xec, 0x02a4, 2); /* 0x02a4 */
636 mdelay(1);
637 toshiba_spi_write(0xcf, 0x01, 1);
638 mdelay(1);
639 toshiba_spi_write(0xd0, 0xc003, 2); /* c003 */
640 mdelay(1);
641 toshiba_spi_write(0xd1, 0x01, 1);
642 mdelay(1);
643 toshiba_spi_write(0xd2, 0x0028, 2);
644 mdelay(1);
645 toshiba_spi_write(0xd3, 0x0028, 2);
646 mdelay(1);
647 toshiba_spi_write(0xd4, 0x26a4, 2);
648 mdelay(1);
649 toshiba_spi_write(0xd5, 0x20, 1);
650 mdelay(1);
651 toshiba_spi_write(0xef, 0x3200, 2);
652 mdelay(32);
653 toshiba_spi_write(0xbc, 0x80, 1); /* wvga pass through */
654 toshiba_spi_write(0x3b, 0x00, 1);
655 mdelay(1);
656 toshiba_spi_write(0xb0, 0x16, 1);
657 mdelay(1);
658 toshiba_spi_write(0xb8, 0xfff5, 2);
659 mdelay(1);
660 toshiba_spi_write(0x11, 0, 0);
661 mdelay(5);
662 toshiba_spi_write(0x29, 0, 0);
663 mdelay(5);
664 }
665}
666
667void lcdc_on(void)
668{
669 lcdc_clock_init(27648000);
670 lcdc_toshiba_panel_power(1);
671 lcdc_disp_on();
672}
673
674#endif