Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are met: |
| 5 | * * Redistributions of source code must retain the above copyright |
| 6 | * notice, this list of conditions and the following disclaimer. |
| 7 | * * Redistributions in binary form must reproduce the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer in the |
| 9 | * documentation and/or other materials provided with the distribution. |
| 10 | * * Neither the name of The Linux Foundation nor |
| 11 | * the names of its contributors may be used to endorse or promote |
| 12 | * products derived from this software without specific prior written |
| 13 | * permission. |
| 14 | * |
| 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 16 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 17 | * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 18 | * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 20 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 21 | * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; |
| 22 | * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 23 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR |
| 24 | * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF |
| 25 | * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | */ |
| 27 | |
| 28 | #include <mdp5.h> |
| 29 | #include <debug.h> |
| 30 | #include <reg.h> |
| 31 | #include <target/display.h> |
| 32 | #include <platform/timer.h> |
| 33 | #include <platform/iomap.h> |
| 34 | #include <dev/lcdc.h> |
| 35 | #include <dev/fbcon.h> |
| 36 | #include <bits.h> |
| 37 | #include <msm_panel.h> |
| 38 | #include <mipi_dsi.h> |
| 39 | #include <err.h> |
| 40 | #include <clock.h> |
Siddhartha Agrawal | 8d69082 | 2013-01-28 12:18:58 -0800 | [diff] [blame] | 41 | #include <scm.h> |
| 42 | |
| 43 | int restore_secure_cfg(uint32_t id); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 44 | |
| 45 | static int mdp_rev; |
| 46 | |
| 47 | void mdp_set_revision(int rev) |
| 48 | { |
| 49 | mdp_rev = rev; |
| 50 | } |
| 51 | |
| 52 | int mdp_get_revision() |
| 53 | { |
| 54 | return mdp_rev; |
| 55 | } |
| 56 | |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 57 | uint32_t mdss_mdp_intf_offset() |
| 58 | { |
| 59 | uint32_t mdss_mdp_intf_off; |
| 60 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 61 | |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 62 | if ((mdss_mdp_rev == MDSS_MDP_HW_REV_106) || |
| 63 | (mdss_mdp_rev == MDSS_MDP_HW_REV_108)) |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 64 | mdss_mdp_intf_off = 0x59100; |
| 65 | else if (mdss_mdp_rev >= MDSS_MDP_HW_REV_102) |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 66 | mdss_mdp_intf_off = 0; |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 67 | else |
Chandan Uddaraju | aab5851 | 2013-06-25 17:47:39 -0700 | [diff] [blame] | 68 | mdss_mdp_intf_off = 0xEC00; |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 69 | |
| 70 | return mdss_mdp_intf_off; |
| 71 | } |
| 72 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 73 | void mdp_clk_gating_ctrl(void) |
| 74 | { |
| 75 | writel(0x40000000, MDP_CLK_CTRL0); |
| 76 | udelay(20); |
| 77 | writel(0x40000040, MDP_CLK_CTRL0); |
| 78 | writel(0x40000000, MDP_CLK_CTRL1); |
| 79 | writel(0x00400000, MDP_CLK_CTRL3); |
| 80 | udelay(20); |
| 81 | writel(0x00404000, MDP_CLK_CTRL3); |
| 82 | writel(0x40000000, MDP_CLK_CTRL4); |
| 83 | } |
| 84 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 85 | static void mdp_select_pipe_type(struct msm_panel_info *pinfo, |
| 86 | uint32_t *left_pipe, uint32_t *right_pipe) |
| 87 | { |
| 88 | switch (pinfo->pipe_type) { |
| 89 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 90 | *left_pipe = MDP_VP_0_RGB_0_BASE; |
| 91 | *right_pipe = MDP_VP_0_RGB_1_BASE; |
| 92 | break; |
| 93 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 94 | *left_pipe = MDP_VP_0_DMA_0_BASE; |
| 95 | *right_pipe = MDP_VP_0_DMA_1_BASE; |
| 96 | break; |
| 97 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 98 | default: |
| 99 | *left_pipe = MDP_VP_0_VIG_0_BASE; |
| 100 | *right_pipe = MDP_VP_0_VIG_1_BASE; |
| 101 | break; |
| 102 | } |
| 103 | } |
| 104 | |
| 105 | static void mdss_mdp_set_flush(struct msm_panel_info *pinfo, |
| 106 | uint32_t *ctl0_reg_val, uint32_t *ctl1_reg_val) |
| 107 | { |
| 108 | switch (pinfo->pipe_type) { |
| 109 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 110 | *ctl0_reg_val = 0x22048; |
| 111 | *ctl1_reg_val = 0x24090; |
| 112 | break; |
| 113 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 114 | *ctl0_reg_val = 0x22840; |
| 115 | *ctl1_reg_val = 0x25080; |
| 116 | break; |
| 117 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 118 | default: |
| 119 | *ctl0_reg_val = 0x22041; |
| 120 | *ctl1_reg_val = 0x24082; |
| 121 | break; |
| 122 | } |
| 123 | } |
| 124 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 125 | static void mdss_source_pipe_config(struct fbcon_config *fb, struct msm_panel_info |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 126 | *pinfo, uint32_t pipe_base) |
| 127 | { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 128 | uint32_t src_size, out_size, stride; |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 129 | uint32_t fb_off = 0; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 130 | |
| 131 | /* write active region size*/ |
| 132 | src_size = (fb->height << 16) + fb->width; |
| 133 | out_size = src_size; |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 134 | if (pinfo->lcdc.dual_pipe) { |
| 135 | out_size = (fb->height << 16) + (fb->width / 2); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 136 | if ((pipe_base == MDP_VP_0_RGB_1_BASE) || |
| 137 | (pipe_base == MDP_VP_0_DMA_1_BASE) || |
| 138 | (pipe_base == MDP_VP_0_VIG_1_BASE)) |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 139 | fb_off = (pinfo->xres / 2); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | stride = (fb->stride * fb->bpp/8); |
| 143 | |
| 144 | writel(fb->base, pipe_base + PIPE_SSPP_SRC0_ADDR); |
| 145 | writel(stride, pipe_base + PIPE_SSPP_SRC_YSTRIDE); |
| 146 | writel(src_size, pipe_base + PIPE_SSPP_SRC_IMG_SIZE); |
| 147 | writel(out_size, pipe_base + PIPE_SSPP_SRC_SIZE); |
| 148 | writel(out_size, pipe_base + PIPE_SSPP_SRC_OUT_SIZE); |
Siddhartha Agrawal | 6ef1e22 | 2013-06-12 18:24:58 -0700 | [diff] [blame] | 149 | writel(fb_off, pipe_base + PIPE_SSPP_SRC_XY); |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 150 | writel(0x00, pipe_base + PIPE_SSPP_OUT_XY); |
| 151 | |
| 152 | /* Tight Packing 3bpp 0-Alpha 8-bit R B G */ |
| 153 | writel(0x0002243F, pipe_base + PIPE_SSPP_SRC_FORMAT); |
| 154 | writel(0x00020001, pipe_base + PIPE_SSPP_SRC_UNPACK_PATTERN); |
| 155 | writel(0x00, pipe_base + PIPE_SSPP_SRC_OP_MODE); |
| 156 | } |
| 157 | |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 158 | static void mdss_vbif_setup() |
| 159 | { |
| 160 | int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 161 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 162 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 163 | if (!access_secure) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 164 | dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 165 | |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 166 | /* Force VBIF Clocks on, needed for 8974 and 8x26 */ |
| 167 | if (mdp_hw_rev < MDSS_MDP_HW_REV_103) |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 168 | writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); |
| 169 | |
| 170 | /* |
| 171 | * Following configuration is needed because on some versions, |
| 172 | * recommended reset values are not stored. |
| 173 | */ |
| 174 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 175 | MDSS_MDP_HW_REV_100)) { |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 176 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
| 177 | writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); |
| 178 | writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
| 179 | writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); |
| 180 | writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); |
| 181 | writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); |
| 182 | writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); |
Ujwal Patel | 00e1985 | 2013-12-18 20:40:38 -0800 | [diff] [blame] | 183 | } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 184 | MDSS_MDP_HW_REV_101)) { |
Aravind Venkateswaran | d78d159 | 2013-06-19 15:39:54 -0700 | [diff] [blame] | 185 | writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 186 | writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 187 | } |
| 188 | } |
| 189 | } |
| 190 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 191 | static uint32_t mdss_smp_alloc(uint32_t client_id, uint32_t smp_cnt, |
| 192 | uint32_t fixed_smp_cnt, uint32_t free_smp_offset) |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 193 | { |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 194 | uint32_t i, j; |
| 195 | uint32_t reg_val = 0; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 196 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 197 | for (i = fixed_smp_cnt, j = 0; i < smp_cnt; i++) { |
| 198 | /* max 3 MMB per register */ |
| 199 | reg_val |= client_id << (((j++) % 3) * 8); |
| 200 | if ((j % 3) == 0) { |
| 201 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + |
| 202 | free_smp_offset); |
| 203 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + |
| 204 | free_smp_offset); |
| 205 | reg_val = 0; |
| 206 | free_smp_offset += 4; |
| 207 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 208 | } |
| 209 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 210 | if (j % 3) { |
| 211 | writel(reg_val, MMSS_MDP_SMP_ALLOC_W_BASE + free_smp_offset); |
| 212 | writel(reg_val, MMSS_MDP_SMP_ALLOC_R_BASE + free_smp_offset); |
| 213 | free_smp_offset += 4; |
| 214 | } |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 215 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 216 | return free_smp_offset; |
| 217 | } |
| 218 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 219 | static void mdss_smp_setup(struct msm_panel_info *pinfo, uint32_t left_pipe, |
| 220 | uint32_t right_pipe) |
| 221 | |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 222 | { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 223 | uint32_t left_sspp_client_id, right_sspp_client_id; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 224 | uint32_t bpp = 3, free_smp_offset = 0, xres = MDSS_MAX_LINE_BUF_WIDTH; |
| 225 | uint32_t smp_cnt, smp_size = 4096, fixed_smp_cnt = 0; |
| 226 | uint32_t mdss_mdp_rev = readl(MDP_HW_REV); |
| 227 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 228 | if (mdss_mdp_rev == MDSS_MDP_HW_REV_106) { |
| 229 | /* 8Kb per SMP on 8916 */ |
| 230 | smp_size = 8192; |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 231 | } else if (mdss_mdp_rev == MDSS_MDP_HW_REV_108) { |
| 232 | /* 10Kb per SMP on 8939 */ |
| 233 | smp_size = 10240; |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 234 | } else if ((mdss_mdp_rev >= MDSS_MDP_HW_REV_103) && |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 235 | (mdss_mdp_rev < MDSS_MDP_HW_REV_200)) { |
| 236 | smp_size = 8192; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 237 | free_smp_offset = 0xC; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 238 | if (pinfo->pipe_type == MDSS_MDP_PIPE_TYPE_RGB) |
| 239 | fixed_smp_cnt = 2; |
| 240 | else |
| 241 | fixed_smp_cnt = 0; |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 242 | } |
| 243 | |
Padmanabhan Komanduru | 6f0e83d | 2014-03-22 01:12:28 +0530 | [diff] [blame] | 244 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_101) || |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 245 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_106) || |
| 246 | MDSS_IS_MAJOR_MINOR_MATCHING(mdss_mdp_rev, MDSS_MDP_HW_REV_108)) { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 247 | switch (pinfo->pipe_type) { |
| 248 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 249 | left_sspp_client_id = 0x7; /* 7 */ |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 250 | right_sspp_client_id = 0x11; /* 17 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 251 | break; |
| 252 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 253 | left_sspp_client_id = 0x4; /* 4 */ |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 254 | right_sspp_client_id = 0xD; /* 13 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 255 | break; |
| 256 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 257 | default: |
| 258 | left_sspp_client_id = 0x1; /* 1 */ |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 259 | right_sspp_client_id = 0x4; /* 4 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 260 | break; |
| 261 | } |
| 262 | } else { |
| 263 | switch (pinfo->pipe_type) { |
| 264 | case MDSS_MDP_PIPE_TYPE_RGB: |
| 265 | left_sspp_client_id = 0x10; /* 16 */ |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 266 | right_sspp_client_id = 0x11; /* 17 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 267 | break; |
| 268 | case MDSS_MDP_PIPE_TYPE_DMA: |
| 269 | left_sspp_client_id = 0xA; /* 10 */ |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 270 | right_sspp_client_id = 0xD; /* 13 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 271 | break; |
| 272 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 273 | default: |
| 274 | left_sspp_client_id = 0x1; /* 1 */ |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 275 | right_sspp_client_id = 0x4; /* 4 */ |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 276 | break; |
| 277 | } |
| 278 | } |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 279 | |
| 280 | /* Each pipe driving half the screen */ |
| 281 | if (pinfo->lcdc.dual_pipe) |
| 282 | xres /= 2; |
| 283 | |
| 284 | /* bpp = bytes per pixel of input image */ |
| 285 | smp_cnt = (xres * bpp * 2) + smp_size - 1; |
| 286 | smp_cnt /= smp_size; |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 287 | |
| 288 | if (smp_cnt > 4) { |
| 289 | dprintf(CRITICAL, "ERROR: %s: Out of SMP's, cnt=%d! \n", __func__, |
| 290 | smp_cnt); |
| 291 | ASSERT(0); /* Max 4 SMPs can be allocated per client */ |
| 292 | } |
| 293 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 294 | writel(smp_cnt * 0x40, left_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 295 | writel(smp_cnt * 0x80, left_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 296 | writel(smp_cnt * 0xc0, left_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 297 | |
| 298 | if (pinfo->lcdc.dual_pipe) { |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 299 | writel(smp_cnt * 0x40, right_pipe + REQPRIORITY_FIFO_WATERMARK0); |
| 300 | writel(smp_cnt * 0x80, right_pipe + REQPRIORITY_FIFO_WATERMARK1); |
| 301 | writel(smp_cnt * 0xc0, right_pipe + REQPRIORITY_FIFO_WATERMARK2); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 302 | } |
| 303 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 304 | free_smp_offset = mdss_smp_alloc(left_sspp_client_id, smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 305 | fixed_smp_cnt, free_smp_offset); |
| 306 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 307 | mdss_smp_alloc(right_sspp_client_id, smp_cnt, fixed_smp_cnt, |
Ujwal Patel | 1b52ca4 | 2013-12-18 23:32:36 -0800 | [diff] [blame] | 308 | free_smp_offset); |
Siddhartha Agrawal | 76574f8 | 2013-05-23 19:33:01 -0700 | [diff] [blame] | 309 | } |
| 310 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 311 | void mdss_intf_tg_setup(struct msm_panel_info *pinfo, uint32_t intf_base) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 312 | { |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 313 | uint32_t hsync_period, vsync_period; |
| 314 | uint32_t hsync_start_x, hsync_end_x; |
| 315 | uint32_t display_hctl, active_hctl, hsync_ctl, display_vstart, display_vend; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 316 | uint32_t mdss_mdp_intf_off; |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 317 | uint32_t adjust_xres = 0; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 318 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 319 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 320 | |
| 321 | if (pinfo == NULL) |
| 322 | return ERR_INVALID_ARGS; |
| 323 | |
| 324 | lcdc = &(pinfo->lcdc); |
| 325 | if (lcdc == NULL) |
| 326 | return ERR_INVALID_ARGS; |
| 327 | |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 328 | adjust_xres = pinfo->xres; |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 329 | if (pinfo->lcdc.split_display) { |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 330 | adjust_xres /= 2; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 331 | if (intf_base == MDP_INTF_1_BASE) { |
Dhaval Patel | fab2ec0 | 2014-01-03 17:33:39 -0800 | [diff] [blame] | 332 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Ingrid Gallardo | 006f803 | 2014-05-13 10:50:21 -0700 | [diff] [blame] | 333 | writel(BIT(8), MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 334 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 335 | } |
| 336 | } |
| 337 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame^] | 338 | if (pinfo->lcdc.dst_split && (intf_base == MDP_INTF_1_BASE)) { |
| 339 | writel(BIT(16), MDP_REG_PPB0_CONFIG); |
| 340 | writel(BIT(5), MDP_REG_PPB0_CNTL); |
| 341 | } |
| 342 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 343 | mdss_mdp_intf_off = intf_base + mdss_mdp_intf_offset(); |
| 344 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 345 | hsync_period = lcdc->h_pulse_width + |
| 346 | lcdc->h_back_porch + |
Siddhartha Agrawal | d359f14 | 2013-06-12 19:16:08 -0700 | [diff] [blame] | 347 | adjust_xres + lcdc->xres_pad + lcdc->h_front_porch; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 348 | vsync_period = (lcdc->v_pulse_width + |
| 349 | lcdc->v_back_porch + |
| 350 | pinfo->yres + lcdc->yres_pad + |
| 351 | lcdc->v_front_porch); |
| 352 | |
| 353 | hsync_start_x = |
| 354 | lcdc->h_pulse_width + |
| 355 | lcdc->h_back_porch; |
| 356 | hsync_end_x = |
| 357 | hsync_period - lcdc->h_front_porch - 1; |
| 358 | |
| 359 | display_vstart = (lcdc->v_pulse_width + |
| 360 | lcdc->v_back_porch) |
| 361 | * hsync_period + lcdc->hsync_skew; |
| 362 | display_vend = ((vsync_period - lcdc->v_front_porch) * hsync_period) |
| 363 | +lcdc->hsync_skew - 1; |
| 364 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 365 | if (intf_base == MDP_INTF_0_BASE) { /* eDP */ |
| 366 | display_vstart += lcdc->h_pulse_width + lcdc->h_back_porch; |
| 367 | display_vend -= lcdc->h_front_porch; |
| 368 | } |
| 369 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 370 | hsync_ctl = (hsync_period << 16) | lcdc->h_pulse_width; |
| 371 | display_hctl = (hsync_end_x << 16) | hsync_start_x; |
| 372 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 373 | writel(hsync_ctl, MDP_HSYNC_CTL + mdss_mdp_intf_off); |
| 374 | writel(vsync_period*hsync_period, MDP_VSYNC_PERIOD_F0 + |
| 375 | mdss_mdp_intf_off); |
| 376 | writel(0x00, MDP_VSYNC_PERIOD_F1 + mdss_mdp_intf_off); |
| 377 | writel(lcdc->v_pulse_width*hsync_period, |
| 378 | MDP_VSYNC_PULSE_WIDTH_F0 + |
| 379 | mdss_mdp_intf_off); |
| 380 | writel(0x00, MDP_VSYNC_PULSE_WIDTH_F1 + mdss_mdp_intf_off); |
| 381 | writel(display_hctl, MDP_DISPLAY_HCTL + mdss_mdp_intf_off); |
| 382 | writel(display_vstart, MDP_DISPLAY_V_START_F0 + |
| 383 | mdss_mdp_intf_off); |
| 384 | writel(0x00, MDP_DISPLAY_V_START_F1 + mdss_mdp_intf_off); |
| 385 | writel(display_vend, MDP_DISPLAY_V_END_F0 + |
| 386 | mdss_mdp_intf_off); |
| 387 | writel(0x00, MDP_DISPLAY_V_END_F1 + mdss_mdp_intf_off); |
| 388 | writel(0x00, MDP_ACTIVE_HCTL + mdss_mdp_intf_off); |
| 389 | writel(0x00, MDP_ACTIVE_V_START_F0 + mdss_mdp_intf_off); |
| 390 | writel(0x00, MDP_ACTIVE_V_START_F1 + mdss_mdp_intf_off); |
| 391 | writel(0x00, MDP_ACTIVE_V_END_F0 + mdss_mdp_intf_off); |
| 392 | writel(0x00, MDP_ACTIVE_V_END_F1 + mdss_mdp_intf_off); |
| 393 | writel(0xFF, MDP_UNDERFFLOW_COLOR + mdss_mdp_intf_off); |
| 394 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 395 | if (intf_base == MDP_INTF_0_BASE) /* eDP */ |
| 396 | writel(0x212A, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
| 397 | else |
| 398 | writel(0x213F, MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 399 | } |
| 400 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 401 | void mdss_layer_mixer_setup(struct fbcon_config *fb, struct msm_panel_info |
| 402 | *pinfo) |
| 403 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 404 | uint32_t mdp_rgb_size, height, width; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 405 | uint32_t left_staging_level, right_staging_level; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 406 | |
Dhaval Patel | 0a9ab81 | 2013-10-25 10:25:06 -0700 | [diff] [blame] | 407 | height = fb->height; |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 408 | width = fb->width; |
| 409 | |
| 410 | if (pinfo->lcdc.dual_pipe) |
| 411 | width /= 2; |
| 412 | |
| 413 | /* write active region size*/ |
| 414 | mdp_rgb_size = (height << 16) | width; |
| 415 | |
| 416 | writel(mdp_rgb_size, MDP_VP_0_MIXER_0_BASE + LAYER_0_OUT_SIZE); |
| 417 | writel(0x00, MDP_VP_0_MIXER_0_BASE + LAYER_0_OP_MODE); |
| 418 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND_OP); |
| 419 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 420 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND_OP); |
| 421 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 422 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND_OP); |
| 423 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 424 | writel(0x100, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND_OP); |
| 425 | writel(0xFF, MDP_VP_0_MIXER_0_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 426 | |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 427 | switch (pinfo->pipe_type) { |
| 428 | case MDSS_MDP_PIPE_TYPE_RGB: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 429 | left_staging_level = 0x0000200; |
| 430 | right_staging_level = 0x1000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 431 | break; |
| 432 | case MDSS_MDP_PIPE_TYPE_DMA: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 433 | left_staging_level = 0x0040000; |
| 434 | right_staging_level = 0x200000; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 435 | break; |
| 436 | case MDSS_MDP_PIPE_TYPE_VIG: |
| 437 | default: |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 438 | left_staging_level = 0x1; |
| 439 | right_staging_level = 0x8; |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 440 | break; |
| 441 | } |
| 442 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 443 | /* Base layer for layer mixer 0 */ |
| 444 | writel(left_staging_level, MDP_CTL_0_BASE + CTL_LAYER_0); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 445 | |
| 446 | if (pinfo->lcdc.dual_pipe) { |
| 447 | writel(mdp_rgb_size, MDP_VP_0_MIXER_1_BASE + LAYER_0_OUT_SIZE); |
| 448 | writel(0x00, MDP_VP_0_MIXER_1_BASE + LAYER_0_OP_MODE); |
| 449 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND_OP); |
| 450 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_0_BLEND0_FG_ALPHA); |
| 451 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND_OP); |
| 452 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_1_BLEND0_FG_ALPHA); |
| 453 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND_OP); |
| 454 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_2_BLEND0_FG_ALPHA); |
| 455 | writel(0x100, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND_OP); |
| 456 | writel(0xFF, MDP_VP_0_MIXER_1_BASE + LAYER_3_BLEND0_FG_ALPHA); |
| 457 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 458 | /* Base layer for layer mixer 1 */ |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 459 | if (pinfo->lcdc.split_display) |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 460 | writel(right_staging_level, MDP_CTL_1_BASE + CTL_LAYER_1); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 461 | else |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 462 | writel(right_staging_level, MDP_CTL_0_BASE + CTL_LAYER_1); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 463 | } |
| 464 | } |
| 465 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 466 | void mdss_qos_remapper_setup(void) |
| 467 | { |
| 468 | uint32_t mdp_hw_rev = readl(MDP_HW_REV); |
| 469 | uint32_t map; |
| 470 | |
| 471 | if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100) || |
| 472 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 473 | MDSS_MDP_HW_REV_102)) |
| 474 | map = 0xE9; |
| 475 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 476 | MDSS_MDP_HW_REV_101)) |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 477 | map = 0xA5; |
| 478 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Padmanabhan Komanduru | 3908d17 | 2014-06-04 18:00:56 +0530 | [diff] [blame] | 479 | MDSS_MDP_HW_REV_106) || |
| 480 | MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
| 481 | MDSS_MDP_HW_REV_108)) |
Padmanabhan Komanduru | a874ae6 | 2014-05-14 14:59:50 +0530 | [diff] [blame] | 482 | map = 0xAA; |
| 483 | else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 484 | MDSS_MDP_HW_REV_103)) |
| 485 | map = 0xFA; |
| 486 | else |
| 487 | return; |
| 488 | |
| 489 | writel(map, MDP_QOS_REMAPPER_CLASS_0); |
| 490 | } |
| 491 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 492 | static uint32_t mdss_mdp_ctl_out_sel(struct msm_panel_info *pinfo, |
| 493 | int is_main_ctl) |
| 494 | { |
| 495 | if (pinfo->lcdc.pipe_swap) { |
| 496 | if (is_main_ctl) |
| 497 | return BIT(4) | BIT(5); /* Interface 2 */ |
| 498 | else |
| 499 | return BIT(5); /* Interface 1 */ |
| 500 | } else { |
| 501 | if (is_main_ctl) |
| 502 | return BIT(5); /* Interface 1 */ |
| 503 | else |
| 504 | return BIT(4) | BIT(5); /* Interface 2 */ |
| 505 | } |
| 506 | } |
| 507 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 508 | int mdp_dsi_video_config(struct msm_panel_info *pinfo, |
| 509 | struct fbcon_config *fb) |
| 510 | { |
| 511 | int ret = NO_ERROR; |
| 512 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 513 | uint32_t intf_sel = 0x100; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 514 | uint32_t left_pipe, right_pipe; |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 515 | uint32_t reg; |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 516 | |
| 517 | mdss_intf_tg_setup(pinfo, MDP_INTF_1_BASE); |
| 518 | |
| 519 | if (pinfo->mipi.dual_dsi) |
| 520 | mdss_intf_tg_setup(pinfo, MDP_INTF_2_BASE); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 521 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 522 | mdp_clk_gating_ctrl(); |
| 523 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 524 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 525 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 526 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 527 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 528 | mdss_qos_remapper_setup(); |
Siddhartha Agrawal | b1b5a1f | 2013-04-17 19:53:41 -0700 | [diff] [blame] | 529 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 530 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 531 | |
Siddhartha Agrawal | d389339 | 2013-06-11 15:32:19 -0700 | [diff] [blame] | 532 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 533 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 534 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 535 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 536 | |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 537 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 538 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 539 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame^] | 540 | /*If dst_split is enabled only intf 2 needs to be enabled. |
| 541 | CTL_1 path should not be set since CTL_0 itself is going |
| 542 | to split after DSPP block*/ |
| 543 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 544 | if (pinfo->mipi.dual_dsi) { |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame^] | 545 | if (!pinfo->lcdc.dst_split) { |
| 546 | reg = 0x1f00 | mdss_mdp_ctl_out_sel(pinfo,0); |
| 547 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
| 548 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 549 | intf_sel |= BIT(16); /* INTF 2 enable */ |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 550 | } |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 551 | |
| 552 | writel(intf_sel, MDP_DISP_INTF_SEL); |
| 553 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 554 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 555 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 556 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 557 | |
| 558 | return 0; |
| 559 | } |
| 560 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 561 | int mdp_edp_config(struct msm_panel_info *pinfo, struct fbcon_config *fb) |
| 562 | { |
| 563 | int ret = NO_ERROR; |
| 564 | struct lcdc_panel_info *lcdc = NULL; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 565 | uint32_t left_pipe, right_pipe; |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 566 | |
| 567 | mdss_intf_tg_setup(pinfo, MDP_INTF_0_BASE); |
| 568 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 569 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 570 | mdp_clk_gating_ctrl(); |
| 571 | |
| 572 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 573 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 574 | |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 575 | mdss_qos_remapper_setup(); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 576 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 577 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 578 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 579 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 580 | |
| 581 | mdss_layer_mixer_setup(fb, pinfo); |
| 582 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 583 | if (pinfo->lcdc.dual_pipe) |
| 584 | writel(0x181F10, MDP_CTL_0_BASE + CTL_TOP); |
| 585 | else |
| 586 | writel(0x1F10, MDP_CTL_0_BASE + CTL_TOP); |
| 587 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 588 | writel(0x9, MDP_DISP_INTF_SEL); |
| 589 | writel(0x1111, MDP_VIDEO_INTF_UNDERFLOW_CTL); |
| 590 | writel(0x01, MDP_UPPER_NEW_ROI_PRIOR_RO_START); |
| 591 | writel(0x01, MDP_LOWER_NEW_ROI_PRIOR_TO_START); |
| 592 | |
| 593 | return 0; |
| 594 | } |
| 595 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 596 | int mdp_dsi_cmd_config(struct msm_panel_info *pinfo, |
| 597 | struct fbcon_config *fb) |
| 598 | { |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 599 | uint32_t intf_sel = BIT(8); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 600 | uint32_t reg; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 601 | int ret = NO_ERROR; |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 602 | uint32_t left_pipe, right_pipe; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 603 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 604 | struct lcdc_panel_info *lcdc = NULL; |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 605 | uint32_t mdss_mdp_intf_off = 0; |
| 606 | |
| 607 | if (pinfo == NULL) |
| 608 | return ERR_INVALID_ARGS; |
| 609 | |
| 610 | lcdc = &(pinfo->lcdc); |
| 611 | if (lcdc == NULL) |
| 612 | return ERR_INVALID_ARGS; |
| 613 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 614 | if (pinfo->lcdc.split_display) { |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 615 | reg = BIT(1); /* Command mode */ |
| 616 | if (pinfo->lcdc.pipe_swap) |
| 617 | reg |= BIT(4); /* Use intf2 as trigger */ |
| 618 | else |
| 619 | reg |= BIT(8); /* Use intf1 as trigger */ |
| 620 | writel(reg, MDP_REG_SPLIT_DISPLAY_UPPER_PIPE_CTL); |
| 621 | writel(reg, MDP_REG_SPLIT_DISPLAY_LOWER_PIPE_CTL); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 622 | writel(0x1, MDP_REG_SPLIT_DISPLAY_EN); |
| 623 | } |
| 624 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 625 | mdss_mdp_intf_off = mdss_mdp_intf_offset(); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 626 | |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 627 | mdp_clk_gating_ctrl(); |
| 628 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 629 | if (pinfo->mipi.dual_dsi) |
| 630 | intf_sel |= BIT(16); /* INTF 2 enable */ |
| 631 | |
| 632 | writel(intf_sel, MDP_DISP_INTF_SEL); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 633 | |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 634 | mdp_select_pipe_type(pinfo, &left_pipe, &right_pipe); |
Siddhartha Agrawal | 703153e | 2013-05-23 19:35:36 -0700 | [diff] [blame] | 635 | mdss_vbif_setup(); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 636 | mdss_smp_setup(pinfo, left_pipe, right_pipe); |
Dhaval Patel | 069d0af | 2014-01-03 16:55:15 -0800 | [diff] [blame] | 637 | mdss_qos_remapper_setup(); |
| 638 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 639 | mdss_source_pipe_config(fb, pinfo, left_pipe); |
| 640 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 641 | if (pinfo->lcdc.dual_pipe) |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 642 | mdss_source_pipe_config(fb, pinfo, right_pipe); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 643 | |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 644 | mdss_layer_mixer_setup(fb, pinfo); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 645 | |
Siddhartha Agrawal | f0b41a2 | 2013-05-23 20:32:20 -0700 | [diff] [blame] | 646 | writel(0x213F, MDP_INTF_1_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 647 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 1); |
| 648 | writel(reg, MDP_CTL_0_BASE + CTL_TOP); |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 649 | |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 650 | if (pinfo->mipi.dual_dsi) { |
| 651 | writel(0x213F, MDP_INTF_2_BASE + MDP_PANEL_FORMAT + mdss_mdp_intf_off); |
Aravind Venkateswaran | 5c1c80f | 2014-06-27 17:20:25 -0700 | [diff] [blame] | 652 | reg = 0x21f00 | mdss_mdp_ctl_out_sel(pinfo, 0); |
| 653 | writel(reg, MDP_CTL_1_BASE + CTL_TOP); |
Dhaval Patel | 6ff630b | 2014-01-03 17:29:22 -0800 | [diff] [blame] | 654 | } |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 655 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 656 | return ret; |
| 657 | } |
| 658 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 659 | int mdp_dsi_video_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 660 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 661 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 662 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 663 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 664 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 665 | writel(0x01, MDP_INTF_1_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 666 | |
| 667 | return NO_ERROR; |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 668 | } |
| 669 | |
| 670 | int mdp_dsi_video_off() |
| 671 | { |
| 672 | if(!target_cont_splash_screen()) |
| 673 | { |
Siddhartha Agrawal | 1a87c5d | 2013-03-06 19:07:53 -0800 | [diff] [blame] | 674 | writel(0x00000000, MDP_INTF_1_TIMING_ENGINE_EN + |
| 675 | mdss_mdp_intf_offset()); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 676 | mdelay(60); |
| 677 | /* Ping-Pong done Tear Check Read/Write */ |
| 678 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 679 | writel(0xFF777713, MDP_INTR_CLEAR); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 680 | } |
| 681 | |
Siddhartha Agrawal | 6a59822 | 2013-02-17 18:33:27 -0800 | [diff] [blame] | 682 | writel(0x00000000, MDP_INTR_EN); |
| 683 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 684 | return NO_ERROR; |
| 685 | } |
| 686 | |
| 687 | int mdp_dsi_cmd_off() |
| 688 | { |
Siddhartha Agrawal | 7dc3aa9 | 2013-04-21 16:04:26 -0700 | [diff] [blame] | 689 | if(!target_cont_splash_screen()) |
| 690 | { |
| 691 | /* Ping-Pong done Tear Check Read/Write */ |
| 692 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 693 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 694 | } |
| 695 | writel(0x00000000, MDP_INTR_EN); |
| 696 | |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 697 | return NO_ERROR; |
| 698 | } |
| 699 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 700 | int mdp_dma_on(struct msm_panel_info *pinfo) |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 701 | { |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 702 | uint32_t ctl0_reg_val, ctl1_reg_val; |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 703 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 704 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
| 705 | writel(ctl1_reg_val, MDP_CTL_1_BASE + CTL_FLUSH); |
Siddhartha Agrawal | d32ba68 | 2013-06-18 12:37:41 -0700 | [diff] [blame] | 706 | writel(0x01, MDP_CTL_0_BASE + CTL_START); |
Siddhartha Agrawal | 7e2e215 | 2013-01-23 17:06:58 -0800 | [diff] [blame] | 707 | return NO_ERROR; |
| 708 | } |
| 709 | |
| 710 | void mdp_disable(void) |
| 711 | { |
| 712 | |
| 713 | } |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 714 | |
Jayant Shekhar | 32397f9 | 2014-03-27 13:30:41 +0530 | [diff] [blame] | 715 | int mdp_edp_on(struct msm_panel_info *pinfo) |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 716 | { |
Jayant Shekhar | 0737392 | 2014-05-26 10:13:49 +0530 | [diff] [blame] | 717 | uint32_t ctl0_reg_val, ctl1_reg_val; |
| 718 | mdss_mdp_set_flush(pinfo, &ctl0_reg_val, &ctl1_reg_val); |
Jayant Shekhar | 03e1a22 | 2014-05-22 11:03:53 +0530 | [diff] [blame] | 719 | writel(ctl0_reg_val, MDP_CTL_0_BASE + CTL_FLUSH); |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 720 | writel(0x01, MDP_INTF_0_TIMING_ENGINE_EN + mdss_mdp_intf_offset()); |
| 721 | return NO_ERROR; |
| 722 | } |
| 723 | |
| 724 | int mdp_edp_off(void) |
| 725 | { |
| 726 | if (!target_cont_splash_screen()) { |
| 727 | |
| 728 | writel(0x00000000, MDP_INTF_0_TIMING_ENGINE_EN + |
| 729 | mdss_mdp_intf_offset()); |
| 730 | mdelay(60); |
| 731 | /* Ping-Pong done Tear Check Read/Write */ |
| 732 | /* Underrun(Interface 0/1/2/3) VSYNC Interrupt Enable */ |
| 733 | writel(0xFF777713, MDP_INTR_CLEAR); |
| 734 | writel(0x00000000, MDP_INTR_EN); |
| 735 | } |
| 736 | |
Kuogee Hsieh | ad69c3c | 2013-08-01 14:34:29 -0700 | [diff] [blame] | 737 | writel(0x00000000, MDP_INTR_EN); |
| 738 | |
Asaf Penso | afb8eb7 | 2013-07-07 18:17:59 +0300 | [diff] [blame] | 739 | return NO_ERROR; |
| 740 | } |