Amol Jadi | f3d5a89 | 2013-07-23 16:09:44 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | #ifndef _USB30_DWC_H |
| 29 | #define _USB30_DWC_H |
| 30 | |
| 31 | #include <bits.h> |
| 32 | |
| 33 | |
| 34 | /********************* START: h/w defined values ******************************/ |
| 35 | /* device command ids */ |
| 36 | typedef enum |
| 37 | { |
| 38 | DWC_DEV_CMD_TX_SET_LINK_FN_LMP_VAL = 0x01, |
| 39 | DWC_DEV_CMD_SET_PERIODIC_PARAMS_VAL = 0x02, |
| 40 | DWC_DEV_CMD_TX_FN_WAKE_DEV_NOTIFY_VAL = 0x03, |
| 41 | DWC_DEV_CMD_SET_SCRATCHPAD_BUF_LO_VAL = 0x04, |
| 42 | DWC_DEV_CMD_SET_SCRATCHPAD_BUF_HI_VAL = 0x05, |
| 43 | DWC_DEV_CMD_TX_FN_HOST_REQ_NOTIFY_VAL = 0x06, |
| 44 | DWC_DEV_CMD_TX_DEVICE_NOTIFY_VAL = 0x07, |
| 45 | DWC_DEV_CMD_SELECTED_FIFO_FLUSH_VAL = 0x09, |
| 46 | DWC_DEV_CMD_ALL_FIFO_FLUSH_VAL = 0x0A, |
| 47 | DWC_DEV_CMD_SET_EP_NRDY_VAL = 0x0C, |
| 48 | DWC_DEV_CMD_RUN_SOC_LOOPBACK_TEST_VAL = 0x10, |
| 49 | } dwc_dev_cmd_t; |
| 50 | |
| 51 | /* ep command ids */ |
| 52 | typedef enum |
| 53 | { |
| 54 | DEPCMD_CMD_SET_EP_CONF = 0x1, |
| 55 | DEPCMD_CMD_SET_TR_CONF = 0x2, |
| 56 | DEPCMD_CMD_GET_EP_STATE = 0x3, |
| 57 | DEPCMD_CMD_SET_STALL = 0x4, |
| 58 | DEPCMD_CMD_CLEAR_STALL = 0x5, |
| 59 | DEPCMD_CMD_START_TRANSFER = 0x6, |
| 60 | DEPCMD_CMD_UPDATE_TRANSFER = 0x7, |
| 61 | DEPCMD_CMD_END_TRANSFER = 0x8, |
| 62 | DEPCMD_CMD_START_NEW_CONF = 0x9, |
| 63 | } dwc_dep_cmd_id_t; |
| 64 | |
| 65 | /* ep type */ |
| 66 | typedef enum { |
| 67 | EP_TYPE_CONTROL = 0x0, |
| 68 | EP_TYPE_ISOCHRONOUS = 0x1, |
| 69 | EP_TYPE_BULK = 0x2, |
| 70 | EP_TYPE_INTERRUPT = 0x3, |
| 71 | } dwc_ep_type_t; |
| 72 | |
| 73 | /* ep direction */ |
| 74 | typedef enum |
| 75 | { |
| 76 | DWC_EP_DIRECTION_OUT = 0x0, |
| 77 | DWC_EP_DIRECTION_IN = 0x1 |
| 78 | } dwc_ep_direction_t; |
| 79 | |
| 80 | |
| 81 | /* macros to parse event information */ |
| 82 | #define DWC_EVENT_IS_DEVICE_EVENT(_event) BIT_SHIFT(_event, 0) |
| 83 | |
| 84 | /* parse device events */ |
| 85 | #define DWC_EVENT_DEVICE_EVENT_ID(_event) BITS_SHIFT(_event, 11, 8) |
| 86 | #define DWC_EVENT_DEVICE_EVENT_INFO(_event) BITS_SHIFT(_event, 24, 16) |
| 87 | |
| 88 | #define DWC_EVENT_DEVICE_EVENT_INFO_SS_EVENT(_event_info) BIT_SHIFT(_event_info, 4) |
| 89 | #define DWC_EVENT_DEVICE_EVENT_INFO_LINK_STATE(_event_info) BITS_SHIFT(_event_info, 3, 0) |
| 90 | |
| 91 | /* parse ep events */ |
| 92 | #define DWC_EVENT_EP_EVENT_PARAM(_event) BITS_SHIFT(_event, 31, 16) |
| 93 | #define DWC_EVENT_EP_EVENT_CMD_TYPE(_event) BITS_SHIFT(_event, 27, 24) |
| 94 | #define DWC_EVENT_EP_EVENT_XFER_RES_IDX(_event) BITS_SHIFT(_event, 22, 16) |
| 95 | #define DWC_EVENT_EP_EVENT_STATUS(_event) BITS_SHIFT(_event, 15, 12) |
| 96 | #define DWC_EVENT_EP_EVENT_CTRL_STAGE(_event) BITS_SHIFT(_event, 13, 12) |
| 97 | #define DWC_EVENT_EP_EVENT_ID(_event) BITS_SHIFT(_event, 9, 6) |
| 98 | #define DWC_EVENT_EP_EVENT_EP_NUM(_event) BITS_SHIFT(_event, 5, 1) |
| 99 | |
| 100 | /* device event ids */ |
| 101 | typedef enum |
| 102 | { |
| 103 | DWC_EVENT_DEVICE_EVENT_ID_VENDOR_DEVICE_TEST_LMP = 12, |
| 104 | DWC_EVENT_DEVICE_EVENT_ID_BUFFER_OVERFLOW = 11, |
| 105 | DWC_EVENT_DEVICE_EVENT_ID_GENERIC_CMD_COMPLETE = 10, |
| 106 | DWC_EVENT_DEVICE_EVENT_ID_ERRATIC_ERROR = 9, |
| 107 | DWC_EVENT_DEVICE_EVENT_ID_SOF = 7, |
| 108 | DWC_EVENT_DEVICE_EVENT_ID_SUSPEND_ENTRY = 6, |
| 109 | DWC_EVENT_DEVICE_EVENT_ID_HIBER = 5, |
| 110 | DWC_EVENT_DEVICE_EVENT_ID_WAKEUP = 4, |
| 111 | DWC_EVENT_DEVICE_EVENT_ID_USB_LINK_STATUS_CHANGE = 3, |
| 112 | DWC_EVENT_DEVICE_EVENT_ID_CONNECT_DONE = 2, |
| 113 | DWC_EVENT_DEVICE_EVENT_ID_USB_RESET = 1, |
| 114 | DWC_EVENT_DEVICE_EVENT_ID_DISCONNECT = 0, |
| 115 | DWC_EVENT_DEVICE_EVENTS_ALL = BITS(0xFFFFFFFF, 12, 0) |
| 116 | } dwc_event_device_event_id_t; |
| 117 | |
| 118 | /* ep event ids */ |
| 119 | typedef enum |
| 120 | { |
| 121 | DWC_EVENT_EP_CMD_COMPLETE = 7, |
| 122 | DWC_EVENT_EP_XFER_NOT_READY = 3, |
| 123 | DWC_EVENT_EP_XFER_IN_PROGRESS = 2, |
| 124 | DWC_EVENT_EP_XFER_COMPLETE = 1, |
| 125 | } dwc_event_ep_event_id_t; |
| 126 | |
| 127 | /* values for control stage in ep events */ |
| 128 | #define CONTROL_DATA_REQUEST 1 |
| 129 | #define CONTROL_STATUS_REQUEST 2 |
| 130 | |
| 131 | /* values for event status field for transfer complete event */ |
| 132 | #define DWC_XFER_COMPLETE_EVT_STATUS_SHORT_PKT 0x2 |
| 133 | #define DWC_XFER_COMPLETE_EVT_STATUS_IOC 0x4 |
| 134 | #define DWC_XFER_COMPLETE_EVT_STATUS_LST 0x8 |
| 135 | |
| 136 | /* master bus data width (DWC_USB3_MDWIDTH in snps data book) */ |
| 137 | #define DWC_MASTER_BUS_WIDTH 8 |
| 138 | |
| 139 | /* super speed link states */ |
| 140 | typedef enum |
| 141 | { |
| 142 | U0 = 0x0, |
| 143 | U1, |
| 144 | U2, |
| 145 | U3, |
| 146 | SS_DIS, |
| 147 | RX_DET, |
| 148 | SS_INACT, |
| 149 | POLL, |
| 150 | RECOV, |
| 151 | HRESET, |
| 152 | CMPLY, |
| 153 | LPBK, |
| 154 | RESUME_RESET = 0xF, |
| 155 | } dwc_event_device_ss_link_state_t; |
| 156 | |
| 157 | /* high speed link states */ |
| 158 | typedef enum |
| 159 | { |
| 160 | ON = 0x0, |
| 161 | L1 = 0x2, |
| 162 | L2 = 0x3, |
| 163 | DISCONNECTED = 0x4, |
| 164 | EARLY_SUSPEND = 0x5, |
| 165 | RESET = 0xE, |
| 166 | RESUME = 0xF, |
| 167 | } dwc_event_device_hs_link_state_t; |
| 168 | |
| 169 | /* action for set config*/ |
| 170 | enum |
| 171 | { |
| 172 | SET_CONFIG_ACTION_INIT = 0x0, |
| 173 | SET_CONFIG_ACTION_RESTORE = 0x1, |
| 174 | SET_CONFIG_ACTION_MODIFY = 0x2, |
| 175 | }; |
| 176 | |
| 177 | /* EP Cmd Param bits */ |
| 178 | #define DEPCMDPAR1_USB_EP_NUM_BIT 26 |
| 179 | #define DEPCMDPAR1_USB_EP_DIR_BIT 25 |
| 180 | |
| 181 | #define DEPCMDPAR0_ACTION_BIT 30 |
| 182 | #define DEPCMDPAR0_BURST_SIZE_BIT 22 |
| 183 | #define DEPCMDPAR0_FIFO_NUM_BIT 17 |
| 184 | #define DEPCMDPAR0_MAX_PKT_SIZE_BIT 3 |
| 185 | #define DEPCMDPAR0_EP_TYPE_BIT 1 |
| 186 | |
| 187 | #define DEPCMDPAR2_XFER_N_RDY_BIT 10 |
| 188 | #define DEPCMDPAR2_XFER_IN_PROG_BIT 9 |
| 189 | #define DEPCMDPAR2_XFER_COMPLETE_BIT 8 |
| 190 | |
| 191 | enum |
| 192 | { |
| 193 | DSTS_CONNECTSPD_HS = 0, |
| 194 | DSTS_CONNECTSPD_FS1 = 1, /* phy clk @ 30 or 60 MHz */ |
| 195 | DSTS_CONNECTSPD_LS = 2, |
| 196 | DSTS_CONNECTSPD_FS2 = 3, /* phy clk @ 48 MHz */ |
| 197 | DSTS_CONNECTSPD_SS = 4, |
| 198 | }; |
| 199 | |
| 200 | /**************************** TRB (Transfer Request Block)*********************/ |
| 201 | #define DWC_TRB_F1_PTR_LOW_BMSK 0xFFFFFFFF |
| 202 | #define DWC_TRB_F1_PTR_LOW_SHFT 0 |
| 203 | |
| 204 | #define DWC_TRB_F2_PTR_HIGH_BMSK 0xFFFFFFFF |
| 205 | #define DWC_TRB_F2_PTR_HIGH_SHFT 0 |
| 206 | |
| 207 | #define DWC_TRB_F3_BUFSIZ_BMSK 0x00FFFFFF |
| 208 | #define DWC_TRB_F3_BUFSIZ_SHFT 0 |
| 209 | #define DWC_TRB_F3_PCM1_BMSK 0x03000000 |
| 210 | #define DWC_TRB_F3_PCM1_SHFT 24 |
| 211 | #define DWC_TRB_F3_TRBSTS_BMSK 0xF0000000 |
| 212 | #define DWC_TRB_F3_TRBSTS_SHFT 28 |
| 213 | |
| 214 | #define DWC_TRB_F4_IOC_BMSK 0x800 |
| 215 | #define DWC_TRB_F4_IOC_SHFT 11 |
| 216 | |
| 217 | #define DWC_TRB_F4_ISP_BMSK 0x400 |
| 218 | #define DWC_TRB_F4_ISP_SHFT 10 |
| 219 | |
| 220 | #define DWC_TRB_F4_TRBCTL_BMSK 0x3F0 |
| 221 | #define DWC_TRB_F4_TRBCTL_SHFT 4 |
| 222 | |
| 223 | #define DWC_TRB_F4_CSP_BMSK 0x8 |
| 224 | #define DWC_TRB_F4_CSP_SHFT 3 |
| 225 | |
| 226 | #define DWC_TRB_F4_CHN_BMSK 0x4 |
| 227 | #define DWC_TRB_F4_CHN_SHFT 2 |
| 228 | |
| 229 | #define DWC_TRB_F4_LST_BMSK 0x2 |
| 230 | #define DWC_TRB_F4_LST_SHFT 1 |
| 231 | |
| 232 | #define DWC_TRB_F4_HWO_BMSK 0x1 |
| 233 | #define DWC_TRB_F4_HWO_SHFT 0 |
| 234 | /**************************** END - TRB ***************************************/ |
| 235 | |
| 236 | #define DWC_MAX_BYTES_PER_TRB 0x00FFFFFF |
| 237 | |
| 238 | /********************* END: h/w defined values ********************************/ |
| 239 | |
| 240 | |
| 241 | |
| 242 | /******************** START: local data not needed by external APIs ***********/ |
| 243 | |
| 244 | /* event buffer: used to manage various controller events */ |
| 245 | typedef struct { |
| 246 | uint32_t *buf; /* ptr to event buffer. */ |
| 247 | uint16_t buf_size; /* size of buf. */ |
| 248 | uint16_t max_index; /* max index value. initialized once. used to track rollover. */ |
| 249 | uint16_t index; /* index into the buf for reading next event */ |
| 250 | } dwc_event_buf_t; |
| 251 | |
| 252 | /* device command */ |
| 253 | typedef struct { |
| 254 | uint32_t cmd; |
| 255 | uint32_t param; |
| 256 | } dwc_device_cmd_t; |
| 257 | |
| 258 | /* ep command */ |
| 259 | typedef struct { |
| 260 | uint32_t cmd; |
| 261 | uint8_t xfer_resource_index; |
| 262 | uint32_t param2; |
| 263 | uint32_t param1; |
| 264 | uint32_t param0; |
| 265 | } dwc_ep_cmd_t; |
| 266 | |
| 267 | /* state of data transfer on an ep */ |
| 268 | typedef enum |
| 269 | { |
| 270 | EP_STATE_INIT = 0x0, /* initial state. cannot start transfer. */ |
| 271 | EP_STATE_INACTIVE = 0x1, /* start xfer has not been issued. transfer is NOT in progress. start transfer can be issued ONLY in this state. */ |
| 272 | EP_STATE_START_TRANSFER = 0x2, /* start xfer is issued but cmd is not completed yet. */ |
| 273 | EP_STATE_XFER_IN_PROG = 0x3, /* start xfer is issued and xfer is in progress. */ |
| 274 | } dwc_ep_state_t; |
| 275 | |
| 276 | /* control fsm states: states to manage control transfers */ |
| 277 | typedef enum |
| 278 | { |
| 279 | EP_FSM_INIT = 0, |
| 280 | EP_FSM_SETUP = 1, |
| 281 | EP_FSM_CTRL_DATA = 2, |
| 282 | EP_FSM_WAIT_FOR_HOST_2 = 3, /* 2-stage transfer wait-for-host stage */ |
| 283 | EP_FSM_WAIT_FOR_HOST_3 = 4, /* 3-stage transfer wait-for-host stage */ |
| 284 | EP_FSM_STATUS_2 = 5, |
| 285 | EP_FSM_STATUS_3 = 6, |
| 286 | EP_FSM_STALL = 7, |
| 287 | } dwc_ctrl_fsm_t; |
| 288 | |
| 289 | /* TRB type */ |
| 290 | typedef enum |
| 291 | { |
| 292 | TRBCTL_NORMAL = 1, |
| 293 | TRBCTL_CONTROL_SETUP = 2, |
| 294 | TRBCTL_CONTROL_STATUS_2 = 3, |
| 295 | TRBCTL_CONTROL_STATUS_3 = 4, |
| 296 | TRBCTL_CONTROL_DATA = 5, |
| 297 | TRBCTL_LINK_TRB = 8, |
| 298 | } dwc_trb_trbctl_t; |
| 299 | |
| 300 | /* data transfer request */ |
| 301 | typedef struct |
| 302 | { |
| 303 | uint8_t *data; |
| 304 | uint32_t len; |
| 305 | dwc_trb_trbctl_t trbctl; |
| 306 | void *context; |
| 307 | void (*callback)(void *context, uint32_t actual, int status); |
| 308 | } dwc_request_t; |
| 309 | |
| 310 | /******************** END: local data not needed by external APIs *************/ |
| 311 | |
| 312 | |
| 313 | /******************** START: data needed by external APIs *********************/ |
| 314 | |
| 315 | /* TRB fields */ |
| 316 | typedef struct |
| 317 | { |
| 318 | uint32_t f1; |
| 319 | uint32_t f2; |
| 320 | uint32_t f3; |
| 321 | uint32_t f4; |
| 322 | } dwc_trb_t; |
| 323 | |
| 324 | /* index into the ep array of the dwc device */ |
| 325 | #define DWC_EP_INDEX(_usb_ep, _direction) (((_usb_ep) << 1) | (_direction)) |
| 326 | |
| 327 | /* phyical ep number: same as ep index. */ |
| 328 | #define DWC_EP_PHY_NUM(_usb_ep, _direction) (((_usb_ep) << 1) | (_direction)) |
| 329 | |
| 330 | /* since we assume non-flexible mapping, phy_num is same as index. */ |
| 331 | #define DWC_EP_PHY_TO_INDEX(_ep_phy_num) (_ep_phy_num) |
| 332 | |
| 333 | typedef void (*dwc_transfer_callback_t)(void *context, uint32_t actual, int status); |
| 334 | |
| 335 | /* length of zero-length-packet */ |
| 336 | /* TODO: shouldn't this be same a max pkt size for the EP |
| 337 | * which is specified by udc? fastboot doesn't need this. |
| 338 | * So this is not verified. |
| 339 | */ |
| 340 | #define DWC_ZLP_BUF_SIZE 512 |
| 341 | |
| 342 | /* Structure to keep all information about an endpoint */ |
| 343 | typedef struct |
| 344 | { |
| 345 | uint8_t number; /* usb ep number */ |
| 346 | dwc_ep_direction_t dir; /* usb ep direction */ |
| 347 | dwc_ep_type_t type; /* ctrl/blk etc. */ |
| 348 | uint16_t max_pkt_size; /* max packet size */ |
| 349 | uint8_t zlp; /* uses zero length pkt to terminate xfer */ |
| 350 | uint32_t burst_size; /* max packets to transfer before waiting for ack */ |
| 351 | |
| 352 | uint8_t phy_num; /* physical EP to which this usb ep is mapped */ |
| 353 | uint8_t tx_fifo_num; /* which TX FIFO to use. only applies to IN endpoints */ |
| 354 | |
| 355 | uint8_t zlp_buf[DWC_ZLP_BUF_SIZE]; /* buffer needed to pad when OUT requests are not exact multiple of max_pkt_size and for zlp */ |
| 356 | |
| 357 | uint8_t resource_idx; /* assigned by h/w on each start xfer cmd. Needed to stop/update xfers. */ |
| 358 | |
| 359 | dwc_trb_t *trb; /* ptr to the first TRB in the chain. */ |
| 360 | uint32_t trb_count; /* size of TRB chain. */ |
| 361 | uint32_t trb_queued; /* number of TRBs queued in the current request. */ |
| 362 | uint32_t bytes_queued; /* number of bytes queued in the current request. */ |
| 363 | dwc_request_t req; /* transfer request that is currently queued on this ep. */ |
| 364 | |
| 365 | dwc_ep_state_t state; /* data transfer state of the ep. */ |
| 366 | |
| 367 | } dwc_ep_t; |
| 368 | |
| 369 | |
| 370 | /* dwc device events */ |
| 371 | typedef enum |
| 372 | { |
| 373 | DWC_NOTIFY_EVENT_OFFLINE, |
| 374 | DWC_NOTIFY_EVENT_CONNECTED_LS, |
| 375 | DWC_NOTIFY_EVENT_CONNECTED_FS, |
| 376 | DWC_NOTIFY_EVENT_CONNECTED_HS, |
| 377 | DWC_NOTIFY_EVENT_CONNECTED_SS, |
| 378 | DWC_NOTIFY_EVENT_DISCONNECTED, |
| 379 | } dwc_notify_event_t; |
| 380 | |
| 381 | /* maximum number of endpoints supported. */ |
| 382 | #define DWC_MAX_NUM_OF_EP 4 |
| 383 | |
| 384 | /* length of setup packet */ |
| 385 | #define DWC_SETUP_PKT_LEN 8 |
| 386 | |
| 387 | enum |
| 388 | { |
| 389 | DWC_SETUP_ERROR = -1, |
| 390 | DWC_SETUP_2_STAGE = 2, |
| 391 | DWC_SETUP_3_STAGE = 3, |
| 392 | }; |
| 393 | |
| 394 | /* Structure to keep all DWC device information. */ |
| 395 | typedef struct |
| 396 | { |
| 397 | void *base; /* base address for snps core registers */ |
| 398 | uint32_t core_id; /* snps core version. read from h/w during init */ |
| 399 | |
| 400 | dwc_ep_t ep[DWC_MAX_NUM_OF_EP]; /* array of endpoint data */ |
| 401 | dwc_event_buf_t event_buf; /* event buffer management */ |
| 402 | dwc_ctrl_fsm_t ctrl_state; /* states to manage control transfers : setup/data/wait/status */ |
| 403 | |
| 404 | uint8_t *setup_pkt; /* Buffer for the received setup packet */ |
| 405 | |
| 406 | /* callback into client to notify device events: online/offline/connect speed */ |
| 407 | void *notify_context; |
| 408 | void (*notify)(void *context, dwc_notify_event_t event); |
| 409 | |
| 410 | /* callback into client to process the setup msgs. */ |
| 411 | void *setup_context; |
| 412 | int (*setup_handler)(void* context, uint8_t* data); |
| 413 | |
| 414 | } dwc_dev_t; |
| 415 | |
| 416 | |
| 417 | /* config data to initialize dwc layer */ |
| 418 | typedef struct |
| 419 | { |
| 420 | void *base; /* dwc base address */ |
| 421 | uint32_t *event_buf; /* buffer to be used for h/w events */ |
| 422 | uint16_t event_buf_size; /* buffer size */ |
| 423 | |
| 424 | /* callback for dwc events */ |
| 425 | void *notify_context; |
| 426 | void (*notify)(void *context, dwc_notify_event_t event); |
| 427 | |
| 428 | /* callback for handling setup packets */ |
| 429 | void *setup_context; |
| 430 | int (*setup_handler)(void *context, uint8_t *data); |
| 431 | |
| 432 | } dwc_config_t; |
| 433 | |
| 434 | /********************************* dwc global apis ****************************/ |
| 435 | |
| 436 | /* generic apis */ |
| 437 | dwc_dev_t* dwc_init(dwc_config_t *config); |
| 438 | void dwc_reset(dwc_dev_t *dev, uint8_t reset); |
| 439 | |
| 440 | /* phy specific apis */ |
| 441 | void dwc_phy_digital_reset(dwc_dev_t *dev); |
| 442 | void dwc_usb2_phy_soft_reset(dwc_dev_t *dev); |
| 443 | void dwc_ss_phy_workaround_12(dwc_dev_t *dev); |
| 444 | |
| 445 | /* device specific apis */ |
| 446 | void dwc_device_init(dwc_dev_t *dev); |
| 447 | void dwc_device_reset(dwc_dev_t *dev); |
| 448 | void dwc_device_run(dwc_dev_t *dev, uint8_t run); |
| 449 | void dwc_device_set_addr(dwc_dev_t *dev, uint16_t addr); |
| 450 | void dwc_device_set_configuration(dwc_dev_t *dev); |
| 451 | void dwc_device_set_periodic_param(dwc_dev_t *dev, uint32_t val); |
| 452 | void dwc_device_add_ep(dwc_dev_t *dev, dwc_ep_t new_ep); |
| 453 | |
| 454 | /* data transfer apis */ |
| 455 | int dwc_transfer_request(dwc_dev_t *dwc, |
| 456 | uint8_t usb_ep, |
| 457 | dwc_ep_direction_t dir, |
| 458 | void *buf, |
| 459 | uint32_t len, |
| 460 | dwc_transfer_callback_t callback, |
| 461 | void *callback_context); |
| 462 | |
| 463 | /******************** END: data needed by external APIs *********************/ |
| 464 | /* static apis */ |
| 465 | |
| 466 | /* command complete event handler */ |
| 467 | static void dwc_event_handle_cmd_complete(dwc_dev_t *dev, uint32_t *event); |
| 468 | |
| 469 | /* device event handler */ |
| 470 | static void dwc_event_handler_device(dwc_dev_t *dev, uint32_t *event); |
| 471 | static void dwc_event_device_link_status_change(dwc_dev_t *dev, uint32_t *event); |
| 472 | static void dwc_event_device_reset(dwc_dev_t *dev); |
| 473 | static void dwc_event_device_connect_done(dwc_dev_t *dev); |
| 474 | static void dwc_event_device_disconnect(dwc_dev_t *dev); |
| 475 | |
| 476 | /* bulk ep event handling functions */ |
| 477 | static void dwc_event_handler_ep_bulk(dwc_dev_t *dev, uint32_t *event); |
| 478 | static void dwc_event_handler_ep_bulk_state_inactive(dwc_dev_t *dev, uint32_t *event); |
| 479 | static void dwc_event_handler_ep_bulk_state_xfer_in_prog(dwc_dev_t *dev, uint32_t *event); |
| 480 | static void dwc_ep_bulk_state_inactive_enter(dwc_dev_t *dev, uint8_t ep_phy_num); |
| 481 | |
| 482 | /* control ep event handling functions */ |
| 483 | static void dwc_event_handler_ep_ctrl(dwc_dev_t *dev, uint32_t *event); |
| 484 | |
| 485 | static void dwc_ep_ctrl_state_setup_enter(dwc_dev_t *dev); |
| 486 | static void dwc_event_handler_ep_ctrl_state_setup(dwc_dev_t *dev, uint32_t *event); |
| 487 | static void dwc_event_handler_ep_ctrl_state_data(dwc_dev_t *dev, uint32_t *event); |
| 488 | static void dwc_event_handler_ep_ctrl_state_wait_for_host_2(dwc_dev_t *dev, uint32_t *event); |
| 489 | static void dwc_event_handler_ep_ctrl_state_wait_for_host_3(dwc_dev_t *dev, uint32_t *event); |
| 490 | static void dwc_event_handler_ep_ctrl_state_status_2(dwc_dev_t *dev, uint32_t *event); |
| 491 | static void dwc_event_handler_ep_ctrl_state_status_3(dwc_dev_t *dev, uint32_t *event); |
| 492 | static void dwc_event_handler_ep_ctrl_state_stall(dwc_dev_t *dev, uint32_t *event); |
| 493 | |
| 494 | static enum handler_return dwc_irq_handler_ee1(void* arg); |
| 495 | static void dwc_ep_config_init_enable(dwc_dev_t *dev, uint8_t index); |
| 496 | |
| 497 | static int dwc_request_queue(dwc_dev_t *dev, uint8_t ep_phy_num, dwc_request_t *req); |
| 498 | #endif |