Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #include <debug.h> |
| 30 | #include <platform/iomap.h> |
| 31 | #include <reg.h> |
| 32 | #include <target.h> |
| 33 | #include <platform.h> |
| 34 | #include <uart_dm.h> |
| 35 | #include <mmc.h> |
| 36 | #include <platform/gpio.h> |
| 37 | #include <dev/keys.h> |
| 38 | #include <spmi_v2.h> |
| 39 | #include <pm8x41.h> |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 40 | #include <pm8x41_hw.h> |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 41 | #include <board.h> |
| 42 | #include <baseband.h> |
| 43 | #include <hsusb.h> |
| 44 | #include <scm.h> |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 45 | #include <platform/irqs.h> |
| 46 | #include <platform/clock.h> |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 47 | #include <platform/timer.h> |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 48 | #include <crypto5_wrapper.h> |
| 49 | #include <partition_parser.h> |
| 50 | #include <stdlib.h> |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 51 | #include <rpm-smd.h> |
| 52 | #include <spmi.h> |
| 53 | #include <sdhci_msm.h> |
| 54 | #include <clock.h> |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 55 | #include <boot_device.h> |
| 56 | #include <secapp_loader.h> |
| 57 | #include <rpmb.h> |
| 58 | #include <smem.h> |
| 59 | #include <qmp_phy.h> |
| 60 | #include <qusb2_phy.h> |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 61 | |
| 62 | #if LONG_PRESS_POWER_ON |
| 63 | #include <shutdown_detect.h> |
| 64 | #endif |
| 65 | |
c_wufeng | 41310ae | 2016-01-14 17:59:22 +0800 | [diff] [blame^] | 66 | #if PON_VIB_SUPPORT |
| 67 | #include <vibrator.h> |
| 68 | #define VIBRATE_TIME 250 |
| 69 | #endif |
| 70 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 71 | #define PMIC_ARB_CHANNEL_NUM 0 |
| 72 | #define PMIC_ARB_OWNER_ID 0 |
| 73 | #define TLMM_VOL_UP_BTN_GPIO 85 |
| 74 | |
| 75 | #define FASTBOOT_MODE 0x77665500 |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 76 | #define RECOVERY_MODE 0x77665502 |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 77 | #define PON_SOFT_RB_SPARE 0x88F |
| 78 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 79 | #define CE1_INSTANCE 1 |
| 80 | #define CE_EE 1 |
| 81 | #define CE_FIFO_SIZE 64 |
| 82 | #define CE_READ_PIPE 3 |
| 83 | #define CE_WRITE_PIPE 2 |
| 84 | #define CE_READ_PIPE_LOCK_GRP 0 |
| 85 | #define CE_WRITE_PIPE_LOCK_GRP 0 |
| 86 | #define CE_ARRAY_SIZE 20 |
| 87 | |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 88 | struct mmc_device *dev; |
| 89 | |
| 90 | static uint32_t mmc_pwrctl_base[] = |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 91 | { MSM_SDC1_BASE, MSM_SDC2_BASE }; |
| 92 | |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 93 | static uint32_t mmc_sdhci_base[] = |
| 94 | { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE }; |
| 95 | |
| 96 | static uint32_t mmc_sdc_pwrctl_irq[] = |
| 97 | { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ }; |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 98 | |
| 99 | void target_early_init(void) |
| 100 | { |
| 101 | #if WITH_DEBUG_UART |
P.V. Phani Kumar | 2e4eeae | 2015-12-31 16:52:54 +0530 | [diff] [blame] | 102 | uart_dm_init(1, 0, BLSP1_UART0_BASE); |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 103 | #endif |
| 104 | } |
| 105 | |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 106 | static void set_sdc_power_ctrl() |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 107 | { |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 108 | /* Drive strength configs for sdc pins */ |
| 109 | struct tlmm_cfgs sdc1_hdrv_cfg[] = |
| 110 | { |
| 111 | { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK, 0}, |
| 112 | { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK, 0}, |
| 113 | { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK , 0}, |
| 114 | }; |
| 115 | |
| 116 | /* Pull configs for sdc pins */ |
| 117 | struct tlmm_cfgs sdc1_pull_cfg[] = |
| 118 | { |
| 119 | { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK, 0}, |
| 120 | { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0}, |
| 121 | { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK, 0}, |
| 122 | }; |
| 123 | |
| 124 | struct tlmm_cfgs sdc1_rclk_cfg[] = |
| 125 | { |
| 126 | { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK, 0}, |
| 127 | }; |
| 128 | |
| 129 | /* Set the drive strength & pull control values */ |
| 130 | tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg)); |
| 131 | tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg)); |
| 132 | tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg)); |
| 133 | } |
| 134 | |
| 135 | void target_sdc_init() |
| 136 | { |
| 137 | struct mmc_config_data config; |
| 138 | |
| 139 | /* Set drive strength & pull ctrl values */ |
| 140 | set_sdc_power_ctrl(); |
| 141 | |
| 142 | config.slot = MMC_SLOT; |
| 143 | config.bus_width = DATA_BUS_WIDTH_8BIT; |
| 144 | config.max_clk_rate = MMC_CLK_192MHZ; |
| 145 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 146 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 147 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 148 | config.hs400_support = 1; |
| 149 | |
| 150 | if (!(dev = mmc_init(&config))) { |
| 151 | /* Try different config. values */ |
| 152 | config.max_clk_rate = MMC_CLK_200MHZ; |
| 153 | config.sdhc_base = mmc_sdhci_base[config.slot - 1]; |
| 154 | config.pwrctl_base = mmc_pwrctl_base[config.slot - 1]; |
| 155 | config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1]; |
| 156 | config.hs400_support = 0; |
| 157 | |
| 158 | if (!(dev = mmc_init(&config))) { |
| 159 | dprintf(CRITICAL, "mmc init failed!"); |
| 160 | ASSERT(0); |
| 161 | } |
| 162 | } |
| 163 | } |
| 164 | |
| 165 | void *target_mmc_device() |
| 166 | { |
| 167 | return (void *) dev; |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | /* Return 1 if vol_up pressed */ |
| 171 | static int target_volume_up() |
| 172 | { |
| 173 | uint8_t status = 0; |
| 174 | |
| 175 | gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE); |
| 176 | |
| 177 | /* Wait for the gpio config to take effect - debounce time */ |
| 178 | thread_sleep(10); |
| 179 | |
| 180 | /* Get status of GPIO */ |
| 181 | status = gpio_status(TLMM_VOL_UP_BTN_GPIO); |
| 182 | |
| 183 | /* Active high signal. */ |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 184 | return !status; |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | /* Return 1 if vol_down pressed */ |
| 188 | uint32_t target_volume_down() |
| 189 | { |
| 190 | /* Volume down button tied in with PMIC RESIN. */ |
| 191 | return pm8x41_resin_status(); |
| 192 | } |
| 193 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 194 | uint32_t target_is_pwrkey_pon_reason() |
| 195 | { |
| 196 | uint8_t pon_reason = pm8950_get_pon_reason(); |
| 197 | if (pm8x41_get_is_cold_boot() && ((pon_reason == KPDPWR_N) || (pon_reason == (KPDPWR_N|PON1)))) |
| 198 | return 1; |
| 199 | else |
| 200 | return 0; |
| 201 | } |
| 202 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 203 | static void target_keystatus() |
| 204 | { |
| 205 | keys_init(); |
| 206 | |
| 207 | if(target_volume_down()) |
| 208 | keys_post_event(KEY_VOLUMEDOWN, 1); |
| 209 | |
| 210 | if(target_volume_up()) |
| 211 | keys_post_event(KEY_VOLUMEUP, 1); |
| 212 | } |
| 213 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 214 | void target_init(void) |
| 215 | { |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 216 | #if VERIFIED_BOOT |
| 217 | #if !VBOOT_MOTA |
| 218 | int ret = 0; |
| 219 | #endif |
| 220 | #endif |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 221 | dprintf(INFO, "target_init()\n"); |
| 222 | |
| 223 | spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID); |
| 224 | |
| 225 | target_keystatus(); |
| 226 | |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 227 | target_sdc_init(); |
| 228 | if (partition_read_table()) |
| 229 | { |
| 230 | dprintf(CRITICAL, "Error reading the partition table info\n"); |
| 231 | ASSERT(0); |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 232 | } |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 233 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 234 | #if LONG_PRESS_POWER_ON |
| 235 | shutdown_detect(); |
| 236 | #endif |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 237 | |
c_wufeng | 41310ae | 2016-01-14 17:59:22 +0800 | [diff] [blame^] | 238 | #if PON_VIB_SUPPORT |
| 239 | vib_timed_turn_on(VIBRATE_TIME); |
| 240 | #endif |
| 241 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 242 | |
| 243 | if (target_use_signed_kernel()) |
| 244 | target_crypto_init_params(); |
| 245 | |
| 246 | #if VERIFIED_BOOT |
| 247 | #if !VBOOT_MOTA |
| 248 | clock_ce_enable(CE1_INSTANCE); |
| 249 | |
| 250 | /* Initialize Qseecom */ |
| 251 | ret = qseecom_init(); |
| 252 | |
| 253 | if (ret < 0) |
| 254 | { |
| 255 | dprintf(CRITICAL, "Failed to initialize qseecom, error: %d\n", ret); |
| 256 | ASSERT(0); |
| 257 | } |
| 258 | |
| 259 | /* Start Qseecom */ |
| 260 | ret = qseecom_tz_init(); |
| 261 | |
| 262 | if (ret < 0) |
| 263 | { |
| 264 | dprintf(CRITICAL, "Failed to start qseecom, error: %d\n", ret); |
| 265 | ASSERT(0); |
| 266 | } |
| 267 | |
| 268 | if (rpmb_init() < 0) |
| 269 | { |
| 270 | dprintf(CRITICAL, "RPMB init failed\n"); |
| 271 | ASSERT(0); |
| 272 | } |
| 273 | |
| 274 | /* |
| 275 | * Load the sec app for first time |
| 276 | */ |
| 277 | if (load_sec_app() < 0) |
| 278 | { |
| 279 | dprintf(CRITICAL, "Failed to load App for verified\n"); |
| 280 | ASSERT(0); |
| 281 | } |
| 282 | #endif |
| 283 | #endif |
| 284 | |
| 285 | #if SMD_SUPPORT |
| 286 | rpm_smd_init(); |
| 287 | #endif |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | void target_serialno(unsigned char *buf) |
| 291 | { |
| 292 | uint32_t serialno; |
| 293 | if (target_is_emmc_boot()) { |
| 294 | serialno = mmc_get_psn(); |
| 295 | snprintf((char *)buf, 13, "%x", serialno); |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | unsigned board_machtype(void) |
| 300 | { |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 301 | return LINUX_MACHTYPE_UNKNOWN; |
| 302 | } |
| 303 | |
| 304 | /* Detect the target type */ |
| 305 | void target_detect(struct board_data *board) |
| 306 | { |
| 307 | /* This is already filled as part of board.c */ |
| 308 | } |
| 309 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 310 | /* Detect the modem type */ |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 311 | void target_baseband_detect(struct board_data *board) |
| 312 | { |
| 313 | uint32_t platform; |
| 314 | |
| 315 | platform = board->platform; |
| 316 | |
| 317 | switch(platform) { |
| 318 | case MSMTITANIUM: |
| 319 | board->baseband = BASEBAND_MSM; |
| 320 | break; |
Gaurav Nebhwani | 22a0d9f | 2015-12-29 13:49:26 +0530 | [diff] [blame] | 321 | case APQTITANIUM: |
| 322 | board->baseband = BASEBAND_APQ; |
| 323 | break; |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 324 | default: |
| 325 | dprintf(CRITICAL, "Platform type: %u is not supported\n",platform); |
| 326 | ASSERT(0); |
| 327 | }; |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 328 | } |
| 329 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 330 | unsigned target_baseband() |
| 331 | { |
| 332 | return board_baseband(); |
| 333 | } |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 334 | int set_download_mode(enum dload_mode mode) |
| 335 | { |
| 336 | int ret = 0; |
| 337 | ret = scm_dload_mode(mode); |
| 338 | |
| 339 | pm8x41_clear_pmic_watchdog(); |
| 340 | |
| 341 | return ret; |
| 342 | } |
| 343 | |
| 344 | int emmc_recovery_init(void) |
| 345 | { |
| 346 | return _emmc_recovery_init(); |
| 347 | } |
| 348 | |
| 349 | unsigned target_pause_for_battery_charge(void) |
| 350 | { |
| 351 | uint8_t pon_reason = pm8x41_get_pon_reason(); |
| 352 | uint8_t is_cold_boot = pm8x41_get_is_cold_boot(); |
| 353 | dprintf(INFO, "%s : pon_reason is %d cold_boot:%d\n", __func__, |
| 354 | pon_reason, is_cold_boot); |
| 355 | /* In case of fastboot reboot,adb reboot or if we see the power key |
| 356 | * pressed we do not want go into charger mode. |
| 357 | * fastboot reboot is warm boot with PON hard reset bit not set |
| 358 | * adb reboot is a cold boot with PON hard reset bit set |
| 359 | */ |
| 360 | if (is_cold_boot && |
| 361 | (!(pon_reason & HARD_RST)) && |
| 362 | (!(pon_reason & KPDPWR_N)) && |
| 363 | ((pon_reason & USB_CHG) || (pon_reason & DC_CHG) || (pon_reason & CBLPWR_N))) |
| 364 | return 1; |
| 365 | else |
| 366 | return 0; |
| 367 | } |
| 368 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 369 | void target_uninit(void) |
| 370 | { |
| 371 | mmc_put_card_to_sleep(dev); |
| 372 | sdhci_mode_disable(&dev->host); |
| 373 | if (crypto_initialized()) |
| 374 | crypto_eng_cleanup(); |
| 375 | |
| 376 | if (target_is_ssd_enabled()) |
| 377 | clock_ce_disable(CE1_INSTANCE); |
| 378 | |
| 379 | #if VERIFIED_BOOT |
| 380 | #if !VBOOT_MOTA |
| 381 | if (is_sec_app_loaded()) |
| 382 | { |
| 383 | if (send_milestone_call_to_tz() < 0) |
| 384 | { |
| 385 | dprintf(CRITICAL, "Failed to unload App for rpmb\n"); |
| 386 | ASSERT(0); |
| 387 | } |
| 388 | } |
| 389 | |
| 390 | if (rpmb_uninit() < 0) |
| 391 | { |
| 392 | dprintf(CRITICAL, "RPMB uninit failed\n"); |
| 393 | ASSERT(0); |
| 394 | } |
| 395 | |
| 396 | clock_ce_disable(CE1_INSTANCE); |
| 397 | #endif |
| 398 | #endif |
| 399 | |
| 400 | #if SMD_SUPPORT |
| 401 | rpm_smd_uninit(); |
| 402 | #endif |
| 403 | } |
| 404 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 405 | /* UTMI MUX configuration to connect PHY to SNPS controller: |
| 406 | * Configure primary HS phy mux to use UTMI interface |
| 407 | * (connected to usb30 controller). |
| 408 | */ |
| 409 | static void tcsr_hs_phy_mux_configure(void) |
| 410 | { |
| 411 | uint32_t reg; |
| 412 | |
| 413 | reg = readl(USB2_PHY_SEL); |
| 414 | |
| 415 | writel(reg | 0x1, USB2_PHY_SEL); |
| 416 | } |
| 417 | |
| 418 | /* configure hs phy mux if using dwc controller */ |
| 419 | void target_usb_phy_mux_configure(void) |
| 420 | { |
| 421 | if(!strcmp(target_usb_controller(), "dwc")) |
| 422 | { |
| 423 | tcsr_hs_phy_mux_configure(); |
| 424 | } |
| 425 | } |
| 426 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 427 | void target_usb_phy_reset() |
| 428 | { |
| 429 | |
| 430 | usb30_qmp_phy_reset(); |
| 431 | qusb2_phy_reset(); |
| 432 | } |
| 433 | |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 434 | /* Initialize target specific USB handlers */ |
| 435 | target_usb_iface_t* target_usb30_init() |
| 436 | { |
| 437 | target_usb_iface_t *t_usb_iface; |
| 438 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 439 | t_usb_iface = (target_usb_iface_t *) calloc(1, sizeof(target_usb_iface_t)); |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 440 | ASSERT(t_usb_iface); |
| 441 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 442 | t_usb_iface->mux_config = NULL; |
| 443 | t_usb_iface->phy_init = usb30_qmp_phy_init; |
| 444 | t_usb_iface->phy_reset = target_usb_phy_reset; |
| 445 | t_usb_iface->clock_init = clock_usb30_init; |
| 446 | t_usb_iface->vbus_override = 1; |
Aparna Mallavarapu | 01fc00a | 2015-06-01 20:37:05 +0530 | [diff] [blame] | 447 | |
| 448 | return t_usb_iface; |
| 449 | } |
| 450 | |
| 451 | /* identify the usb controller to be used for the target */ |
| 452 | const char * target_usb_controller() |
| 453 | { |
| 454 | return "dwc"; |
| 455 | } |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 456 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 457 | /* Do any target specific intialization needed before entering fastboot mode */ |
| 458 | void target_fastboot_init(void) |
| 459 | { |
| 460 | if (target_is_ssd_enabled()) { |
| 461 | clock_ce_enable(CE1_INSTANCE); |
| 462 | target_load_ssd_keystore(); |
| 463 | } |
| 464 | } |
| 465 | |
| 466 | void target_load_ssd_keystore(void) |
| 467 | { |
| 468 | uint64_t ptn; |
| 469 | int index; |
| 470 | uint64_t size; |
| 471 | uint32_t *buffer = NULL; |
| 472 | |
| 473 | if (!target_is_ssd_enabled()) |
| 474 | return; |
| 475 | |
| 476 | index = partition_get_index("ssd"); |
| 477 | |
| 478 | ptn = partition_get_offset(index); |
| 479 | if (ptn == 0){ |
| 480 | dprintf(CRITICAL, "Error: ssd partition not found\n"); |
| 481 | return; |
| 482 | } |
| 483 | |
| 484 | size = partition_get_size(index); |
| 485 | if (size == 0) { |
| 486 | dprintf(CRITICAL, "Error: invalid ssd partition size\n"); |
| 487 | return; |
| 488 | } |
| 489 | |
| 490 | buffer = memalign(CACHE_LINE, ROUNDUP(size, CACHE_LINE)); |
| 491 | if (!buffer) { |
| 492 | dprintf(CRITICAL, "Error: allocating memory for ssd buffer\n"); |
| 493 | return; |
| 494 | } |
| 495 | |
| 496 | if (mmc_read(ptn, buffer, size)) { |
| 497 | dprintf(CRITICAL, "Error: cannot read data\n"); |
| 498 | free(buffer); |
| 499 | return; |
| 500 | } |
| 501 | |
| 502 | clock_ce_enable(CE1_INSTANCE); |
| 503 | scm_protect_keystore(buffer, size); |
| 504 | clock_ce_disable(CE1_INSTANCE); |
| 505 | free(buffer); |
| 506 | } |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 507 | |
| 508 | crypto_engine_type board_ce_type(void) |
| 509 | { |
| 510 | return CRYPTO_ENGINE_TYPE_HW; |
| 511 | } |
| 512 | |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 513 | /* Set up params for h/w CE. */ |
| 514 | void target_crypto_init_params() |
| 515 | { |
| 516 | struct crypto_init_params ce_params; |
| 517 | |
| 518 | /* Set up base addresses and instance. */ |
| 519 | ce_params.crypto_instance = CE1_INSTANCE; |
| 520 | ce_params.crypto_base = MSM_CE1_BASE; |
| 521 | ce_params.bam_base = MSM_CE1_BAM_BASE; |
| 522 | |
| 523 | /* Set up BAM config. */ |
| 524 | ce_params.bam_ee = CE_EE; |
| 525 | ce_params.pipes.read_pipe = CE_READ_PIPE; |
| 526 | ce_params.pipes.write_pipe = CE_WRITE_PIPE; |
| 527 | ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP; |
| 528 | ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP; |
| 529 | |
| 530 | /* Assign buffer sizes. */ |
| 531 | ce_params.num_ce = CE_ARRAY_SIZE; |
| 532 | ce_params.read_fifo_size = CE_FIFO_SIZE; |
| 533 | ce_params.write_fifo_size = CE_FIFO_SIZE; |
| 534 | |
| 535 | /* BAM is initialized by TZ for this platform. |
| 536 | * Do not do it again as the initialization address space |
| 537 | * is locked. |
| 538 | */ |
| 539 | ce_params.do_bam_init = 0; |
| 540 | |
| 541 | crypto_init_params(&ce_params); |
| 542 | } |
P.V. Phani Kumar | a053a32 | 2015-08-13 18:36:05 +0530 | [diff] [blame] | 543 | |
| 544 | void pmic_reset_configure(uint8_t reset_type) |
| 545 | { |
| 546 | pm8x41_reset_configure(reset_type); |
| 547 | } |
P.V. Phani Kumar | 77826d3 | 2015-12-26 20:56:35 +0530 | [diff] [blame] | 548 | |
| 549 | uint32_t target_get_pmic() |
| 550 | { |
| 551 | return PMIC_IS_PMI8950; |
| 552 | } |
| 553 | |
| 554 | struct qmp_reg qmp_settings[] = |
| 555 | { |
| 556 | {0x804, 0x01}, /*USB3PHY_PCIE_USB3_PCS_POWER_DOWN_CONTROL */ |
| 557 | {0xAC, 0x14}, /* QSERDES_COM_SYSCLK_EN_SEL */ |
| 558 | {0x34, 0x08}, /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */ |
| 559 | {0x174, 0x30}, /* QSERDES_COM_CLK_SELECT */ |
| 560 | {0x3C, 0x06}, /* QSERDES_COM_SYS_CLK_CTRL */ |
| 561 | {0xB4, 0x00}, /* QSERDES_COM_RESETSM_CNTRL */ |
| 562 | {0xB8, 0x08}, /* QSERDES_COM_RESETSM_CNTRL2 */ |
| 563 | {0x194, 0x06}, /* QSERDES_COM_CMN_CONFIG */ |
| 564 | {0x19c, 0x01}, /* QSERDES_COM_SVS_MODE_CLK_SEL */ |
| 565 | {0x178, 0x00}, /* QSERDES_COM_HSCLK_SEL */ |
| 566 | {0xd0, 0x82}, /* QSERDES_COM_DEC_START_MODE0 */ |
| 567 | {0xdc, 0x55}, /* QSERDES_COM_DIV_FRAC_START1_MODE0 */ |
| 568 | {0xe0, 0x55}, /* QSERDES_COM_DIV_FRAC_START2_MODE0 */ |
| 569 | {0xe4, 0x03}, /* QSERDES_COM_DIV_FRAC_START3_MODE0 */ |
| 570 | {0x78, 0x0b}, /* QSERDES_COM_CP_CTRL_MODE0 */ |
| 571 | {0x84, 0x16}, /* QSERDES_COM_PLL_RCTRL_MODE0 */ |
| 572 | {0x90, 0x28}, /* QSERDES_COM_PLL_CCTRL_MODE0 */ |
| 573 | {0x108, 0x80}, /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */ |
| 574 | {0x10C, 0x00}, /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */ |
| 575 | {0x184, 0x0A}, /* QSERDES_COM_CORECLK_DIV */ |
| 576 | {0x4c, 0x15}, /* QSERDES_COM_LOCK_CMP1_MODE0 */ |
| 577 | {0x50, 0x34}, /* QSERDES_COM_LOCK_CMP2_MODE0 */ |
| 578 | {0x54, 0x00}, /* QSERDES_COM_LOCK_CMP3_MODE0 */ |
| 579 | {0xC8, 0x00}, /* QSERDES_COM_LOCK_CMP_EN */ |
| 580 | {0x18c, 0x00}, /* QSERDES_COM_CORE_CLK_EN */ |
| 581 | {0xcc, 0x00}, /* QSERDES_COM_LOCK_CMP_CFG */ |
| 582 | {0x128, 0x00}, /* QSERDES_COM_VCO_TUNE_MAP */ |
| 583 | {0x0C, 0x0A}, /* QSERDES_COM_BG_TIMER */ |
| 584 | {0x10, 0x01}, /* QSERDES_COM_SSC_EN_CENTER */ |
| 585 | {0x1c, 0x31}, /* QSERDES_COM_SSC_PER1 */ |
| 586 | {0x20, 0x01}, /* QSERDES_COM_SSC_PER2 */ |
| 587 | {0x14, 0x00}, /* QSERDES_COM_SSC_ADJ_PER1 */ |
| 588 | {0x18, 0x00}, /* QSERDES_COM_SSC_ADJ_PER2 */ |
| 589 | {0x24, 0xde}, /* QSERDES_COM_SSC_STEP_SIZE1 */ |
| 590 | {0x28, 0x07}, /* QSERDES_COM_SSC_STEP_SIZE2 */ |
| 591 | {0x48, 0x0F}, /* USB3PHY_QSERDES_COM_PLL_IVCO */ |
| 592 | {0x70, 0x0F}, /* USB3PHY_QSERDES_COM_BG_TRIM */ |
| 593 | {0x100, 0x80}, /* QSERDES_COM_INTEGLOOP_INITVAL */ |
| 594 | |
| 595 | /* Rx Settings */ |
| 596 | {0x440, 0x0b}, /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */ |
| 597 | {0x4d8, 0x02}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */ |
| 598 | {0x4dc, 0x6c}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */ |
| 599 | {0x4e0, 0xbb}, /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */ |
| 600 | {0x508, 0x77}, /* QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */ |
| 601 | {0x50c, 0x80}, /* QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 */ |
| 602 | {0x514, 0x03}, /* QSERDES_RX_SIGDET_CNTRL */ |
| 603 | {0x51c, 0x16}, /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */ |
| 604 | {0x448, 0x75}, /* QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE */ |
| 605 | {0x450, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW */ |
| 606 | {0x454, 0x00}, /* QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH */ |
| 607 | {0x40C, 0x0a}, /* QSERDES_RX_UCDR_FO_GAIN */ |
| 608 | {0x41C, 0x06}, /* QSERDES_RX_UCDR_SO_GAIN */ |
| 609 | {0x510, 0x00}, /*QSERDES_RX_SIGDET_ENABLES */ |
| 610 | |
| 611 | /* Tx settings */ |
| 612 | {0x268, 0x45}, /* QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN */ |
| 613 | {0x2ac, 0x12}, /* QSERDES_TX_RCV_DETECT_LVL_2 */ |
| 614 | {0x294, 0x06}, /* QSERDES_TX_LANE_MODE */ |
| 615 | {0x254, 0x00}, /* QSERDES_TX_RES_CODE_LANE_OFFSET */ |
| 616 | |
| 617 | /* FLL settings */ |
| 618 | {0x8c8, 0x83}, /* PCIE_USB3_PCS_FLL_CNTRL2 */ |
| 619 | {0x8c4, 0x02}, /* PCIE_USB3_PCS_FLL_CNTRL1 */ |
| 620 | {0x8cc, 0x09}, /* PCIE_USB3_PCS_FLL_CNT_VAL_L */ |
| 621 | {0x8D0, 0xA2}, /* PCIE_USB3_PCS_FLL_CNT_VAL_H_TOL */ |
| 622 | {0x8D4, 0x85}, /* PCIE_USB3_PCS_FLL_MAN_CODE */ |
| 623 | |
| 624 | /* PCS Settings */ |
| 625 | {0x880, 0xD1}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG1 */ |
| 626 | {0x884, 0x1F}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG2 */ |
| 627 | {0x888, 0x47}, /* PCIE_USB3_PCS_LOCK_DETECT_CONFIG3 */ |
| 628 | {0x80C, 0x9F}, /* PCIE_USB3_PCS_TXMGN_V0 */ |
| 629 | {0x824, 0x17}, /* PCIE_USB3_PCS_TXDEEMPH_M6DB_V0 */ |
| 630 | {0x828, 0x0F}, /* PCIE_USB3_PCS_TXDEEMPH_M3P5DB_V0 */ |
| 631 | {0x8B8, 0x75}, /* PCIE_USB3_PCS_RXEQTRAINING_WAIT_TIME */ |
| 632 | {0x8BC, 0x13}, /* PCIE_USB3_PCS_RXEQTRAINING_RUN_TIME */ |
| 633 | {0x8B0, 0x86}, /* PCIE_USB3_PCS_LFPS_TX_ECSTART_EQTLOCK */ |
| 634 | {0x8A0, 0x04}, /* PCIE_USB3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK */ |
| 635 | {0x88C, 0x44}, /* PCIE_USB3_PCS_TSYNC_RSYNC_TIME */ |
| 636 | {0x870, 0xE7}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_L */ |
| 637 | {0x874, 0x03}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_P1U2_H */ |
| 638 | {0x878, 0x40}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_L */ |
| 639 | {0x87c, 0x00}, /* PCIE_USB3_PCS_RCVR_DTCT_DLY_U3_H */ |
| 640 | {0x9D8, 0x88}, /* PCIE_USB3_PCS_RX_SIGDET_LVL */ |
| 641 | {0x808, 0x03}, /* PCIE_USB3_PCS_START_CONTROL */ |
| 642 | {0x800, 0x00}, /* PCIE_USB3_PCS_SW_RESET */ |
| 643 | }; |
| 644 | |
| 645 | struct qmp_reg *target_get_qmp_settings() |
| 646 | { |
| 647 | return qmp_settings; |
| 648 | } |
| 649 | |
| 650 | int target_get_qmp_regsize() |
| 651 | { |
| 652 | return ARRAY_SIZE(qmp_settings); |
| 653 | } |