Shashank Mittal | 52525ff | 2010-04-13 11:11:10 -0700 | [diff] [blame^] | 1 | /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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| 2 |
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| 3 | * Redistribution and use in source and binary forms, with or without
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| 4 | * modification, are permitted provided that the following conditions are
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| 5 | * met:
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| 6 | * * Redistributions of source code must retain the above copyright
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| 7 | * notice, this list of conditions and the following disclaimer.
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| 8 | * * Redistributions in binary form must reproduce the above
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| 9 | * copyright notice, this list of conditions and the following
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| 10 | * disclaimer in the documentation and/or other materials provided
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| 11 | * with the distribution.
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| 12 | * * Neither the name of Code Aurora Forum, Inc. nor the names of its
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| 13 | * contributors may be used to endorse or promote products derived
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| 14 | * from this software without specific prior written permission.
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| 15 | *
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| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 27 | */
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| 28 |
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| 29 | #ifndef __MMC_H__
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| 30 | #define __MMC_H__
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| 31 |
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| 32 | #ifndef MMC_BOOT_MCI_BASE
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| 33 | #define MMC_BOOT_MCI_BASE 0
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| 34 | #endif
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| 35 |
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| 36 | #ifndef MMC_SLOT
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| 37 | #define MMC_SLOT 0
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| 38 | #endif
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| 39 |
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| 40 | #define MMC_BOOT_MCI_REG(offset) (MMC_BOOT_MCI_BASE + offset)
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| 41 |
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| 42 | /*
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| 43 | * Define Macros for SDCC Registers
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| 44 | */
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| 45 | #define MMC_BOOT_MCI_POWER MMC_BOOT_MCI_REG(0x000) /* 8 bit */
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| 46 |
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| 47 | /* MCICMD output control - 6th bit */
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| 48 | #ifdef PLATFORM_MSM7X30
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| 49 | #define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
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| 50 | #define MMC_BOOT_MCI_PWR_OFF 0x00
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| 51 | #define MMC_BOOT_MCI_PWR_UP 0x01
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| 52 | #define MMC_BOOT_MCI_PWR_ON 0x01
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| 53 | #else
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| 54 | #define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6)
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| 55 | #define MMC_BOOT_MCI_PWR_OFF 0x00
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| 56 | #define MMC_BOOT_MCI_PWR_UP 0x02
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| 57 | #define MMC_BOOT_MCI_PWR_ON 0x03
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| 58 | #endif
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| 59 |
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| 60 | #define MMC_BOOT_MCI_CLK MMC_BOOT_MCI_REG(0x004) /* 16 bits */
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| 61 | /* Enable MCI bus clock - 0: clock disabled 1: enabled */
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| 62 | #define MMC_BOOT_MCI_CLK_ENABLE (1 << 8)
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| 63 | /* Disable clk o/p when bus idle- 0:always enabled 1:enabled when bus active */
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| 64 | #define MMC_BOOT_MCI_CLK_PWRSAVE (1 << 9)
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| 65 | /* Enable Widebus mode - 00: 1 bit mode 10:4 bit mode 01/11: 8 bit mode */
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| 66 | #define MMC_BOOT_MCI_CLK_WIDEBUS_MODE (3 << 10)
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| 67 | #define MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT 0
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| 68 | #define MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT (2 << 10)
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| 69 | #define MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT (1 << 10)
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| 70 | /* Enable flow control- 0: disable 1: enable */
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| 71 | #define MMC_BOOT_MCI_CLK_ENA_FLOW (1 << 12)
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| 72 | /* Set/clear to select rising/falling edge for data/cmd output */
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| 73 | #define MMC_BOOT_MCI_CLK_INVERT_OUT (1 << 13)
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| 74 | /* Select to lach data/cmd coming in falling/rising/feedbk/loopbk of MCIclk */
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| 75 | #define MMC_BOOT_MCI_CLK_IN_FALLING 0x0
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| 76 | #define MMC_BOOT_MCI_CLK_IN_RISING (1 << 14)
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| 77 | #define MMC_BOOT_MCI_CLK_IN_FEEDBACK (2 << 14)
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| 78 | #define MMC_BOOT_MCI_CLK_IN_LOOPBACK (3 << 14)
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| 79 |
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| 80 | /* Bus Width */
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| 81 | #define MMC_BOOT_BUS_WIDTH_1_BIT 0
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| 82 | #define MMC_BOOT_BUS_WIDTH_4_BIT 2
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| 83 | #define MMC_BOOT_BUS_WIDTH_8_BIT 3
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| 84 |
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| 85 | #define MMC_BOOT_MCI_ARGUMENT MMC_BOOT_MCI_REG(0x008) /* 32 bits */
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| 86 |
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| 87 | #define MMC_BOOT_MCI_CMD MMC_BOOT_MCI_REG(0x00C) /* 16 bits */
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| 88 | /* Command Index: 0 -5 */
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| 89 | /* Waits for response if set */
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| 90 | #define MMC_BOOT_MCI_CMD_RESPONSE (1 << 6)
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| 91 | /* Receives a 136-bit long response if set */
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| 92 | #define MMC_BOOT_MCI_CMD_LONGRSP (1 << 7)
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| 93 | /* If set, CPSM disables command timer and waits for interrupt */
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| 94 | #define MMC_BOOT_MCI_CMD_INTERRUPT (1 << 8)
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| 95 | /* If set waits for CmdPend before starting to send a command */
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| 96 | #define MMC_BOOT_MCI_CMD_PENDING (1 << 9)
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| 97 | /* CPSM is enabled if set */
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| 98 | #define MMC_BOT_MCI_CMD_ENABLE (1 << 10)
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| 99 | /* If set PROG_DONE status bit asserted when busy is de-asserted */
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| 100 | #define MMC_BOOT_MCI_CMD_PROG_ENA (1 << 11)
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| 101 | /* To indicate that this is a Command with Data (for SDIO interrupts) */
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| 102 | #define MMC_BOOT_MCI_CMD_DAT_CMD (1 << 12)
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| 103 | /* Signals the next command to be an abort (stop) command. Always read 0 */
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| 104 | #define MMC_BOOT_MCI_CMD_MCIABORT (1 << 13)
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| 105 | /* Waits for Command Completion Signal if set */
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| 106 | #define MMC_BOOT_MCI_CMD_CCS_ENABLE (1 << 14)
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| 107 | /* If set sends CCS disable sequence */
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| 108 | #define MMC_BOOT_MCI_CMD_CCS_DISABLE (1 << 15)
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| 109 |
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| 110 | #define MMC_BOOT_MCI_RESP_CMD MMC_BOOT_MCI_REG(0x010)
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| 111 |
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| 112 | #define MMC_BOOT_MCI_RESP_0 MMC_BOOT_MCI_REG(0x014)
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| 113 | #define MMC_BOOT_MCI_RESP_1 MMC_BOOT_MCI_REG(0x018)
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| 114 | #define MMC_BOOT_MCI_RESP_2 MMC_BOOT_MCI_REG(0x01C)
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| 115 | #define MMC_BOOT_MCI_RESP_3 MMC_BOOT_MCI_REG(0x020)
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| 116 |
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| 117 | #define MMC_BOOT_MCI_DATA_TIMER MMC_BOOT_MCI_REG(0x024)
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| 118 | #define MMC_BOOT_MCI_DATA_LENGTH MMC_BOOT_MCI_REG(0x028)
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| 119 | #define MMC_BOOT_MCI_DATA_CTL MMC_BOOT_MCI_REG(0x02C) /* 16 bits */
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| 120 | /* Data transfer enabled */
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| 121 | #define MMC_BOOT_MCI_DATA_ENABLE (1 << 0)
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| 122 | /* Data transfer direction - 0: controller to card 1:card to controller */
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| 123 | #define MMC_BOOT_MCI_DATA_DIR (1 << 1)
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| 124 | /* Data transfer mode - 0: block data transfer 1: stream data transfer */
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| 125 | #define MMC_BOOT_MCI_DATA_MODE (1 << 2)
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| 126 | /* Enable DM interface - 0: DM disabled 1: DM enabled */
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| 127 | #define MMC_BOOT_MCI_DATA_DM_ENABLE (1 << 3)
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| 128 | /* Data block length in bytes (1-4096) */
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| 129 | #define MMC_BOOT_MCI_BLKSIZE_POS 4
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| 130 | #define MMC_BOOT_MCI_DATA_COUNT MMC_BOOT_MCI_REG(0x030)
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| 131 | #define MMC_BOOT_MCI_STATUS MMC_BOOT_MCI_REG(0x034)
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| 132 | /* Command response received - CRC check failed */
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| 133 | #define MMC_BOOT_MCI_STAT_CMD_CRC_FAIL (1 << 0)
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| 134 | /* Data block sent/received - CRC check failed */
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| 135 | #define MMC_BOOT_MCI_STAT_DATA_CRC_FAIL (1 << 1)
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| 136 | /* Command resonse timeout */
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| 137 | #define MMC_BOOT_MCI_STAT_CMD_TIMEOUT (1 << 2)
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| 138 | /* Data timeout */
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| 139 | #define MMC_BOOT_MCI_STAT_DATA_TIMEOUT (1 << 3)
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| 140 | /* Transmit FIFO underrun error */
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| 141 | #define MMC_BOOT_MCI_STAT_TX_UNDRUN (1 << 4)
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| 142 | /* Receive FIFO overrun error */
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| 143 | #define MMC_BOOT_MCI_STAT_RX_OVRRUN (1 << 5)
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| 144 | /* Command response received - CRC check passed */
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| 145 | #define MMC_BOOT_MCI_STAT_CMD_RESP_END (1 << 6)
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| 146 | /* Command sent - no response required */
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| 147 | #define MMC_BOOT_MCI_STAT_CMD_SENT (1 << 7)
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| 148 | /* Data end - data counter zero */
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| 149 | #define MMC_BOOT_MCI_STAT_DATA_END (1 << 8)
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| 150 | /* Start bit not detected on all data signals in wide bus mode */
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| 151 | #define MMC_BOOT_MCI_STAT_START_BIT_ERR (1 << 9)
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| 152 | /* Data block sent/received - CRC check passed */
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| 153 | #define MMC_BOOT_MCI_STAT_DATA_BLK_END (1 << 10)
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| 154 | /* Command transfer in progress */
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| 155 | #define MMC_BOOT_MCI_STAT_CMD_ACTIVE (1 << 11)
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| 156 | /* Data transmit in progress */
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| 157 | #define MMC_BOOT_MCI_STAT_TX_ACTIVE (1 << 12)
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| 158 | /* Data receive in progress */
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| 159 | #define MMC_BOOT_MCI_STAT_RX_ACTIVE (1 << 13)
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| 160 | /* Transmit FIFO half full */
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| 161 | #define MMC_BOOT_MCI_STAT_TX_FIFO_HFULL (1 << 14)
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| 162 | /* Receive FIFO half full */
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| 163 | #define MMC_BOOT_MCI_STAT_RX_FIFO_HFULL (1 << 15)
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| 164 | /* Transmit FIFO full */
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| 165 | #define MMC_BOOT_MCI_STAT_TX_FIFO_FULL (1 << 16)
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| 166 | /* Receive FIFO full */
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| 167 | #define MMC_BOOT_MCI_STAT_RX_FIFO_FULL (1 << 17)
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| 168 | /* Transmit FIFO empty */
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| 169 | #define MMC_BOOT_MCI_STAT_TX_FIFO_EMPTY (1 << 18)
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| 170 | /* Receive FIFO empty */
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| 171 | #define MMC_BOOT_MCI_STAT_RX_FIFO_EMPTY (1 << 19)
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| 172 | /* Data available in transmit FIFO */
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| 173 | #define MMC_BOOT_MCI_STAT_TX_DATA_AVLBL (1 << 20)
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| 174 | /* Data available in receive FIFO */
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| 175 | #define MMC_BOOT_MCI_STAT_RX_DATA_AVLBL (1 << 21)
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| 176 | /* SDIO interrupt indicator for wake-up */
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| 177 | #define MMC_BOOT_MCI_STAT_SDIO_INTR (1 << 22)
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| 178 | /* Programming done */
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| 179 | #define MMC_BOOT_MCI_STAT_PROG_DONE (1 << 23)
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| 180 | /* CE-ATA command completion signal detected */
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| 181 | #define MMC_BOOT_MCI_STAT_ATA_CMD_CMPL (1 << 24)
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| 182 | /* SDIO interrupt indicator for normal operation */
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| 183 | #define MMC_BOOT_MCI_STAT_SDIO_INTR_OP (1 << 25)
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| 184 | /* Commpand completion signal timeout */
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| 185 | #define MMC_BOOT_MCI_STAT_CCS_TIMEOUT (1 << 26)
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| 186 |
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| 187 | #define MMC_BOOT_MCI_STATIC_STATUS (MMC_BOOT_MCI_STAT_CMD_CRC_FAIL| \
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| 188 | MMC_BOOT_MCI_STAT_DATA_CRC_FAIL| \
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| 189 | MMC_BOOT_MCI_STAT_CMD_TIMEOUT| \
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| 190 | MMC_BOOT_MCI_STAT_DATA_TIMEOUT| \
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| 191 | MMC_BOOT_MCI_STAT_TX_UNDRUN| \
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| 192 | MMC_BOOT_MCI_STAT_RX_OVRRUN| \
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| 193 | MMC_BOOT_MCI_STAT_CMD_RESP_END| \
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| 194 | MMC_BOOT_MCI_STAT_CMD_SENT| \
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| 195 | MMC_BOOT_MCI_STAT_DATA_END| \
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| 196 | MMC_BOOT_MCI_STAT_START_BIT_ERR| \
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| 197 | MMC_BOOT_MCI_STAT_DATA_BLK_END| \
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| 198 | MMC_BOOT_MCI_SDIO_INTR_CLR| \
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| 199 | MMC_BOOT_MCI_STAT_PROG_DONE| \
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| 200 | MMC_BOOT_MCI_STAT_ATA_CMD_CMPL |\
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| 201 | MMC_BOOT_MCI_STAT_CCS_TIMEOUT)
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| 202 |
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| 203 | #define MMC_BOOT_MCI_CLEAR MMC_BOOT_MCI_REG(0x038)
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| 204 | #define MMC_BOOT_MCI_CMD_CRC_FAIL_CLR (1 << 0)
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| 205 | #define MMC_BOOT_MCI_DATA_CRC_FAIL_CLR (1 << 1)
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| 206 | #define MMC_BOOT_MCI_CMD_TIMEOUT_CLR (1 << 2)
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| 207 | #define MMC_BOOT_MCI_DATA_TIMEOUT_CLR (1 << 3)
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| 208 | #define MMC_BOOT_MCI_TX_UNDERRUN_CLR (1 << 4)
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| 209 | #define MMC_BOOT_MCI_RX_OVERRUN_CLR (1 << 5)
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| 210 | #define MMC_BOOT_MCI_CMD_RESP_END_CLR (1 << 6)
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| 211 | #define MMC_BOOT_MCI_CMD_SENT_CLR (1 << 7)
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| 212 | #define MMC_BOOT_MCI_DATA_END_CLR (1 << 8)
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| 213 | #define MMC_BOOT_MCI_START_BIT_ERR_CLR (1 << 9)
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| 214 | #define MMC_BOOT_MCI_DATA_BLK_END_CLR (1 << 10)
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| 215 | #define MMC_BOOT_MCI_SDIO_INTR_CLR (1 << 22)
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| 216 | #define MMC_BOOT_MCI_PROG_DONE_CLR (1 << 23)
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| 217 | #define MMC_BOOT_MCI_ATA_CMD_COMPLR_CLR (1 << 24)
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| 218 | #define MMC_BOOT_MCI_CCS_TIMEOUT_CLR (1 << 25)
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| 219 |
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| 220 | #define MMC_BOOT_MCI_INT_MASK0 MMC_BOOT_MCI_REG(0x03C)
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| 221 | #define MMC_BOOT_MCI_CMD_CRC_FAIL_MASK (1 << 0)
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| 222 | #define MMC_BOOT_MCI_DATA_CRC_FAIL_MASK (1 << 1)
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| 223 | #define MMC_BOOT_MCI_CMD_TIMEOUT_MASK (1 << 2)
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| 224 | #define MMC_BOOT_MCI_DATA_TIMEOUT_MASK (1 << 3)
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| 225 | #define MMC_BOOT_MCI_TX_OVERRUN_MASK (1 << 4)
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| 226 | #define MMC_BOOT_MCI_RX_OVERRUN_MASK (1 << 5)
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| 227 | #define MMC_BOOT_MCI_CMD_RESP_END_MASK (1 << 6)
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| 228 | #define MMC_BOOT_MCI_CMD_SENT_MASK (1 << 7)
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| 229 | #define MMC_BOOT_MCI_DATA_END_MASK (1 << 8)
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| 230 | #define MMC_BOOT_MCI_START_BIT_ERR_MASK (1 << 9)
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| 231 | #define MMC_BOOT_MCI_DATA_BLK_END_MASK (1 << 10)
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| 232 | #define MMC_BOOT_MCI_CMD_ACTIVE_MASK (1 << 11)
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| 233 | #define MMC_BOOT_MCI_TX_ACTIVE_MASK (1 << 12)
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| 234 | #define MMC_BOOT_MCI_RX_ACTIVE_MASK (1 << 13)
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| 235 | #define MMC_BOOT_MCI_TX_FIFO_HFULL_MASK (1 << 14)
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| 236 | #define MMC_BOOT_MCI_RX_FIFO_HFULL_MASK (1 << 15)
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| 237 | #define MMC_BOOT_MCI_TX_FIFO_FULL_MASK (1 << 16)
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| 238 | #define MMC_BOOT_MCI_RX_FIFO_FULL_MASK (1 << 17)
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| 239 | #define MMC_BOOT_MCI_TX_FIFO_EMPTY_MASK (1 << 18)
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| 240 | #define MMC_BOOT_MCI_RX_FIFO_EMPTY_MASK (1 << 19)
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| 241 | #define MMC_BOOT_MCI_TX_DATA_AVLBL_MASK (1 << 20)
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| 242 | #define MMC_BOOT_MCI_RX_DATA_AVLBL_MASK (1 << 21)
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| 243 | #define MMC_BOOT_MCI_SDIO_INT_MASK (1 << 22)
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| 244 | #define MMC_BOOT_MCI_PROG_DONE_MASK (1 << 23)
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| 245 | #define MMC_BOOT_MCI_ATA_CMD_COMPL_MASK (1 << 24)
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| 246 | #define MMC_BOOT_MCI_SDIO_INT_OPER_MASK (1 << 25)
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| 247 | #define MMC_BOOT_MCI_CCS_TIME_OUT_MASK (1 << 26)
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| 248 |
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| 249 | #define MMC_BOOT_MCI_INT_MASK1 MMC_BOOT_MCI_REG(0x040)
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| 250 |
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| 251 | #define MMC_BOOT_MCI_FIFO_COUNT MMC_BOOT_MCI_REG(0x044)
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| 252 |
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| 253 | #define MMC_BOOT_MCI_CCS_TIMER MMC_BOOT_MCI_REG(0x0058)
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| 254 |
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| 255 | #define MMC_BOOT_MCI_FIFO MMC_BOOT_MCI_REG(0x080)
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| 256 |
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| 257 | /* SD Memory Card bus commands */
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| 258 | #define CMD0_GO_IDLE_STATE 0
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| 259 | #define CMD1_SEND_OP_COND 1
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| 260 | #define CMD2_ALL_SEND_CID 2
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| 261 | #define CMD3_SEND_RELATIVE_ADDR 3
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| 262 | #define CMD4_SET_DSR 4
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| 263 | #define CMD6_SWITCH_FUNC 6
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| 264 | #define CMD7_SELECT_DESELECT_CARD 7
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| 265 | #define CMD8_SEND_EXT_CSD 8
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| 266 | #define CMD9_SEND_CSD 9
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| 267 | #define CMD10_SEND_CID 10
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| 268 | #define CMD12_STOP_TRANSMISSION 12
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| 269 | #define CMD13_SEND_STATUS 13
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| 270 | #define CMD15_GO_INACTIVE_STATUS 15
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| 271 | #define CMD16_SET_BLOCKLEN 16
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| 272 | #define CMD17_READ_SINGLE_BLOCK 17
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| 273 | #define CMD18_READ_MULTIPLE_BLOCK 18
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| 274 | #define CMD24_WRITE_SINGLE_BLOCK 24
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| 275 | #define CMD25_WRITE_MULTIPLE_BLOCK 25
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| 276 | #define CMD32_ERASE_WR_BLK_START 32
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| 277 | #define CMD33_ERASE_WR_BLK_END 33
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| 278 | #define CMD38_ERASE 38
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| 279 | #define CMD55_APP_CMD 55
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| 280 |
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| 281 | /* Switch Function Modes */
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| 282 | #define MMC_BOOT_SWITCH_FUNC_CHECK 0
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| 283 | #define MMC_BOOT_SWITCH_FUNC_SET 1
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| 284 |
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| 285 | /* OCR Register */
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| 286 | #define MMC_BOOT_OCR_17_19 (1 << 7)
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| 287 | #define MMC_BOOT_OCR_27_36 (0x1FF << 15)
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| 288 | #define MMC_BOOT_OCR_SEC_MODE (2 << 29)
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| 289 | #define MMC_BOOT_OCR_BUSY (1 << 31)
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| 290 |
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| 291 | /* Commands type */
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| 292 | #define MMC_BOOT_CMD_BCAST (1 << 0)
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| 293 | #define MMC_BOOT_CMD_BCAST_W_RESP (1 << 1)
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| 294 | #define MMC_BOOT_CMD_ADDRESS (1 << 2)
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| 295 | #define MMC_BOOT_CMD_ADDR_DATA_XFER (1 << 3)
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| 296 |
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| 297 | /* Response types */
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| 298 | #define MMC_BOOT_RESP_NONE 0
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| 299 | #define MMC_BOOT_RESP_R1 (1 << 0)
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| 300 | #define MMC_BOOT_RESP_R1B (1 << 1)
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| 301 | #define MMC_BOOT_RESP_R2 (1 << 2)
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| 302 | #define MMC_BOOT_RESP_R3 (1 << 3)
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| 303 | #define MMC_BOOT_RESP_R6 (1 << 6)
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| 304 | #define MMC_BOOT_RESP_R7 (1 << 7)
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| 305 |
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| 306 | #define IS_RESP_136_BITS(x) (x & MMC_BOOT_RESP_R2)
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| 307 | #define CHECK_FOR_BUSY_AT_RESP(x)
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| 308 |
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| 309 | /* Card Status bits (R1 register) */
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| 310 | #define MMC_BOOT_R1_AKE_SEQ_ERROR (1 << 3)
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| 311 | #define MMC_BOOT_R1_APP_CMD (1 << 5)
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| 312 | #define MMC_BOOT_R1_RDY_FOR_DATA (1 << 6)
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| 313 | #define MMC_BOOT_R1_CURR_STATE_IDLE (0 << 9)
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| 314 | #define MMC_BOOT_R1_CURR_STATE_RDY (1 << 9)
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| 315 | #define MMC_BOOT_R1_CURR_STATE_IDENT (2 << 9)
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| 316 | #define MMC_BOOT_R1_CURR_STATE_STBY (3 << 9)
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| 317 | #define MMC_BOOT_R1_CURR_STATE_TRAN (4 << 9)
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| 318 | #define MMC_BOOT_R1_CURR_STATE_DATA (5 << 9)
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| 319 | #define MMC_BOOT_R1_CURR_STATE_RCV (6 << 9)
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| 320 | #define MMC_BOOT_R1_CURR_STATE_PRG (7 << 9)
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| 321 | #define MMC_BOOT_R1_CURR_STATE_DIS (8 << 9)
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| 322 | #define MMC_BOOT_R1_ERASE_RESET (1 << 13)
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| 323 | #define MMC_BOOT_R1_CARD_ECC_DISABLED (1 << 14)
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| 324 | #define MMC_BOOT_R1_WP_ERASE_SKIP (1 << 15)
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| 325 | #define MMC_BOOT_R1_ERROR (1 << 19)
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| 326 | #define MMC_BOOT_R1_CC_ERROR (1 << 20)
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| 327 | #define MMC_BOOT_R1_CARD_ECC_FAILED (1 << 21)
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| 328 | #define MMC_BOOT_R1_ILLEGAL_CMD (1 << 22)
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| 329 | #define MMC_BOOT_R1_COM_CRC_ERR (1 << 23)
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| 330 | #define MMC_BOOT_R1_LOCK_UNLOCK_FAIL (1 << 24)
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| 331 | #define MMC_BOOT_R1_CARD_IS_LOCKED (1 << 25)
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| 332 | #define MMC_BOOT_R1_WP_VIOLATION (1 << 26)
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| 333 | #define MMC_BOOT_R1_ERASE_PARAM (1 << 27)
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| 334 | #define MMC_BOOT_R1_ERASE_SEQ_ERR (1 << 28)
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| 335 | #define MMC_BOOT_R1_BLOCK_LEN_ERR (1 << 29)
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| 336 | #define MMC_BOOT_R1_ADDR_ERR (1 << 30)
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| 337 | #define MMC_BOOT_R1_OUT_OF_RANGE (1 << 31)
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| 338 |
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| 339 | /* Macros for Common Errors */
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| 340 | #define MMC_BOOT_E_SUCCESS 0
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| 341 | #define MMC_BOOT_E_FAILURE 1
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| 342 | #define MMC_BOOT_E_TIMEOUT 2
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| 343 | #define MMC_BOOT_E_INVAL 3
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| 344 | #define MMC_BOOT_E_CRC_FAIL 4
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| 345 | #define MMC_BOOT_E_INIT_FAIL 5
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| 346 | #define MMC_BOOT_E_CMD_INDX_MISMATCH 6
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| 347 | #define MMC_BOOT_E_RESP_VERIFY_FAIL 7
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| 348 | #define MMC_BOOT_E_NOT_SUPPORTED 8
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| 349 | #define MMC_BOOT_E_CARD_BUSY 9
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| 350 | #define MMC_BOOT_E_MEM_ALLOC_FAIL 10
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| 351 | #define MMC_BOOT_E_CLK_ENABLE_FAIL 11
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| 352 | #define MMC_BOOT_E_CMMC_DECODE_FAIL 12
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| 353 | #define MMC_BOOT_E_CID_DECODE_FAIL 13
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| 354 | #define MMC_BOOT_E_BLOCKLEN_ERR 14
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| 355 | #define MMC_BOOT_E_ADDRESS_ERR 15
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| 356 | #define MMC_BOOT_E_DATA_CRC_FAIL 16
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| 357 | #define MMC_BOOT_E_DATA_TIMEOUT 17
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| 358 | #define MMC_BOOT_E_RX_OVRRUN 18
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| 359 | #define MMC_BOOT_E_VREG_SET_FAILED 19
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| 360 | #define MMC_BOOT_E_GPIO_CFG_FAIL 20
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| 361 |
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| 362 | /* EXT_CSD */
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| 363 | #define MMC_BOOT_ACCESS_WRITE 0x3
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| 364 | #define MMC_BOOT_EXT_CMMC_HS_TIMING 185
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| 365 | #define MMC_BOOT_EXT_CMMC_BUS_WIDTH 183
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| 366 |
|
| 367 | /* Data structure definitions */
|
| 368 | struct mmc_boot_command
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| 369 | {
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| 370 | unsigned int cmd_index;
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| 371 | unsigned int argument;
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| 372 | unsigned int cmd_type;
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| 373 |
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| 374 | unsigned int resp[4];
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| 375 | unsigned int resp_type;
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| 376 | unsigned int prg_enabled;
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| 377 | unsigned int xfer_mode;
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| 378 | };
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| 379 |
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| 380 | #define MMC_BOOT_XFER_MODE_BLOCK 0
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| 381 | #define MMC_BOOT_XFER_MODE_STREAM 1
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| 382 |
|
| 383 | /* CSD Register.
|
| 384 | * Note: not all the fields have been defined here
|
| 385 | */
|
| 386 | struct mmc_boot_csd
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| 387 | {
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| 388 | unsigned int cmmc_structure;
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| 389 | unsigned int card_cmd_class;
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| 390 | unsigned int write_blk_len;
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| 391 | unsigned int read_blk_len;
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| 392 | unsigned int r2w_factor;
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| 393 | unsigned int sector_size;
|
| 394 | unsigned int c_size_mult;
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| 395 | unsigned int c_size;
|
| 396 | unsigned int nsac_clk_cycle;
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| 397 | unsigned int taac_ns;
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| 398 | unsigned int tran_speed;
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| 399 | unsigned int erase_blk_len:1;
|
| 400 | unsigned int read_blk_misalign:1;
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| 401 | unsigned int write_blk_misalign:1;
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| 402 | unsigned int read_blk_partial:1;
|
| 403 | unsigned int write_blk_partial:1;
|
| 404 | };
|
| 405 |
|
| 406 | /* CID Register */
|
| 407 | struct mmc_boot_cid
|
| 408 | {
|
| 409 | unsigned int mid; /* 8 bit manufacturer id*/
|
| 410 | unsigned int oid; /* 16 bits 2 character ASCII - OEM ID*/
|
| 411 | unsigned char pnm[7];/* 6 character ASCII - product name*/
|
| 412 | unsigned int prv; /* 8 bits - product revision */
|
| 413 | unsigned int psn; /* 32 bits - product serial number */
|
| 414 | unsigned int month; /* 4 bits manufacturing month */
|
| 415 | unsigned int year; /* 4 bits manufacturing year */
|
| 416 | };
|
| 417 |
|
| 418 | /* SCR Register */
|
| 419 | struct mmc_boot_scr
|
| 420 | {
|
| 421 | unsigned int scr_structure;
|
| 422 | unsigned int mmc_spec;
|
| 423 | #define MMC_BOOT_SCR_MMC_SPEC_V1_01 0
|
| 424 | #define MMC_BOOT_SCR_MMC_SPEC_V1_10 1
|
| 425 | #define MMC_BOOT_SCR_MMC_SPEC_V2_00 2
|
| 426 | unsigned int data_stat_after_erase;
|
| 427 | unsigned int mmc_security;
|
| 428 | #define MMC_BOOT_SCR_NO_SECURITY 0
|
| 429 | #define MMC_BOOT_SCR_SECURITY_UNUSED 1
|
| 430 | #define MMC_BOOT_SCR_SECURITY_V1_01 2
|
| 431 | #define MMC_BOOT_SCR_SECURITY_V2_00 3
|
| 432 | unsigned int mmc_bus_width;
|
| 433 | #define MMC_BOOT_SCR_BUS_WIDTH_1_BIT (1<<0)
|
| 434 | #define MMC_BOOT_SCR_BUS_WIDTH_4_BIT (1<<2)
|
| 435 | };
|
| 436 |
|
| 437 | struct mmc_boot_card
|
| 438 | {
|
| 439 | unsigned int rca;
|
| 440 | unsigned int ocr;
|
| 441 | unsigned int capacity;
|
| 442 | unsigned int type;
|
| 443 | #define MMC_BOOT_TYPE_STD_SD 0
|
| 444 | #define MMC_BOOT_TYPE_SDHC 1
|
| 445 | #define MMC_BOOT_TYPE_SDIO 2
|
| 446 | unsigned int status;
|
| 447 | #define MMC_BOOT_STATUS_INACTIVE 0
|
| 448 | #define MMC_BOOT_STATUS_ACTIVE 1
|
| 449 | unsigned int rd_timeout_ns;
|
| 450 | unsigned int wr_timeout_ns;
|
| 451 | unsigned int rd_block_len;
|
| 452 | unsigned int wr_block_len;
|
| 453 | //unsigned int data_xfer_len;
|
| 454 | struct mmc_boot_cid cid;
|
| 455 | struct mmc_boot_csd csd;
|
| 456 | struct mmc_boot_scr scr;
|
| 457 | };
|
| 458 |
|
| 459 | #define MMC_BOOT_XFER_MULTI_BLOCK 0
|
| 460 | #define MMC_BOOT_XFER_SINGLE_BLOCK 1
|
| 461 |
|
| 462 | struct mmc_boot_host
|
| 463 | {
|
| 464 | unsigned int mclk_rate;
|
| 465 | unsigned int pclk_rate;
|
| 466 | unsigned int ocr;
|
| 467 | unsigned int cmd_retry;
|
| 468 | unsigned int clk_enabled;
|
| 469 | };
|
| 470 |
|
| 471 |
|
| 472 | /* MACRO used to evoke regcomp */
|
| 473 | #define REGCOMP_CKRTN(regx, str, errhandle) \
|
| 474 | do { \
|
| 475 | if(regcomp(regx, str, REG_EXTENDED) != 0) { \
|
| 476 | printf("Error building regex: %s\n", str); \
|
| 477 | goto errhandle; \
|
| 478 | } \
|
| 479 | } while(0);
|
| 480 |
|
| 481 |
|
| 482 | #define GET_LWORD_FROM_BYTE(x) ((unsigned)*(x) | \
|
| 483 | ((unsigned)*(x+1) << 8) | \
|
| 484 | ((unsigned)*(x+2) << 16) | \
|
| 485 | ((unsigned)*(x+3) << 24))
|
| 486 |
|
| 487 | #define PUT_LWORD_TO_BYTE(x, y) do{*(x) = y & 0xff; \
|
| 488 | *(x+1) = (y >> 8) & 0xff; \
|
| 489 | *(x+2) = (y >> 16) & 0xff; \
|
| 490 | *(x+3) = (y >> 24) & 0xff; }while(0)
|
| 491 |
|
| 492 | #define GET_PAR_NUM_FROM_POS(x) (((x & 0x0000FF00) >> 8) + (x & 0x000000FF))
|
| 493 |
|
| 494 | /* Some useful define used to access the MBR/EBR table */
|
| 495 | #define BLOCK_SIZE 0x200
|
| 496 | #define TABLE_ENTRY_0 0x1BE
|
| 497 | #define TABLE_ENTRY_1 0x1CE
|
| 498 | #define TABLE_ENTRY_2 0x1DE
|
| 499 | #define TABLE_ENTRY_3 0x1EE
|
| 500 | #define TABLE_SIGNATURE 0x1FE
|
| 501 | #define TABLE_ENTRY_SIZE 0x010
|
| 502 |
|
| 503 | #define OFFSET_STATUS 0x00
|
| 504 | #define OFFSET_TYPE 0x04
|
| 505 | #define OFFSET_FIRST_SEC 0x08
|
| 506 | #define OFFSET_SIZE 0x0C
|
| 507 | #define COPYBUFF_SIZE (1024 * 16)
|
| 508 | #define BINARY_IN_TABLE_SIZE (16 * 512)
|
| 509 | #define MAX_FILE_ENTRIES 20
|
| 510 |
|
| 511 | #define MMC_BOOT_TYPE 0x48
|
| 512 | #define MMC_SYSTEM_TYPE 0x82
|
| 513 | #define MMC_USERDATA_TYPE 0x83
|
| 514 |
|
| 515 | #define MMC_RCA 2
|
| 516 |
|
| 517 | struct mbr_entry
|
| 518 | {
|
| 519 | unsigned dstatus;
|
| 520 | unsigned dtype ;
|
| 521 | unsigned dfirstsec;
|
| 522 | unsigned dsize;
|
| 523 | unsigned char name[64];
|
| 524 | };
|
| 525 |
|
| 526 | /* Can be used to unpack array of upto 32 bits data */
|
| 527 | #define UNPACK_BITS(array, start, len, size_of) \
|
| 528 | ({ \
|
| 529 | unsigned int indx = (start) / (size_of); \
|
| 530 | unsigned int offset = (start) % (size_of); \
|
| 531 | unsigned int mask = (((len)<(size_of))? 1<<(len):0) - 1; \
|
| 532 | unsigned int unpck = array[indx] >> offset; \
|
| 533 | unsigned int indx2 = ((start) + (len) - 1) / (size_of); \
|
| 534 | if(indx2 > indx) \
|
| 535 | unpck |= array[indx2] << ((size_of) - offset); \
|
| 536 | unpck & mask; \
|
| 537 | })
|
| 538 |
|
| 539 | #define MMC_BOOT_MAX_COMMAND_RETRY 10
|
| 540 | #define MMC_BOOT_RD_BLOCK_LEN 512
|
| 541 | #define MMC_BOOT_WR_BLOCK_LEN 512
|
| 542 |
|
| 543 | /* We have 12 32-bits FIFO registers */
|
| 544 | #define MMC_BOOT_MCI_FIFO_SIZE ( 12 * 4 )
|
| 545 |
|
| 546 | /*Need to put at proper place*/
|
| 547 | #define SDC1_CLK 19 /* Secure Digital Card clocks */
|
| 548 | #define SDC1_PCLK 20
|
| 549 | #define SDC2_CLK 21
|
| 550 | #define SDC2_PCLK 22
|
| 551 | #define SDC3_CLK 23
|
| 552 | #define SDC3_PCLK 24
|
| 553 | #define SDC4_CLK 25
|
| 554 | #define SDC4_PCLK 26
|
| 555 |
|
| 556 | #define MAX_PARTITIONS 64
|
| 557 |
|
| 558 | #define MMC_BOOT_CHECK_PATTERN 0xAA /* 10101010b */
|
| 559 |
|
| 560 | #define MMC_CLK_400KHZ 400000
|
| 561 | #define MMC_CLK_144KHZ 144000
|
| 562 | #define MMC_CLK_20MHZ 20000000
|
| 563 | #define MMC_CLK_25MHZ 25000000
|
| 564 | #define MMC_CLK_50MHZ 49152000
|
| 565 |
|
| 566 | #define MMC_CLK_ENABLE 1
|
| 567 | #define MMC_CLK_DISABLE 0
|
| 568 |
|
| 569 | #endif
|
| 570 |
|