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Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +05301/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <debug.h>
30#include <platform/iomap.h>
31#include <reg.h>
32#include <target.h>
33#include <platform.h>
34#include <uart_dm.h>
35#include <mmc.h>
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080036#include <platform/gpio.h>
37#include <dev/keys.h>
38#include <spmi_v2.h>
39#include <pm8x41.h>
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053040#include <board.h>
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080041#include <baseband.h>
42#include <hsusb.h>
43#include <platform/gpio.h>
44#include <platform/gpio.h>
45#include <platform/irqs.h>
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053046
47#define PMIC_ARB_CHANNEL_NUM 0
48#define PMIC_ARB_OWNER_ID 0
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080049#define TLMM_VOL_UP_BTN_GPIO 107
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053050
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080051static void set_sdc_power_ctrl(void);
52
53struct mmc_device *dev;
54
55static uint32_t mmc_pwrctl_base[] =
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053056 { MSM_SDC1_BASE, MSM_SDC2_BASE };
57
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080058static uint32_t mmc_sdhci_base[] =
59 { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE };
60
61static uint32_t mmc_sdc_pwrctl_irq[] =
62 { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ };
63
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053064void target_early_init(void)
65{
66#if WITH_DEBUG_UART
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080067 uart_dm_init(2, 0, BLSP1_UART1_BASE);
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053068#endif
69}
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080070
71void target_sdc_init()
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +053072{
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080073 struct mmc_config_data config;
74
75 /* Set drive strength & pull ctrl values */
76 set_sdc_power_ctrl();
77
78 config.bus_width = DATA_BUS_WIDTH_8BIT;
Aparna Mallavarapu53b09402014-03-26 14:46:43 +053079 config.max_clk_rate = MMC_CLK_177MHZ;
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080080
81 /* Try slot 1*/
82 config.slot = 1;
83 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
84 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
85 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
86 config.hs400_support = 0;
87
88 if (!(dev = mmc_init(&config))) {
89 /* Try slot 2 */
90 config.slot = 2;
Aparna Mallavarapu53b09402014-03-26 14:46:43 +053091 config.max_clk_rate = MMC_CLK_200MHZ;
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -080092 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
93 config.pwrctl_base = mmc_pwrctl_base[config.slot - 1];
94 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
95
96 if (!(dev = mmc_init(&config))) {
97 dprintf(CRITICAL, "mmc init failed!");
98 ASSERT(0);
99 }
100 }
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530101}
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800102
103void *target_mmc_device()
104{
105 return (void *) dev;
106}
107
108/* Return 1 if vol_up pressed */
109static int target_volume_up()
110{
111 uint8_t status = 0;
112
113 gpio_tlmm_config(TLMM_VOL_UP_BTN_GPIO, 0, GPIO_INPUT, GPIO_PULL_UP, GPIO_2MA, GPIO_ENABLE);
114
115 /* Wait for the gpio config to take effect - debounce time */
116 thread_sleep(10);
117
118 /* Get status of GPIO */
119 status = gpio_status(TLMM_VOL_UP_BTN_GPIO);
120
121 /* Active low signal. */
122 return !status;
123}
124
125/* Return 1 if vol_down pressed */
126uint32_t target_volume_down()
127{
128 /* Volume down button tied in with PMIC RESIN. */
129 return pm8x41_resin_status();
130}
131
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530132static void target_keystatus()
133{
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800134 keys_init();
135
136 if(target_volume_down())
137 keys_post_event(KEY_VOLUMEDOWN, 1);
138
139 if(target_volume_up())
140 keys_post_event(KEY_VOLUMEUP, 1);
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530141}
142
143void target_init(void)
144{
145 uint32_t base_addr;
146 uint8_t slot;
147
148 dprintf(INFO, "target_init()\n");
149
150 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
151
152 target_keystatus();
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800153 set_sdc_power_ctrl();
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530154
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800155 target_sdc_init();
156 if (partition_read_table())
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530157 {
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800158 dprintf(CRITICAL, "Error reading the partition table info\n");
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530159 ASSERT(0);
160 }
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530161}
162
163void target_serialno(unsigned char *buf)
164{
165 uint32_t serialno;
166 if (target_is_emmc_boot()) {
167 serialno = mmc_get_psn();
168 snprintf((char *)buf, 13, "%x", serialno);
169 }
170}
171
172unsigned board_machtype(void)
173{
Aparna Mallavarapu7cc5a792014-02-27 21:49:59 -0800174 return LINUX_MACHTYPE_UNKNOWN;
175}
176
177unsigned check_reboot_mode(void)
178{
179 uint32_t restart_reason = 0;
180
181 /* Read reboot reason and scrub it */
182 restart_reason = readl(RESTART_REASON_ADDR);
183 writel(0x00, RESTART_REASON_ADDR);
184
185 return restart_reason;
186}
187
188void reboot_device(unsigned reboot_reason)
189{
190 writel(reboot_reason, RESTART_REASON_ADDR);
191
192 /* Configure PMIC for warm reset */
193 pm8x41_reset_configure(PON_PSHOLD_WARM_RESET);
194
195 /* Drop PS_HOLD for MSM */
196 writel(0x00, MPM2_MPM_PS_HOLD);
197
198 mdelay(5000);
199
200 dprintf(CRITICAL, "Rebooting failed\n");
201}
202
203/* Detect the target type */
204void target_detect(struct board_data *board)
205{
206 /*
207 * already fill the board->target on board.c
208 */
209}
210
211void target_baseband_detect(struct board_data *board)
212{
213 uint32_t platform;
214
215 platform = board->platform;
216 switch(platform)
217 {
218 case MSM8916:
219 board->baseband = BASEBAND_MSM;
220 break;
221 default:
222 dprintf(CRITICAL, "Platform type: %u is not supported\n", platform);
223 ASSERT(0);
224 };
225}
226
227unsigned target_baseband()
228{
229 return board_baseband();
230}
231
232int emmc_recovery_init(void)
233{
234 return _emmc_recovery_init();
235}
236
237static void set_sdc_power_ctrl()
238{
239 /* Drive strength configs for sdc pins */
240 struct tlmm_cfgs sdc1_hdrv_cfg[] =
241 {
242 { SDC1_CLK_HDRV_CTL_OFF, TLMM_CUR_VAL_16MA, TLMM_HDRV_MASK },
243 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
244 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_6MA, TLMM_HDRV_MASK },
245 };
246
247 /* Pull configs for sdc pins */
248 struct tlmm_cfgs sdc1_pull_cfg[] =
249 {
250 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
251 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
252 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
253 };
254
255 /* Set the drive strength & pull control values */
256 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
257 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
258}
259
260void target_usb_init(void)
261{
262 uint32_t val;
263
264 /* Select and enable external configuration with USB PHY */
265 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
266
267 /* Enable sess_vld */
268 val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
269 writel(val, USB_GENCONFIG_2);
270
271 /* Enable external vbus configuration in the LINK */
272 val = readl(USB_USBCMD);
273 val |= SESS_VLD_CTRL;
274 writel(val, USB_USBCMD);
275}
276
277void target_usb_stop(void)
278{
279 /* Disable VBUS mimicing in the controller. */
280 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
281}
282
283
284void target_uninit(void)
285{
286 mmc_put_card_to_sleep(dev);
287 sdhci_mode_disable(&dev->host);
288}
289
290/* Do any target specific intialization needed before entering fastboot mode */
291void target_fastboot_init(void)
292{
293 /* Set the BOOT_DONE flag in PM8916 */
294 pm8x41_set_boot_done();
Aparna Mallavarapufe1f3d12013-10-19 15:05:30 +0530295}