Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
Deepa Dinamani | 1e09494 | 2012-10-30 15:49:02 -0700 | [diff] [blame] | 2 | * |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
Deepa Dinamani | 1e09494 | 2012-10-30 15:49:02 -0700 | [diff] [blame] | 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
| 12 | * * Neither the name of The Linux Foundation nor the names of its |
| 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
| 28 | |
| 29 | #ifndef _PLATFORM_MSMCOPPER_IOMAP_H_ |
| 30 | #define _PLATFORM_MSMCOPPER_IOMAP_H_ |
| 31 | |
Neeti Desai | 13e688d | 2012-08-22 16:30:55 -0700 | [diff] [blame] | 32 | #define MSM_IOMAP_BASE 0xF9000000 |
| 33 | #define MSM_IOMAP_END 0xFEFFFFFF |
| 34 | |
Deepa Dinamani | 81eddd5 | 2012-05-31 11:18:50 -0700 | [diff] [blame] | 35 | #define SDRAM_START_ADDR 0x00000000 |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 36 | #define SDRAM_SEC_BANK_START_ADDR 0x10000000 |
Deepa Dinamani | 81eddd5 | 2012-05-31 11:18:50 -0700 | [diff] [blame] | 37 | |
| 38 | #define MSM_SHARED_BASE 0x0FA00000 |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 39 | |
Neeti Desai | 120b55d | 2012-08-20 17:15:56 -0700 | [diff] [blame] | 40 | #define RPM_MSG_RAM_BASE 0xFC42B000 |
Channagoud Kadabi | 8c8587f | 2013-02-08 12:46:09 -0800 | [diff] [blame] | 41 | #define SYSTEM_IMEM_BASE 0xFE800000 |
Channagoud Kadabi | adb0e16 | 2013-03-19 10:49:24 -0700 | [diff] [blame] | 42 | #define MSM_SHARED_IMEM_BASE 0xFE805000 |
Amol Jadi | baee474 | 2013-03-18 15:35:05 -0700 | [diff] [blame] | 43 | |
Pavel Nedev | a4c9d3a | 2013-05-15 14:42:34 +0300 | [diff] [blame] | 44 | #define RESTART_REASON_ADDR (RPM_MSG_RAM_BASE + 0x65C) |
| 45 | #define RESTART_REASON_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0x65C) |
| 46 | #define DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0x0) |
| 47 | #define EMERGENCY_DLOAD_MODE_ADDR_V2 (MSM_SHARED_IMEM_BASE + 0xFE0) |
Pavel Nedev | 0351149 | 2013-03-08 19:05:32 -0800 | [diff] [blame] | 48 | |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 49 | #define KPSS_BASE 0xF9000000 |
| 50 | |
| 51 | #define MSM_GIC_DIST_BASE KPSS_BASE |
| 52 | #define MSM_GIC_CPU_BASE (KPSS_BASE + 0x2000) |
| 53 | #define APCS_KPSS_ACS_BASE (KPSS_BASE + 0x00008000) |
| 54 | #define APCS_APC_KPSS_PLL_BASE (KPSS_BASE + 0x0000A000) |
| 55 | #define APCS_KPSS_CFG_BASE (KPSS_BASE + 0x00010000) |
| 56 | #define APCS_KPSS_WDT_BASE (KPSS_BASE + 0x00017000) |
Deepa Dinamani | 1f01f19 | 2012-08-10 16:04:10 -0700 | [diff] [blame] | 57 | #define KPSS_APCS_QTMR_AC_BASE (KPSS_BASE + 0x00020000) |
| 58 | #define KPSS_APCS_F0_QTMR_V1_BASE (KPSS_BASE + 0x00021000) |
| 59 | #define QTMR_BASE KPSS_APCS_F0_QTMR_V1_BASE |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 60 | |
| 61 | #define PERIPH_SS_BASE 0xF9800000 |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 62 | |
| 63 | #define MSM_SDC1_BAM_BASE (PERIPH_SS_BASE + 0x00004000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 64 | #define MSM_SDC1_BASE (PERIPH_SS_BASE + 0x00024000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 65 | #define MSM_SDC1_DML_BASE (PERIPH_SS_BASE + 0x00024800) |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 66 | #define MSM_SDC1_SDHCI_BASE (PERIPH_SS_BASE + 0x00024900) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 67 | #define MSM_SDC3_BAM_BASE (PERIPH_SS_BASE + 0x00044000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 68 | #define MSM_SDC3_BASE (PERIPH_SS_BASE + 0x00064000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 69 | #define MSM_SDC3_DML_BASE (PERIPH_SS_BASE + 0x00064800) |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 70 | #define MSM_SDC3_SDHCI_BASE (PERIPH_SS_BASE + 0x00064900) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 71 | #define MSM_SDC2_BAM_BASE (PERIPH_SS_BASE + 0x00084000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 72 | #define MSM_SDC2_BASE (PERIPH_SS_BASE + 0x000A4000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 73 | #define MSM_SDC2_DML_BASE (PERIPH_SS_BASE + 0x000A4800) |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 74 | #define MSM_SDC2_SDHCI_BASE (PERIPH_SS_BASE + 0x000A4900) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 75 | #define MSM_SDC4_BAM_BASE (PERIPH_SS_BASE + 0x000C4000) |
Deepa Dinamani | ca5ad85 | 2012-05-07 18:19:47 -0700 | [diff] [blame] | 76 | #define MSM_SDC4_BASE (PERIPH_SS_BASE + 0x000E4000) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 77 | #define MSM_SDC4_DML_BASE (PERIPH_SS_BASE + 0x000E4800) |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 78 | #define MSM_SDC4_SDHCI_BASE (PERIPH_SS_BASE + 0x000E4900) |
Deepa Dinamani | 07e6687 | 2012-06-29 18:32:05 -0700 | [diff] [blame] | 79 | |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 80 | #define BLSP1_UART0_BASE (PERIPH_SS_BASE + 0x0011D000) |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 81 | #define BLSP1_UART1_BASE (PERIPH_SS_BASE + 0x0011E000) |
| 82 | #define BLSP1_UART2_BASE (PERIPH_SS_BASE + 0x0011F000) |
| 83 | #define BLSP1_UART3_BASE (PERIPH_SS_BASE + 0x00120000) |
| 84 | #define BLSP1_UART4_BASE (PERIPH_SS_BASE + 0x00121000) |
| 85 | #define BLSP1_UART5_BASE (PERIPH_SS_BASE + 0x00122000) |
Deepa Dinamani | 26e9326 | 2012-05-21 17:35:14 -0700 | [diff] [blame] | 86 | #define MSM_USB_BASE (PERIPH_SS_BASE + 0x00255000) |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 87 | |
| 88 | #define CLK_CTL_BASE 0xFC400000 |
Deepa Dinamani | 1e09494 | 2012-10-30 15:49:02 -0700 | [diff] [blame] | 89 | |
| 90 | #define GCC_WDOG_DEBUG (CLK_CTL_BASE + 0x00001780) |
| 91 | |
Deepa Dinamani | 0687ecd | 2012-08-10 16:00:26 -0700 | [diff] [blame] | 92 | #define USB_HS_BCR (CLK_CTL_BASE + 0x480) |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 93 | |
Deepa Dinamani | c2a9b36 | 2012-02-23 15:15:54 -0800 | [diff] [blame] | 94 | #define SPMI_BASE 0xFC4C0000 |
| 95 | #define SPMI_GENI_BASE (SPMI_BASE + 0xA000) |
| 96 | #define SPMI_PIC_BASE (SPMI_BASE + 0xB000) |
| 97 | |
Deepa Dinamani | b9a5720 | 2012-12-20 18:05:11 -0800 | [diff] [blame] | 98 | #define MSM_CE2_BAM_BASE 0xFD444000 |
| 99 | #define MSM_CE2_BASE 0xFD45A000 |
Eugene Yasman | a0d1812 | 2013-02-26 13:23:05 +0200 | [diff] [blame] | 100 | #define USB2_PHY_SEL 0xFD4AB000 |
Deepa Dinamani | b9a5720 | 2012-12-20 18:05:11 -0800 | [diff] [blame] | 101 | |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame] | 102 | #define TLMM_BASE_ADDR 0xFD510000 |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 103 | #define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10) |
| 104 | #define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10) |
| 105 | |
Joel King | 46d2a45 | 2013-02-13 18:35:21 -0800 | [diff] [blame] | 106 | #define MPM2_MPM_CTRL_BASE 0xFC4A1000 |
| 107 | #define MPM2_MPM_PS_HOLD 0xFC4AB000 |
| 108 | #define MPM2_MPM_SLEEP_TIMETICK_COUNT_VAL 0xFC4A3000 |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 109 | |
sundarajan srinivasan | 6aaa50c | 2013-02-27 14:18:57 -0800 | [diff] [blame] | 110 | /* CE 1 */ |
| 111 | #define GCC_CE1_BCR (CLK_CTL_BASE + 0x1040) |
| 112 | #define GCC_CE1_CMD_RCGR (CLK_CTL_BASE + 0x1050) |
| 113 | #define GCC_CE1_CFG_RCGR (CLK_CTL_BASE + 0x1054) |
| 114 | #define GCC_CE1_CBCR (CLK_CTL_BASE + 0x1044) |
| 115 | #define GCC_CE1_AXI_CBCR (CLK_CTL_BASE + 0x1048) |
| 116 | #define GCC_CE1_AHB_CBCR (CLK_CTL_BASE + 0x104C) |
| 117 | |
Deepa Dinamani | 32bfad0 | 2012-11-02 12:15:05 -0700 | [diff] [blame] | 118 | /* CE 2 */ |
| 119 | #define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080) |
| 120 | #define GCC_CE2_CMD_RCGR (CLK_CTL_BASE + 0x1090) |
| 121 | #define GCC_CE2_CFG_RCGR (CLK_CTL_BASE + 0x1094) |
| 122 | #define GCC_CE2_CBCR (CLK_CTL_BASE + 0x1084) |
| 123 | #define GCC_CE2_AXI_CBCR (CLK_CTL_BASE + 0x1088) |
| 124 | #define GCC_CE2_AHB_CBCR (CLK_CTL_BASE + 0x108C) |
| 125 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 126 | /* GPLL */ |
| 127 | #define GPLL0_STATUS (CLK_CTL_BASE + 0x001C) |
| 128 | #define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480) |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame] | 129 | #define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484) |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 130 | |
| 131 | /* SDCC */ |
| 132 | #define SDCC1_BCR (CLK_CTL_BASE + 0x4C0) /* block reset */ |
| 133 | #define SDCC1_APPS_CBCR (CLK_CTL_BASE + 0x4C4) /* branch control */ |
| 134 | #define SDCC1_AHB_CBCR (CLK_CTL_BASE + 0x4C8) |
| 135 | #define SDCC1_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x4CC) |
| 136 | #define SDCC1_CMD_RCGR (CLK_CTL_BASE + 0x4D0) /* cmd */ |
| 137 | #define SDCC1_CFG_RCGR (CLK_CTL_BASE + 0x4D4) /* cfg */ |
| 138 | #define SDCC1_M (CLK_CTL_BASE + 0x4D8) /* m */ |
| 139 | #define SDCC1_N (CLK_CTL_BASE + 0x4DC) /* n */ |
| 140 | #define SDCC1_D (CLK_CTL_BASE + 0x4E0) /* d */ |
| 141 | |
Channagoud Kadabi | 5a612c7 | 2013-06-04 13:28:14 -0700 | [diff] [blame^] | 142 | /* SDCC2 */ |
| 143 | #define SDCC2_BCR (CLK_CTL_BASE + 0x500) /* block reset */ |
| 144 | #define SDCC2_APPS_CBCR (CLK_CTL_BASE + 0x504) /* branch control */ |
| 145 | #define SDCC2_AHB_CBCR (CLK_CTL_BASE + 0x508) |
| 146 | #define SDCC2_INACTIVITY_TIMER_CBCR (CLK_CTL_BASE + 0x50C) |
| 147 | #define SDCC2_CMD_RCGR (CLK_CTL_BASE + 0x510) /* cmd */ |
| 148 | #define SDCC2_CFG_RCGR (CLK_CTL_BASE + 0x514) /* cfg */ |
| 149 | #define SDCC2_M (CLK_CTL_BASE + 0x518) /* m */ |
| 150 | #define SDCC2_N (CLK_CTL_BASE + 0x51C) /* n */ |
| 151 | #define SDCC2_D (CLK_CTL_BASE + 0x520) /* d */ |
| 152 | |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 153 | /* UART */ |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame] | 154 | #define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4) |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 155 | #define BLSP2_AHB_CBCR (CLK_CTL_BASE + 0x944) |
Neeti Desai | ac01127 | 2012-08-29 18:24:54 -0700 | [diff] [blame] | 156 | #define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704) |
| 157 | #define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C) |
| 158 | #define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710) |
| 159 | #define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714) |
| 160 | #define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718) |
| 161 | #define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C) |
Amol Jadi | 29f9503 | 2012-06-22 12:52:54 -0700 | [diff] [blame] | 162 | |
| 163 | /* USB */ |
| 164 | #define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484) |
| 165 | #define USB_HS_AHB_CBCR (CLK_CTL_BASE + 0x488) |
| 166 | #define USB_HS_SYSTEM_CMD_RCGR (CLK_CTL_BASE + 0x490) |
| 167 | #define USB_HS_SYSTEM_CFG_RCGR (CLK_CTL_BASE + 0x494) |
| 168 | |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 169 | /* I2C */ |
| 170 | #define BLSP2_QUP5_I2C_APPS_CBCR (CLK_CTL_BASE + 0xB88) |
| 171 | |
| 172 | #define BLSP_QUP_BASE(blsp_id, qup_id) ((blsp_id == 1) ? \ |
Channagoud Kadabi | 1106913 | 2013-03-28 11:51:19 -0700 | [diff] [blame] | 173 | (PERIPH_SS_BASE + 0x00123000 \ |
Channagoud Kadabi | 634ac6d | 2012-12-12 18:13:56 -0800 | [diff] [blame] | 174 | + (qup_id * 0x1000)) :\ |
| 175 | (PERIPH_SS_BASE + 0x00163000 + \ |
| 176 | (qup_id * 0x1000))) |
Siddhartha Agrawal | 7ac6d51 | 2013-01-22 18:39:50 -0800 | [diff] [blame] | 177 | |
Siddhartha Agrawal | acdaf5b | 2013-01-22 18:14:53 -0800 | [diff] [blame] | 178 | #define MSM_MMSS_CLK_CTL_BASE 0xFD8C0000 |
Siddhartha Agrawal | 7ac6d51 | 2013-01-22 18:39:50 -0800 | [diff] [blame] | 179 | |
| 180 | #define MIPI_DSI_BASE (0xFD922800) |
| 181 | #define REG_DSI(off) (MIPI_DSI_BASE + 0x04 + (off)) |
| 182 | |
| 183 | #define MDP_BASE (0xfd900000) |
| 184 | #define REG_MDP(off) (MDP_BASE + (off)) |
| 185 | |
Channagoud Kadabi | 8495f88 | 2013-04-02 11:20:28 -0700 | [diff] [blame] | 186 | /* DRV strength for sdcc */ |
| 187 | #define SDC1_HDRV_PULL_CTL (TLMM_BASE_ADDR + 0x00002044) |
Channagoud Kadabi | 4fb29e9 | 2013-04-05 11:32:11 -0700 | [diff] [blame] | 188 | |
| 189 | /* SDHCI */ |
| 190 | #define SDCC_MCI_HC_MODE (PERIPH_SS_BASE + 0x00024078) |
| 191 | #define SDCC_HC_PWRCTL_MASK_REG (PERIPH_SS_BASE + 0x000240E0) |
| 192 | #define SDCC_HC_PWRCTL_CTL_REG (PERIPH_SS_BASE + 0x000240E8) |
Deepa Dinamani | 7d6c897 | 2011-12-14 15:16:56 -0800 | [diff] [blame] | 193 | #endif |