blob: 3e2ea2f667ed9adae1d7eadb1764f66649ab9ec1 [file] [log] [blame]
Brian Swetland2500aa12009-01-01 04:33:55 -08001/*
2 * Copyright (c) 2008, Google Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in
12 * the documentation and/or other materials provided with the
13 * distribution.
14 * * Neither the name of Google, Inc. nor the names of its contributors
15 * may be used to endorse or promote products derived from this
16 * software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
25 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <debug.h>
33#include <arch/arm.h>
34#include <reg.h>
35#include <kernel/thread.h>
36#include <platform/interrupts.h>
37
38#include <platform/irqs.h>
39#include <platform/iomap.h>
40
41#define VIC_REG(off) (MSM_VIC_BASE + (off))
42
43#define VIC_INT_SELECT0 VIC_REG(0x0000) /* 1: FIQ, 0: IRQ */
44#define VIC_INT_SELECT1 VIC_REG(0x0004) /* 1: FIQ, 0: IRQ */
45#define VIC_INT_EN0 VIC_REG(0x0010)
46#define VIC_INT_EN1 VIC_REG(0x0014)
47#define VIC_INT_ENCLEAR0 VIC_REG(0x0020)
48#define VIC_INT_ENCLEAR1 VIC_REG(0x0024)
49#define VIC_INT_ENSET0 VIC_REG(0x0030)
50#define VIC_INT_ENSET1 VIC_REG(0x0034)
51#define VIC_INT_TYPE0 VIC_REG(0x0040) /* 1: EDGE, 0: LEVEL */
52#define VIC_INT_TYPE1 VIC_REG(0x0044) /* 1: EDGE, 0: LEVEL */
53#define VIC_INT_POLARITY0 VIC_REG(0x0050) /* 1: NEG, 0: POS */
54#define VIC_INT_POLARITY1 VIC_REG(0x0054) /* 1: NEG, 0: POS */
55#define VIC_NO_PEND_VAL VIC_REG(0x0060)
56#define VIC_INT_MASTEREN VIC_REG(0x0064) /* 1: IRQ, 2: FIQ */
57#define VIC_PROTECTION VIC_REG(0x006C) /* 1: ENABLE */
58#define VIC_CONFIG VIC_REG(0x0068) /* 1: USE ARM1136 VIC */
59#define VIC_IRQ_STATUS0 VIC_REG(0x0080)
60#define VIC_IRQ_STATUS1 VIC_REG(0x0084)
61#define VIC_FIQ_STATUS0 VIC_REG(0x0090)
62#define VIC_FIQ_STATUS1 VIC_REG(0x0094)
63#define VIC_RAW_STATUS0 VIC_REG(0x00A0)
64#define VIC_RAW_STATUS1 VIC_REG(0x00A4)
65#define VIC_INT_CLEAR0 VIC_REG(0x00B0)
66#define VIC_INT_CLEAR1 VIC_REG(0x00B4)
67#define VIC_SOFTINT0 VIC_REG(0x00C0)
68#define VIC_SOFTINT1 VIC_REG(0x00C4)
69#define VIC_IRQ_VEC_RD VIC_REG(0x00D0) /* pending int # */
70#define VIC_IRQ_VEC_PEND_RD VIC_REG(0x00D4) /* pending vector addr */
71#define VIC_IRQ_VEC_WR VIC_REG(0x00D8)
72#define VIC_IRQ_IN_SERVICE VIC_REG(0x00E0)
73#define VIC_IRQ_IN_STACK VIC_REG(0x00E4)
74#define VIC_TEST_BUS_SEL VIC_REG(0x00E8)
75
76struct ihandler {
77 int_handler func;
78 void *arg;
79};
80
81static struct ihandler handler[NR_IRQS];
82
83void platform_init_interrupts(void)
84{
85 writel(0xffffffff, VIC_INT_CLEAR0);
86 writel(0xffffffff, VIC_INT_CLEAR1);
87 writel(0, VIC_INT_SELECT0);
88 writel(0, VIC_INT_SELECT1);
89 writel(0xffffffff, VIC_INT_TYPE0);
90 writel(0xffffffff, VIC_INT_TYPE1);
91 writel(0, VIC_CONFIG);
92 writel(1, VIC_INT_MASTEREN);
93}
94
95enum handler_return platform_irq(struct arm_iframe *frame)
96{
97 unsigned num;
98 enum handler_return ret;
99 num = readl(VIC_IRQ_VEC_RD);
100 num = readl(VIC_IRQ_VEC_PEND_RD);
101 if (num > NR_IRQS)
102 return 0;
103 writel(1 << (num & 31), (num > 31) ? VIC_INT_CLEAR1 : VIC_INT_CLEAR0);
104 ret = handler[num].func(handler[num].arg);
105 writel(0, VIC_IRQ_VEC_WR);
106 return ret;
107}
108
109void platform_fiq(struct arm_iframe *frame)
110{
111 PANIC_UNIMPLEMENTED;
112}
113
114status_t mask_interrupt(unsigned int vector)
115{
116 unsigned reg = (vector > 31) ? VIC_INT_ENCLEAR1 : VIC_INT_ENCLEAR0;
117 unsigned bit = 1 << (vector & 31);
118 writel(bit, reg);
119 return 0;
120}
121
122status_t unmask_interrupt(unsigned int vector)
123{
124 unsigned reg = (vector > 31) ? VIC_INT_ENSET1 : VIC_INT_ENSET0;
125 unsigned bit = 1 << (vector & 31);
126 writel(bit, reg);
127 return 0;
128}
129
130void register_int_handler(unsigned int vector, int_handler func, void *arg)
131{
132 if (vector >= NR_IRQS)
133 return;
134
135 enter_critical_section();
136 handler[vector].func = func;
137 handler[vector].arg = arg;
138 exit_critical_section();
139}
140